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1. 发明授权

US06674798B2 Motion vector detecting device capable of accommodating a plurality of predictive modes 失效
标题翻译：能够适应多种预测模式的运动矢量检测装置
公开(公告)号：US06674798B2
公开(公告)日：2004-01-06
申请号：US09961139
申请日：2001-09-24
申请人： Kazuya Ishihara , Shinichi Uramoto , Shinichi Nakagawa , Tetsuya Matsumura , Satoshi Kumaki , Atsuo Hanami
发明人： Kazuya Ishihara , Shinichi Uramoto , Shinichi Nakagawa , Tetsuya Matsumura , Satoshi Kumaki , Atsuo Hanami
IPC分类号： H04N736
CPC分类号： H04N5/145 , G06T7/223 , G06T7/231 , G06T2207/10016 , H04N19/433 , H04N19/51
摘要： A processor array includes element processors which are arranged in a matrix in correspondence to respective pixels of a template block, which is a current picture image pixel block. Each element processor stores pixel data of a search window block, which is a corresponding reference picture image pixel block, and obtains an evaluation function value component with respect to the template block pixel data. A summing part sorts the evaluation function components received from the respective element processors of the processor array in accordance with a plurality of predictive modes and sums up the components for the respective sorts, for forming evaluation function values for the respective predictive modes. A comparison part compares the evaluation function values received from the summing part for each predictive mode, to decide a displacement vector providing the best similarity as a motion vector for each predictive mode. It is possible to simultaneously detect motion vectors according to a plurality of predictive modes. It is possible to detect motion vectors employed for moving image predictive compensation in accordance with a plurality of predictive modes at a high speed with a small hardware volume.
摘要翻译：处理器阵列包括对应于作为当前图像像素块的模板块的各个像素的矩阵排列的元件处理器。每个元素处理器存储作为对应的参考图像像素块的搜索窗口块的像素数据，并获得关于模板块像素数据的评估函数值分量。求和部分根据多种预测模式对从处理器阵列的相应元件处理器接收的评估函数分量进行排序，并对各种类型的组件求和，以形成各个预测模式的评估函数值。比较部分比较从每个预测模式的求和部分接收的评估函数值，以确定提供最佳相似度的位移矢量作为每个预测模式的运动矢量。可以根据多种预测模式同时检测运动矢量。根据具有小硬件体积的高速的多种预测模式，可以检测用于运动图像预测补偿的运动矢量。

2. 发明授权

US6125432A Image process apparatus having a storage device with a plurality of banks storing pixel data, and capable of precharging one bank while writing to another bank 失效
标题翻译：具有存储装置的图像处理装置具有存储像素数据的多个存储体，并且能够在写入另一个存储体时对一个存储体进行预充电
公开(公告)号：US6125432A
公开(公告)日：2000-09-26
申请号：US903348
申请日：1997-07-30
申请人： Atsuo Hanami , Shinichi Nakagawa , Tetsuya Matsumura , Hiroshi Segawa , Kazuya Ishihara , Satoshi Kumaki
发明人： Atsuo Hanami , Shinichi Nakagawa , Tetsuya Matsumura , Hiroshi Segawa , Kazuya Ishihara , Satoshi Kumaki
IPC分类号： G06F12/06 , G06F12/00 , G06T1/60 , G09G5/39 , G09G5/399 , G11C11/401 , G11C11/407 , H04N7/50 , G06F12/02
CPC分类号： G09G5/39 , H04N19/423 , H04N19/61 , G09G2340/02 , G09G2360/123 , G09G5/399
摘要： Screen data consists of two sets of field data. Each set of field data is divided into a plurality of data blocks which has four rows of pixel data corresponding to four rows of pixels vertically arranged. Every data block corresponding to one set of field data is stored in the first bank (bank0) of a frame buffer memory while that corresponding to the other set of field data is stored in the second bank (bank1). One row address is assigned to each data block. Bank1 is precharged while bank0 is in a write operation and vice versa in order to carry out the precharging operation and the write operation concurrently, so that the pixel data can be transferred at a high data transfer rate and each of two sets of field data can be transferred independently.
摘要翻译：屏幕数据由两组现场数据组成。每组场数据被分成多个数据块，其具有与垂直排列的四行像素对应的四行像素数据。对应于一组场数据的每个数据块被存储在帧缓冲存储器的第一存储体（存储体0）中，而与另一组场数据相对应的数据块存储在第二存储体（存储体1）中）。一行地址分配给每个数据块。 Bank1被预充电，而bank0处于写操作，反之亦然，以便同时执行预充电操作和写操作，使得可以以高数据传输速率传输像素数据，并且两组现场数据可以独立转让

3. 发明授权

US5651123A Program execution control device having addressability in accordance with M series pseudo-random number sequence 失效
标题翻译：具有符合M系列伪随机数序列的寻址能力的程序执行控制装置
公开(公告)号：US5651123A
公开(公告)日：1997-07-22
申请号：US460947
申请日：1995-06-05
申请人： Shinichi Nakagawa , Kazuya Ishihara , Satoshi Kumaki , Atsuo Hanami , Hiroshi Segawa , Tetsuya Matsumura
发明人： Shinichi Nakagawa , Kazuya Ishihara , Satoshi Kumaki , Atsuo Hanami , Hiroshi Segawa , Tetsuya Matsumura
IPC分类号： G06F9/32 , G06F9/38 , G06F9/30
CPC分类号： G06F9/3802 , G06F9/321 , G06F2207/7219
摘要： Instructions of a program are stored at addresses sequentially designated in accordance with an M series pseudo-random number sequence in an instruction memory in the order of program addresses. A pseudo-random number program counter has a feedback shift register for generating the same M series pseudo-random number sequence and applies an address of an instruction to be read from the instruction memory to the instruction memory based on a generated pseudo-random number, and a jump address and a select signal from an instruction decoder. As a result, instructions are read from the instruction memory and executed in the order of program addresses. The feedback shift register can be implemented as a small-scale circuit and operable at high speed.
摘要翻译：程序的指令按照程序地址的顺序存储在指令存储器中根据M系列伪随机数序列顺序指定的地址处。伪随机数程序计数器具有用于产生相同M系列伪随机数序列的反馈移位寄存器，并且基于生成的伪随机数将从指令存储器读出的指令的地址应用于指令存储器，以及来自指令解码器的跳转地址和选择信号。结果，从指令存储器中读取指令并按程序地址的顺序执行。反馈移位寄存器可以实现为小规模电路并且可以高速运行。

4. 发明授权

US5539401A Variable-length code table and variable-length coding device 失效
标题翻译：可变长度码表和可变长度编码装置
公开(公告)号：US5539401A
公开(公告)日：1996-07-23
申请号：US483035
申请日：1995-06-07
申请人： Satoshi Kumaki , Kazuya Ishihara , Shinichi Nakagawa , Atsuo Hanami
发明人： Satoshi Kumaki , Kazuya Ishihara , Shinichi Nakagawa , Atsuo Hanami
IPC分类号： H04N19/60 , G06T9/00 , H03M7/42 , H04N1/41 , H04N1/411 , H04N19/423 , H04N19/426 , H04N19/625 , H04N19/93 , H03M7/40
CPC分类号： H03M7/42 , G06T9/005 , H04N1/411
摘要： A variable-length code table, which is used for producing a variable-length code from data formed of one set of first and second equal-length components, stores at an address uniquely assigned by the one set of the equal-length components a corresponding variable-length code and a code length of the variable-length code. Combination of the first and second equal-length components is preselected such that the maximum value of the absolute value of the first equal-length component increases as the absolute value of the second equal-length component combined therewith decreases. The second equal-length components are classified into a plurality of classes in accordance with the magnitude of the absolute value. Each address includes a first region having a value and a length uniquely specified based on the class including the second equal-length component, a second region storing the first equal-length component, and a third region storing the second equal-length component, and is constructed to have a fixed length as a whole. Region lengths of the second and third regions are determined correspondingly to the class including the second equal-length component, and each are specifically determined to have the minimum value required for storing the maximum values of the absolute values of the first and second equal-length components of the combinations of the equal-length components included in the corresponding class.
摘要翻译：用于从由一组第一和第二等长分量形成的数据产生可变长度码的可变长度码表存储在由一组等长分量唯一分配的地址a相应的地址可变长度代码和可变长度代码的代码长度。预先选择第一和第二等长分量的组合，使得第一等长分量的绝对值的最大值随着与其组合的第二等长分量的绝对值减小而增加。第二等长分量根据绝对值的大小被分类为多个类别。每个地址包括具有基于包括第二等长分量的类别唯一地指定的值和长度的第一区域，存储第一等长分量的第二区域和存储第二等长分量的第三区域，以及被构造为具有整体的固定长度。对应于包括第二等长分量的类别确定第二和第三区域的区域长度，并且每个具体确定为具有存储第一和第二等长度的绝对值的最大值所需的最小值相应类别中包括的等长分量组合的组成部分。

5. 发明授权

US5740088A Control signal generating device generating various control signals using storage unit having small storage capacity 失效
标题翻译：控制信号发生装置利用具有小存储容量的存储单元产生各种控制信号
公开(公告)号：US5740088A
公开(公告)日：1998-04-14
申请号：US530497
申请日：1995-09-19
申请人： Shinichi Nakagawa , Kiyofumi Kawamoto , Kazuya Ishihara , Satoshi Kumaki , Atsuo Hanami
发明人： Shinichi Nakagawa , Kiyofumi Kawamoto , Kazuya Ishihara , Satoshi Kumaki , Atsuo Hanami
IPC分类号： H03K3/84 , G05B19/07 , G06F7/00 , G06F7/58 , H04L7/00 , G06F1/02
CPC分类号： G05B19/07 , G06F7/00
摘要： A first pseudo random number generating circuit sequentially provides an output signal to a matching detecting circuit in response to a clock signal. A second pseudo random number generating circuit generates an initial value, and then, sequentially provides an output signal to a storage device in response to an output signal from the matching detecting circuit and the clock signal. Data with the output signal as an address is provided as an output signal from the storage device. When the matching detecting circuit detects matching between the output signals, the matching detecting circuit provides the output signals to the second pseudo random number generating circuit and an AND logic circuit. As described above, when the output signal of the matching detecting circuit is provided, the output signals from the storage device are provided as respective output control signals.
摘要翻译：第一伪随机数产生电路响应于时钟信号顺序地向匹配检测电路提供输出信号。第二伪随机数发生电路产生初始值，然后响应于来自匹配检测电路的输出信号和时钟信号，向存储装置依次提供输出信号。以输出信号作为地址的数据作为来自存储装置的输出信号提供。当匹配检测电路检测输出信号之间的匹配时，匹配检测电路将输出信号提供给第二伪随机数产生电路和与逻辑电路。如上所述，当提供匹配检测电路的输出信号时，来自存储装置的输出信号被提供为相应的输出控制信号。

6. 发明授权

US5600813A Method of and circuit for generating zigzag addresses 失效
标题翻译：用于生成之字形地址的方法和电路
公开(公告)号：US5600813A
公开(公告)日：1997-02-04
申请号：US15374
申请日：1993-02-09
申请人： Shinichi Nakagawa , Kazuya Ishihara , Satoshi Kumaki
发明人： Shinichi Nakagawa , Kazuya Ishihara , Satoshi Kumaki
IPC分类号： H03M7/30 , G06F9/345 , G06F17/14 , G06T1/20 , G06T1/60 , G06T9/00 , H04N1/41 , G06F12/00
CPC分类号： G06F17/147 , G06F9/345 , G06T9/007
摘要： In order to generate zigzag addresses for Discrete Cosine Transformation DCT data arranged in the form of a square matrix, row differentials (.DELTA.y) and column differentials (.DELTA.x) being differentials of row addresses (y) and column addresses (x) are previously stored to be successively read out (steps S12 and S13). The row differentials (.DELTA.y) and the column differentials (.DELTA.x) are added to the row addresses (y) and the column addresses (x) respectively, to newly obtain zigzag addresses (steps S14 and S15). Thus, the amount data to be stored can be reduced. Further, it is possible to further reduce the amount of data to be stored by compressing data through regularity of the row differentials (.DELTA.y) and the column differentials (.DELTA.x).
摘要翻译：为了产生以方形矩阵形式排列的离散余弦变换DCT数据的Z字形地址，行行地址（y）和列地址（x）之间的差分是行差（DELTA y）和列差（DELTA x）存储以被连续地读出（步骤S12和S13）。行行差（DELTA y）和列差（DELTA x）分别被添加到行地址（y）和列地址（x），以最新地获得之字形地址（步骤S14和S15）。因此，可以减少要存储的量数据。此外，通过行差（DELTA y）和列差（DELTA x）的规律性压缩数据，可以进一步减少要存储的数据量。

7. 发明授权

US5479369A Semiconductor integrated circuit device and semiconductor memory device 失效
标题翻译：半导体集成电路器件和半导体存储器件
公开(公告)号：US5479369A
公开(公告)日：1995-12-26
申请号：US375877
申请日：1995-01-20
申请人： Tetsuya Matsumura , Satoshi Kumaki , Shinichi Nakagawa
发明人： Tetsuya Matsumura , Satoshi Kumaki , Shinichi Nakagawa
IPC分类号： G11C11/417 , G11C7/10 , H01L27/10 , H03K3/356 , G11C7/00
CPC分类号： H03K3/356173 , G11C7/1051 , H03K3/356121
摘要： In a semiconductor integrated circuit device having a data latch function, one of two inverters constituting a data latch circuit is formed of a PMOS transistor and an NMOS transistor, with the source terminal of the NMOS transistor being connected to a terminal for applying a reset signal. The reset signal is applied to an inverter through the NMOS transistor, and the inverter inverts the reset signal and resets the data latch circuit. Since one inverter of the data latch circuit is formed of the PMOS transistor and the NMOS transistor, the setting/resetting function of the semiconductor integrated circuit device can readily be implemented.
摘要翻译：在具有数据锁存功能的半导体集成电路器件中，构成数据锁存电路的两个反相器中的一个由PMOS晶体管和NMOS晶体管构成，NMOS晶体管的源极端子连接到用于施加复位信号的端子。复位信号通过NMOS晶体管施加到逆变器，反相器反相复位信号并复位数据锁存电路。由于数据锁存电路的一个反相器由PMOS晶体管和NMOS晶体管形成，因此可以容易地实现半导体集成电路器件的设置/复位功能。

8. 发明授权

US5400295A Semiconductor integrated circuit device and semiconductor memory device 失效
公开(公告)号：US5400295A
公开(公告)日：1995-03-21
申请号：US976055
申请日：1992-11-13
申请人： Tetsuya Matsumura , Satoshi Kumaki , Shinichi Nakagawa
发明人： Tetsuya Matsumura , Satoshi Kumaki , Shinichi Nakagawa
IPC分类号： G11C11/417 , G11C7/10 , H01L27/10 , H03K3/356 , G11C11/34
CPC分类号： H03K3/356173 , G11C7/1051 , H03K3/356121
摘要： In a semiconductor integrated circuit device having a data latch function, one of two inverters constituting a data latch circuit is formed of a PMOS transistor and an NMOS transistor, with the source terminal of the NMOS transistor being connected to a terminal for applying a reset signal. The reset signal is applied to an inverter through the NMOS transistor, and the inverter inverts the reset signal and resets the data latch circuit. Since one inverter of the data latch circuit is formed of the PMOS transistor and the NMOS transistor, the setting/resetting function of the semiconductor integrated circuit device can readily be implemented.

9. 发明授权

US08324873B2 Power supply apparatus and power supply method 有权
标题翻译：电源装置及电源方式
公开(公告)号：US08324873B2
公开(公告)日：2012-12-04
申请号：US12636764
申请日：2009-12-13
申请人： Shinichi Nakagawa , Masahiro Natsume , Katsuyuki Yasukouchi
发明人： Shinichi Nakagawa , Masahiro Natsume , Katsuyuki Yasukouchi
IPC分类号： G05F1/613
CPC分类号： H02M3/1584
摘要： A power supply apparatus is provided which includes: a first switch provided between an inductor and a terminal to which a reference voltage is applied; a second switch provided between the inductor and an output terminal; a first comparator circuit that compares an input voltage with a first comparison voltage; a signal generating circuit that outputs a frequency signal according to an output from the first comparator circuit; and a first control circuit that controls the first and second switches based on an output from the signal generating circuit to control an electrical current flowing into the inductor.
摘要翻译：提供了一种电源装置，其包括：设置在电感器和施加了参考电压的端子之间的第一开关; 设置在电感器和输出端子之间的第二开关; 第一比较器电路，其将输入电压与第一比较电压进行比较; 信号发生电路，其根据来自所述第一比较器电路的输出输出频率信号; 以及第一控制电路，其基于来自信号发生电路的输出来控制第一和第二开关，以控制流入电感器的电流。

10. 发明授权

US07910431B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07910431B2
公开(公告)日：2011-03-22
申请号：US12149320
申请日：2008-04-30
申请人： Koji Takahashi , Shinichi Nakagawa
发明人： Koji Takahashi , Shinichi Nakagawa
IPC分类号： H01L21/336
CPC分类号： H01L27/0207 , G11C16/0466 , H01L27/0266 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11536 , H01L27/11546
摘要： On a surface of a Si substrate, a nonvolatile memory cell, an nMOS transistor, and a pMOS transistor are formed, and thereafter an interlayer insulation film covering the nonvolatile memory cell, the nMOS transistor, and the pMOS transistor is formed. Next, in the interlayer insulation film, there are formed plural contact plugs connected respectively to a control gate of the nonvolatile memory cell, a source or a drain of the nMOS transistor, and a source or a drain of the pMOS transistor. Thereafter, there is formed a single-layer wiring connecting the control gate to the sources or drains of the nMOS transistor and the pMOS transistor via the plural contact plugs.
摘要翻译：在Si衬底的表面上形成非易失性存储单元，nMOS晶体管和pMOS晶体管，然后形成覆盖非易失性存储单元，nMOS晶体管和pMOS晶体管的层间绝缘膜。接下来，在层间绝缘膜中，形成有分别连接到非易失性存储单元的控制栅极，nMOS晶体管的源极或漏极以及pMOS晶体管的源极或漏极的多个接触插塞。此后，形成了通过多个接触插塞将控制栅极连接到nMOS晶体管和pMOS晶体管的源极或漏极的单层布线。

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