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1. 发明授权

US6141274A Semiconductor integrated circuit having a pre-charged operation and a data latch function 有权
标题翻译：具有预充电操作和数据锁存功能的半导体集成电路
公开(公告)号：US6141274A
公开(公告)日：2000-10-31
申请号：US340145
申请日：1999-06-28
申请人： Satoshi Eto , Masato Matsumiya , Yuichi Uzawa , Kuninori Kawabata , Akira Kikutake , Toru Koga
发明人： Satoshi Eto , Masato Matsumiya , Yuichi Uzawa , Kuninori Kawabata , Akira Kikutake , Toru Koga
IPC分类号： G11C11/407 , G11C7/10 , G11C7/00
CPC分类号： G11C7/1048 , G11C7/1039 , G11C7/1051
摘要： In a semiconductor integrated circuit having the function of executing a pre-charge operation of a data bus when data is transferred to the data bus from a plurality of driver circuits connected to the data bus, a reset circuit for executing the pre-charge operation of the data bus is constituted so as to start the pre-charge operation of the data bus upon receiving an end timing of a strobe signal. Preferably, the reset circuit detects that the data bus reaches a pre-charge level for executing the pre-charge operation, and then terminates the pre-charge operation. On the other hand, in a semiconductor integrated circuit having a data latch function by a pipeline system when the data is read out from a memory cell, etc., in synchronism with a clock, a plurality of latch circuit units for temporarily storing the data are disposed in a data read path, and each of these latch circuit units is constituted in such a manner as to allow the data to pass, as such, when a control signal for controlling data latch is inputted, and to latch the data when the control signal is not inputted.
摘要翻译：在具有从数据总线连接的多个驱动电路向数据总线传送数据时执行数据总线的预充电动作的半导体集成电路中，执行预充电动作的复位电路数据总线被构成为在接收到选通信号的结束定时时开始数据总线的预充电操作。优选地，复位电路检测到数据总线达到用于执行预充电操作的预充电水平，然后终止预充电操作。另一方面，在与时钟同步地从存储单元读出数据时，在具有流水线系统的数据锁存功能的半导体集成电路中，用于临时存储数据的多个锁存电路单元被布置在数据读取路径中，并且这些锁存电路单元中的每一个被构成为允许数据通过，当用于控制数据锁存器的控制信号被输入时，并且当数据被锁定时锁存数据不输入控制信号。

2. 发明授权

US6147919A Semiconductor memory employing direct-type sense amplifiers capable of realizing high-speed access 有权
标题翻译：采用直接式读出放大器的半导体存储器，能够实现高速存取
公开(公告)号：US6147919A
公开(公告)日：2000-11-14
申请号：US274245
申请日：1999-03-23
申请人： Kuninori Kawabata , Masato Matsumiya , Satoshi Eto , Masato Takita , Toshikazu Nakamura , Masatomo Hasegawa , Hideki Kanou , Ayako Kitamoto , Toru Koga , Yuki Ishii , Akira Kikutake , Yuichi Uzawa
发明人： Kuninori Kawabata , Masato Matsumiya , Satoshi Eto , Masato Takita , Toshikazu Nakamura , Masatomo Hasegawa , Hideki Kanou , Ayako Kitamoto , Toru Koga , Yuki Ishii , Akira Kikutake , Yuichi Uzawa
IPC分类号： H01L27/10 , G11C7/06 , G11C7/12 , G11C7/02
CPC分类号： G11C7/06 , G11C7/12
摘要： A semiconductor memory has memory cells arranged in arrays, direct-type sense amplifiers arranged in each column of the memory cells, for writing and reading data to and from a memory cell to be accessed, column selection lines for selecting sense amplifiers that are in a column that involves the memory cell to be accessed, write-only column selection lines for selecting sense amplifiers that are in a row that involves the memory cell to be accessed if the memory cell is accessed to write data thereto, and local drivers. The sense amplifiers are grouped, in each row, into sense amplifier blocks. The write-only column selection lines consist of first selection lines for selecting sense amplifier blocks that are in the row that involves the memory cell to be accessed for data write and second selection lines for selecting sense amplifiers that are contained in the selected sense amplifier blocks. The local drivers apply a selection signal to the second selection lines according to a selection signal from the first selection lines. The write-only column selection lines are controlled by signals that are used to control the sense amplifiers.
摘要翻译：半导体存储器具有排列成阵列的存储单元，布置在每个存储单元列中的直接型读出放大器，用于向要被访问的存储单元写入数据和从存储单元读取数据;列选择线，用于选择读取放大器涉及要访问的存储器单元的列，只读列选择线，用于选择存储单元被访问以涉及要访问的存储器单元的行的读出放大器以写入数据，以及本地驱动器。读出放大器在每行中分组成读出放大器模块。只写列选择线由用于选择读入放大器块的第一选择线组成，所述读出放大器块包括要被存取的存储单元以进行数据写入，第二选择线用于选择包含在所选择的读出放大器块中的读出放大器。本地驱动器根据来自第一选择线的选择信号向第二选择线施加选择信号。只写列选择线由用于控制读出放大器的信号控制。

3. 发明授权

US6130849A Semiconductor memory device and data bus amplifier activation method for the semiconductor memory device 有权
标题翻译：用于半导体存储器件的半导体存储器件和数据总线放大器激活方法
公开(公告)号：US6130849A
公开(公告)日：2000-10-10
申请号：US300269
申请日：1999-04-27
申请人： Kuninori Kawabata , Masato Matsumiya , Satoshi Eto , Yuichi Uzawa , Toru Koga , Akira Kikutake
发明人： Kuninori Kawabata , Masato Matsumiya , Satoshi Eto , Yuichi Uzawa , Toru Koga , Akira Kikutake
IPC分类号： G11C11/413 , G11C7/22 , G11C11/407 , G11C11/4076 , G11C11/409 , G11C7/02
CPC分类号： G11C7/22 , G11C11/4076 , G11C2207/2281 , G11C2207/229
摘要： In a data bus amplifier activation method for a semiconductor memory device having a memory cell array, a column selection circuit for selecting a column in the memory cell array, a read data bus for transferring read data, output from the column selected by the column selection circuit, to a read data bus amplifier, and a write data bus for transferring write data, output from a write data bus amplifier, to the column selected by the column selection circuit, the read data bus amplifier or the write data bus amplifier is activated by detecting the selection of the column effected by the column selection circuit. By so doing, a read data bus amplifier enable signal or a write data bus amplifier enable signal can be generated after the occurrence of a column select signal, eliminating the need to allow a large margin for the generation timing of the read data bus amplifier enable signal or the write data bus amplifier enable signal, and as a result, the operating speed of the semiconductor memory device can be increased.
摘要翻译：在具有存储单元阵列的半导体存储器件的数据总线放大器激活方法中，用于选择存储单元阵列中的列的列选择电路，用于传送读数据的读数据总线，由列选择电路，读取数据总线放大器以及用于将从数据总线放大器输出的写数据传送到由列选择电路选择的列的写数据总线，读数据总线放大器或写数据总线放大器被激活通过检测由列选择电路实现的列的选择。通过这样做，读数据总线放大器使能信号或写数据总线放大器使能信号可以在出现列选择信号之后产生，消除了对读数据总线放大器使能的产生定时的大余量信号或写数据总线放大器使能信号，结果可以提高半导体存储器件的工作速度。

4. 发明授权

US06404692B1 Semiconductor memory 失效
公开(公告)号：US06404692B1
公开(公告)日：2002-06-11
申请号：US09539615
申请日：2000-03-31
申请人： Masato Takita , Yuichi Uzawa , Shinichi Yamada , Masato Matsumiya
发明人： Masato Takita , Yuichi Uzawa , Shinichi Yamada , Masato Matsumiya
IPC分类号： G11C700
CPC分类号： G11C7/1072 , G11C8/12 , G11C11/4085 , G11C11/4087
摘要： A semiconductor memory selects desired one of word lines, which belong to banks each including a memory cell array, on the basis of a main WD select signal (mwd) and sub-WD select signals (swdx and swdz) determined in accordance with an address. The main WD select signal is a pulse signal. A latch circuit latches, for a predetermined time, the state of the sub-WD select signals having changed on the basis of state changes of the main WD select signal. This allows the banks to share the main WD select signal. Since a main WD signal generator is thus shared by the banks, the area of a chip can be reduced.

5. 发明申请

US20050165958A1 Data relay apparatus, content addressable/associative memory device, and content addressable/associative memory device use information search method 失效
标题翻译：数据中继装置，内容寻址/关联存储装置以及内容寻址/关联存储装置使用信息搜索方法
公开(公告)号：US20050165958A1
公开(公告)日：2005-07-28
申请号：US11055330
申请日：2005-02-10
申请人： Yuichi Uzawa , Yasuhiro Ooba
发明人： Yuichi Uzawa , Yasuhiro Ooba
IPC分类号： G06F15/173 , G06F17/30
CPC分类号： H04L45/7453 , G06F17/30982
摘要： A data relay apparatus in which a search request command can be inputted efficiently to a content addressable/associative memory device. When a packet is inputted, a network processor generates a search request and passes it to the content addressable/associative memory device. Then the content addressable/associative memory device analyzes the structure of the search request and generates a plurality of search conditions. The content addressable/associative memory device makes a search according to each search condition and outputs a memory address corresponding to a detected piece of information to be searched to a memory device. The memory device passes a candidate search result corresponding to the memory address to the network processor as a search result.
摘要翻译：一种数据中继装置，其中搜索请求命令可以有效地输入到内容寻址/关联存储装置。当分组被输入时，网络处理器产生搜索请求并将其传递到内容寻址/关联存储设备。然后内容可寻址/关联存储器件分析搜索请求的结构并产生多个搜索条件。内容可寻址/关联存储器装置根据每个搜索条件进行搜索，并将与检测到的要搜索的信息相对应的存储器地址输出到存储器件。存储器件将与存储器地址相对应的候选搜索结果作为搜索结果传递给网络处理器。

6. 发明申请

US20060064413A1 Data retrieval method and device 审中-公开
标题翻译：数据检索方法和设备
公开(公告)号：US20060064413A1
公开(公告)日：2006-03-23
申请号：US11266551
申请日：2005-11-03
申请人： Yuichi Uzawa , Yasuhiro Ooba
发明人： Yuichi Uzawa , Yasuhiro Ooba
IPC分类号： G06F17/30
CPC分类号： H04L29/12009 , G06F16/90344 , H04L29/12801 , H04L29/12933 , H04L45/00 , H04L45/742 , H04L45/7453 , H04L45/7457 , H04L61/6004 , H04L61/6068 , H04L69/22
摘要： In a method and device for retrieving data matching a retrieval key from a database, entries having all of unmasked bits in all of retrieved fields matched with data bits of retrieval keys corresponding to the unmasked bits are determined to be an interim retrieval result from among entries divided into a plurality of fields and stored in a database; a longest prefix length for each of the retrieved fields is obtained from among prefix lengths of the retrieved fields of the interim retrieval result; and an entry in the interim retrieval result having the longest prefix length in one of the retrieved fields whose priority is the highest is determined to be a retrieval result.
摘要翻译：在用于从数据库中检索与检索密钥相匹配的数据的方法和装置中，将与所有未掩码位对应的检索密钥的数据位匹配的所有检索字段中的所有未掩码位的条目确定为来自条目的临时检索结果分为多个字段并存储在数据库中; 从中间检索结果的检索字段的前缀长度中获得每个检索字段的最长前缀长度; 并且将其优先级最高的检索字段之一中具有最长前缀长度的临时检索结果中的条目确定为检索结果。

7. 发明授权

US07249216B2 Data relay apparatus, content addressable/associative memory device, and content addressable/associative memory device use information search method 失效
标题翻译：数据中继装置，内容寻址/关联存储装置以及内容寻址/关联存储装置使用信息搜索方法
公开(公告)号：US07249216B2
公开(公告)日：2007-07-24
申请号：US11055330
申请日：2005-02-10
申请人： Yuichi Uzawa , Yasuhiro Ooba
发明人： Yuichi Uzawa , Yasuhiro Ooba
IPC分类号： G06F12/00
CPC分类号： H04L45/7453 , G06F17/30982
摘要： A data relay apparatus in which a search request command can be inputted efficiently to a content addressable/associative memory device. When a packet is inputted, a network processor generates a search request and passes it to the content addressable/associative memory device. Then the content addressable/associative memory device analyzes the structure of the search request and generates a plurality of search conditions. The content addressable/associative memory device makes a search according to each search condition and outputs a memory address corresponding to a detected piece of information to be searched to a memory device. The memory device passes a candidate search result corresponding to the memory address to the network processor as a search result.
摘要翻译：一种数据中继装置，其中搜索请求命令可以有效地输入到内容寻址/关联存储装置。当分组被输入时，网络处理器产生搜索请求并将其传递到内容寻址/关联存储设备。然后内容可寻址/关联存储器件分析搜索请求的结构并产生多个搜索条件。内容可寻址/关联存储器装置根据每个搜索条件进行搜索，并将与检测到的要搜索的信息相对应的存储器地址输出到存储器件。存储器件将与存储器地址相对应的候选搜索结果作为搜索结果传递给网络处理器。

8. 发明授权

US06639819B2 Associative memory apparatus and routing apparatus 失效
公开(公告)号：US06639819B2
公开(公告)日：2003-10-28
申请号：US10011373
申请日：2001-10-22
申请人： Yuichi Uzawa , Yasuhiro Ooba
发明人： Yuichi Uzawa , Yasuhiro Ooba
IPC分类号： G11C1500
CPC分类号： G11C15/00
摘要： An associative memory apparatus has such a structure as to reduce a load of an updating work and readily cope with an increase of the capacity. The associative memory apparatus outputs longest prefix match in only one searching operation, thereby shortening a processing time for the searching process. The apparatus comprises entry units, each of which includes a logical operating means outputting information about a bit length not masked in entry data when the entry data stored in its own entry unit coincides with bit data that is a key, and a search result outputting means outputting a search match information with respect to the search key only when the entry data stored in its own entry unit is entry data having the longest bit length not masked.

9. 发明授权

US6144602A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US6144602A
公开(公告)日：2000-11-07
申请号：US493624
申请日：2000-01-28
申请人： Yuichi Uzawa
发明人： Yuichi Uzawa
IPC分类号： G11C11/409 , G11C7/10 , G11C7/12 , G11C11/4094 , G11C11/4096 , G11C7/00
CPC分类号： G11C11/4096 , G11C11/4094 , G11C7/1048 , G11C7/12
摘要： As the pre-charge potential for write global data buses (12, 13), a potential lower than the power supply voltage (Vii) for peripheral circuit by the threshold voltage (Vth) of a transistor is used. This suppresses disturbance in the potential of a pair of bit lines (18, 19) due to pre-charge operation. It suffices if the write global data buses are pre-charged to the potential lower than the power supply voltage (Vii) for peripheral circuit by the threshold voltage (Vth). This can reduce current consumption accordingly. By generating the pre-charge potential without using the power supply voltage (Viic) for core, adverse effects on sense operation can be avoided.
摘要翻译：作为写入全局数据总线（12,13）的预充电电位，使用低于晶体管的阈值电压（Vth）的外围电路的电源电压（Vii）的电位。这抑制了由于预充电操作导致的一对位线（18,19）的电位的干扰。如果写全局数据总线被预充电到低于外围电路的电源电压（Vii）的阈值阈值电压（Vth）就足够了。这可以相应地减少电流消耗。通过在不使用核心的电源电压（Viic）的情况下产生预充电电位，可以避免对感测操作的不利影响。

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