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1. 发明授权

US07495988B2 Integrated circuit device and electronic instrument 有权
标题翻译：集成电路器件和电子仪器
公开(公告)号：US07495988B2
公开(公告)日：2009-02-24
申请号：US11270694
申请日：2005-11-10
申请人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Hisanobu Ishiyama , Kazuhiro Maekawa
发明人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Hisanobu Ishiyama , Kazuhiro Maekawa
IPC分类号： G11C5/14
CPC分类号： G09G3/2007 , G09G2310/027 , G09G2360/18
摘要： An integrated circuit device having a display memory, wherein a plurality of first power supply interconnects VSSL for supplying a first power supply voltage VSS to memory cells MC are formed in a metal interconnect layer in which a plurality of wordlines WL are formed; and wherein a plurality of second power supply interconnects VDDL for supplying a second power supply voltage VDD to the memory cells are formed in another metal interconnect layer in which a plurality of bitlines BL are formed, the second power supply voltage VDD being higher than the first power supply voltage VSS. A plurality of bitline protection interconnects SHD are formed in a layer above the bitlines BL, and each of the bitline protection interconnects SHD at least partially covers one of the bitlines BL in a plan view. A third power supply interconnect GL for supplying a third power supply voltage to circuits other than the display memory are formed in a layer above the bitline protection interconnects SHD, the third power supply voltage being higher than the second power supply voltage VDD.
摘要翻译：一种具有显示存储器的集成电路器件，其中在形成有多个字线WL的金属互连层中形成有用于向存储单元MC提供第一电源电压VSS的多个第一电源互连VSSL; 并且其中，在形成有多个位线BL的另一个金属互连层中形成有用于将第二电源电压VDD提供给存储单元的多个第二电源互连VDDL，第二电源电压VDD高于第一电源电压VDD 电源电压VSS。多个位线保护互连SHD形成在位线BL上方的层中，并且每个位线保护互连SHD在平面图中至少部分地覆盖位线BL之一。用于将第三电源电压提供给除了显示存储器之外的电路的第三电源互连GL形成在位线保护互连SHD上方的层中，第三电源电压高于第二电源电压VDD。

2. 发明申请

US20070013685A1 Integrated circuit device and electronic instrument 有权
标题翻译：集成电路器件和电子仪器
公开(公告)号：US20070013685A1
公开(公告)日：2007-01-18
申请号：US11270694
申请日：2005-11-10
申请人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Hisanobu Ishiyama , Kazuhiro Maekawa
发明人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Hisanobu Ishiyama , Kazuhiro Maekawa
IPC分类号： G09G5/00
CPC分类号： G09G3/2007 , G09G2310/027 , G09G2360/18
摘要： An integrated circuit device having a display memory, wherein a plurality of first power supply interconnects VSSL for supplying a first power supply voltage VSS to memory cells MC are formed in a metal interconnect layer in which a plurality of wordlines WL are formed; and wherein a plurality of second power supply interconnects VDDL for supplying a second power supply voltage VDD to the memory cells are formed in another metal interconnect layer in which a plurality of bitlines BL are formed, the second power supply voltage VDD being higher than the first power supply voltage VSS. A plurality of bitline protection interconnects SHD are formed in a layer above the bitlines BL, and each of the bitline protection interconnects SHD at least partially covers one of the bitlines BL in a plan view. A third power supply interconnect GL for supplying a third power supply voltage to circuits other than the display memory are formed in a layer above the bitline protection interconnects SHD, the third power supply voltage being higher than the second power supply voltage VDD.
摘要翻译：一种具有显示存储器的集成电路器件，其中在形成有多个字线WL的金属互连层中形成有用于向存储单元MC提供第一电源电压VSS的多个第一电源互连VSSL; 并且其中，在形成有多个位线BL的另一个金属互连层中形成有用于将第二电源电压VDD提供给存储单元的多个第二电源互连VDDL，第二电源电压VDD高于第一电源电压VDD 电源电压VSS。多个位线保护互连SHD形成在位线BL上方的层中，并且每个位线保护互连SHD在平面图中至少部分地覆盖位线BL之一。用于将第三电源电压提供给除了显示存储器之外的电路的第三电源互连GL形成在位线保护互连SHD上方的层中，第三电源电压高于第二电源电压VDD。

3. 发明申请

US20070013074A1 Integrated circuit device and electronic instrument 有权
标题翻译：集成电路器件和电子仪器
公开(公告)号：US20070013074A1
公开(公告)日：2007-01-18
申请号：US11270586
申请日：2005-11-10
申请人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Hisanobu Ishiyama , Kazuhiro Maekawa
发明人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Hisanobu Ishiyama , Kazuhiro Maekawa
IPC分类号： H01L23/52
CPC分类号： H01L23/552 , G11C5/063 , H01L24/49 , H01L2224/49175 , H01L2924/00014 , H01L2924/01019 , H01L2924/01037 , H01L2924/01066 , H01L2924/14 , H01L2924/19041 , H01L2924/3025 , H01L2224/45099
摘要： An integrated circuit device having a display memory, wherein a plurality of first power supply interconnects for supplying a first power supply voltage to a plurality of memory cells are provided in a metal interconnect layer in which a plurality of bitlines are formed; wherein a second power supply interconnect for supplying a second power supply voltage to the memory cells is provided in a metal interconnect layer in which a plurality of wordlines are formed, the second power supply voltage being higher than the first power supply voltage; wherein a plurality of bitline protection interconnects are formed in a layer above the bitlines, each of the bitline protection interconnects at least partially covering one of the bitlines in a plan view; and wherein a third power supply interconnect for supplying a third power supply voltage to circuits of the integrated circuit device other than the display memory is provided in a layer above the bitline protection interconnects, the third power supply voltage being higher than the second power supply voltage.
摘要翻译：一种具有显示存储器的集成电路器件，其中在形成多个位线的金属互连层中提供用于向多个存储单元提供第一电源电压的多个第一电源互连件; 其中在形成有多个字线的金属互连层中提供用于向所述存储单元提供第二电源电压的第二电源互连，所述第二电源电压高于所述第一电源电压; 其中多个位线保护互连形成在所述位线上方的层中，所述位线保护互连中的每一个在平面图中至少部分地覆盖所述位线之一; 并且其中，用于将第三电源电压提供给除了所述显示存储器之外的所述集成电路装置的电路的第三电源互连设置在所述位线保护互连线上方的层中，所述第三电源电压高于所述第二电源电压。

4. 发明授权

US07492659B2 Integrated circuit device and electronic instrument 有权
标题翻译：集成电路器件和电子仪器
公开(公告)号：US07492659B2
公开(公告)日：2009-02-17
申请号：US11270586
申请日：2005-11-10
申请人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Hisanobu Ishiyama , Kazuhiro Maekawa
发明人： Satoru Kodaira , Noboru Itomi , Shuji Kawaguchi , Takashi Kumagai , Hisanobu Ishiyama , Kazuhiro Maekawa
IPC分类号： G11C5/14
CPC分类号： H01L23/552 , G11C5/063 , H01L24/49 , H01L2224/49175 , H01L2924/00014 , H01L2924/01019 , H01L2924/01037 , H01L2924/01066 , H01L2924/14 , H01L2924/19041 , H01L2924/3025 , H01L2224/45099
摘要： An integrated circuit device having a display memory, wherein a plurality of first power supply interconnects for supplying a first power supply voltage to a plurality of memory cells are provided in a metal interconnect layer in which a plurality of bitlines are formed; wherein a second power supply interconnect for supplying a second power supply voltage to the memory cells is provided in a metal interconnect layer in which a plurality of wordlines are formed, the second power supply voltage being higher than the first power supply voltage; wherein a plurality of bitline protection interconnects are formed in a layer above the bitlines, each of the bitline protection interconnects at least partially covering one of the bitlines in a plan view; and wherein a third power supply interconnect for supplying a third power supply voltage to circuits of the integrated circuit device other than the display memory is provided in a layer above the bitline protection interconnects, the third power supply voltage being higher than the second power supply voltage.
摘要翻译：一种具有显示存储器的集成电路器件，其中在形成多个位线的金属互连层中提供用于向多个存储单元提供第一电源电压的多个第一电源互连件; 其中在形成有多个字线的金属互连层中提供用于向所述存储单元提供第二电源电压的第二电源互连，所述第二电源电压高于所述第一电源电压; 其中多个位线保护互连形成在所述位线上方的层中，所述位线保护互连中的每一个在平面图中至少部分地覆盖所述位线之一; 并且其中，用于将第三电源电压提供给除了所述显示存储器之外的所述集成电路装置的电路的第三电源互连设置在所述位线保护互连线上方的层中，所述第三电源电压高于所述第二电源电压。

5. 发明授权

US08547722B2 Integrated circuit device and electronic instrument 有权
标题翻译：集成电路器件和电子仪器
公开(公告)号：US08547722B2
公开(公告)日：2013-10-01
申请号：US13137995
申请日：2011-09-23
申请人： Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa , Noboru Itomi , Satoru Kodaira , Junichi Karasawa , Takashi Kumagai , Hisanobu Ishiyama , Takashi Fujise
发明人： Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa , Noboru Itomi , Satoru Kodaira , Junichi Karasawa , Takashi Kumagai , Hisanobu Ishiyama , Takashi Fujise
IPC分类号： G11C5/06
CPC分类号： G09G3/3688 , G09G3/2011 , G09G2330/02 , G09G2330/04 , H01L2224/05553
摘要： An integrated circuit device includes first to Nth circuit blocks CB1 to CBN, a first interface region disposed along a fourth side and on the D2 side of the first to Nth circuit blocks CB1 to CBN, and a second interface region disposed along a second side and on the D4 side of the first to Nth circuit blocks CB1 to CBN. A local line LLG formed using a wiring layer lower than an Ith layer is provided between the adjacent circuit blocks as at least one of a signal line and a power supply line. Global lines GLG and GLD formed using the Ith or higher wiring layer are provided along the direction D1 over the circuit block disposed between the nonadjacent circuit blocks as at least one of a signal line and a power supply line.
摘要翻译：集成电路装置包括第一至第N电路块CB1至CBN，沿第一至第N电路块CB1至CBN的第四侧和第二侧设置的第一接口区域以及沿着第二侧设置的第二接口区域，在第一至第N电路块CB1至CBN的D4侧。使用低于第I层的布线层形成的局部线LLG设置在相邻的电路块之间，作为信号线和电源线中的至少一个。使用第I或更高布线层形成的全局线GLG和GLD沿着方向D1设置在布置在不相邻电路块之间的电路块上，作为信号线和电源线中的至少一个。

6. 发明申请

US20070013635A1 Integrated circuit device and electronic instrument 审中-公开
标题翻译：集成电路器件和电子仪器
公开(公告)号：US20070013635A1
公开(公告)日：2007-01-18
申请号：US11477742
申请日：2006-06-30
申请人： Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa , Noboru Itomi , Satoru Kodaira , Junichi Karasawa , Takashi Kumagai , Hisanobu Ishiyama , Takashi Fujise
发明人： Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa , Noboru Itomi , Satoru Kodaira , Junichi Karasawa , Takashi Kumagai , Hisanobu Ishiyama , Takashi Fujise
IPC分类号： G09G3/36
CPC分类号： G09G3/3674 , G09G3/3685
摘要： An integrated circuit device includes a data driver block DB, a memory block MB, and a logic circuit block LB. The data driver block DB includes a data driver DR and a buffer circuit BF which buffers a driver control signal from the logic circuit block LB and outputs the buffered driver control signal to the data driver DR. The memory block MB includes a memory cell array MA and a row address decoder RD which selects a wordline. The data driver block DB and the memory block MB are disposed along a direction D1, the buffer circuit BF and the data driver DR are disposed along a direction D2, the row address decoder RD and the memory cell array MA are disposed along the direction D2, and the buffer circuit BF and the row address decoder RD are disposed along the direction D1.
摘要翻译：集成电路装置包括数据驱动块DB，存储块MB和逻辑电路块LB。数据驱动器块DB包括数据驱动器DR和缓冲电路BF，其缓冲来自逻辑电路块LB的驱动器控制信号，并将缓冲的驱动器控制信号输出到数据驱动器DR。存储块MB包括选择字线的存储单元阵列MA和行地址解码器RD。数据驱动块DB和存储块MB沿着方向D1设置，缓冲电路BF和数据驱动器DR沿着方向D 2设置，行地址解码器RD和存储单元阵列MA沿着方向D 2，并且缓冲电路BF和行地址解码器RD沿着方向D1设置。

7. 发明申请

US20070001982A1 Integrated circuit device and electronic instrument 有权
标题翻译：集成电路器件和电子仪器
公开(公告)号：US20070001982A1
公开(公告)日：2007-01-04
申请号：US11477670
申请日：2006-06-30
申请人： Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa , Noboru Itomi , Satoru Kodaira , Junichi Karasawa , Takashi Kumagai , Hisanobu Ishiyama , Takashi Fujise
发明人： Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa , Noboru Itomi , Satoru Kodaira , Junichi Karasawa , Takashi Kumagai , Hisanobu Ishiyama , Takashi Fujise
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G3/2011 , G09G2330/02 , G09G2330/04 , H01L2224/05553
摘要： An integrated circuit device includes first to Nth circuit blocks CB1 to CBN, a first interface region disposed along a fourth side and on the D2 side of the first to Nth circuit blocks CB1 to CBN, and a second interface region disposed along a second side and on the D4 side of the first to Nth circuit blocks CB1 to CBN. A local line LLG formed using a wiring layer lower than an Ith layer is provided between the adjacent circuit blocks as at least one of a signal line and a power supply line. Global lines GLG and GLD formed using the Ith or higher wiring layer are provided along the direction D1 over the circuit block disposed between the nonadjacent circuit blocks as at least one of a signal line and a power supply line.
摘要翻译：集成电路装置包括第一至第N电路块CB 1至CBN，沿着第一至第N电路块CB 1至CBN的第四侧和第二侧设置的第一接口区域，以及沿着第二至第N电路块并且在第一至第N电路块CB 1至CBN的D4侧。使用低于第I层的布线层形成的局部线LLG设置在相邻的电路块之间，作为信号线和电源线中的至少一个。使用第I或更高布线层形成的全局线GLG和GLD沿着方向D1设置在布置在不相邻电路块之间的电路块上，作为信号线和电源线中的至少一个。

8. 发明申请

US20070001886A1 Integrated circuit device and electronic instrument 审中-公开
标题翻译：集成电路器件和电子仪器
公开(公告)号：US20070001886A1
公开(公告)日：2007-01-04
申请号：US11477646
申请日：2006-06-30
申请人： Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa , Noboru Itomi , Satoru Kodaira , Junichi Karasawa , Takashi Kumagai , Hisanobu Ishiyama , Takashi Fujise
发明人： Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa , Noboru Itomi , Satoru Kodaira , Junichi Karasawa , Takashi Kumagai , Hisanobu Ishiyama , Takashi Fujise
IPC分类号： H03M1/66
CPC分类号： G09G3/3611 , G09G3/3648 , G09G3/3696 , G09G2360/18
摘要： An integrated circuit device includes a driver macrocell in which a plurality of circuit blocks are integrated into a macrocell. The driver macrocell includes a data driver block DB for driving data lines, a memory block MB which stores image data, and a pad block PDB in which pads for electrically connecting output lines of the data driver block DB with the data lines are disposed. The data driver block DB and the memory block MB are disposed along a direction D1, and the pad block PDB is disposed on the D2 side of the data driver block DB and the memory block MB.
摘要翻译：集成电路装置包括驱动器宏单元，其中多个电路块集成到宏单元中。驱动器宏单元包括用于驱动数据线的数据驱动器块DB，存储图像数据的存储器块MB和用于电连接数据驱动器块DB的输出线与数据线的焊盘的焊盘块PDB。数据驱动块DB和存储块MB沿着方向D1设置，并且焊盘块PDB设置在数据驱动块DB和存储块MB的D 2侧。

9. 发明申请

US20120019566A1 Integrated circuit device and electronic instrument 有权
标题翻译：集成电路器件和电子仪器
公开(公告)号：US20120019566A1
公开(公告)日：2012-01-26
申请号：US13137995
申请日：2011-09-23
申请人： Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa , Noboru Itomi , Satoru Kodaira , Junichi Karasawa , Takashi Kumagai , Hisanobu Ishiyama , Takashi Fujise
发明人： Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa , Noboru Itomi , Satoru Kodaira , Junichi Karasawa , Takashi Kumagai , Hisanobu Ishiyama , Takashi Fujise
IPC分类号： G09G5/10
CPC分类号： G09G3/3688 , G09G3/2011 , G09G2330/02 , G09G2330/04 , H01L2224/05553
摘要： An integrated circuit device includes first to Nth circuit blocks CB1 to CBN, a first interface region disposed along a fourth side and on the D2 side of the first to Nth circuit blocks CB1 to CBN, and a second interface region disposed along a second side and on the D4 side of the first to Nth circuit blocks CB1 to CBN. A local line LLG formed using a wiring layer lower than an Ith layer is provided between the adjacent circuit blocks as at least one of a signal line and a power supply line. Global lines GLG and GLD formed using the Ith or higher wiring layer are provided along the direction D1 over the circuit block disposed between the nonadjacent circuit blocks as at least one of a signal line and a power supply line.
摘要翻译：集成电路装置包括第一至第N电路块CB1至CBN，沿第一至第N电路块CB1至CBN的第四侧和第二侧设置的第一接口区域以及沿着第二侧设置的第二接口区域，在第一至第N电路块CB1至CBN的D4侧。使用低于第I层的布线层形成的局部线LLG设置在相邻的电路块之间，作为信号线和电源线中的至少一个。使用第I或更高布线层形成的全局线GLG和GLD沿着方向D1设置在布置在不相邻电路块之间的电路块上，作为信号线和电源线中的至少一个。

10. 发明授权

US08054710B2 Integrated circuit device and electronic instrument 有权
标题翻译：集成电路器件和电子仪器
公开(公告)号：US08054710B2
公开(公告)日：2011-11-08
申请号：US11477670
申请日：2006-06-30
申请人： Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa , Noboru Itomi , Satoru Kodaira , Junichi Karasawa , Takashi Kumagai , Hisanobu Ishiyama , Takashi Fujise
发明人： Satoru Ito , Masahiko Moriguchi , Kazuhiro Maekawa , Noboru Itomi , Satoru Kodaira , Junichi Karasawa , Takashi Kumagai , Hisanobu Ishiyama , Takashi Fujise
IPC分类号： G11C8/00
CPC分类号： G09G3/3688 , G09G3/2011 , G09G2330/02 , G09G2330/04 , H01L2224/05553
摘要： An integrated circuit device includes first to Nth circuit blocks CB1 to CBN, a first interface region disposed along a fourth side and on the D2 side of the first to Nth circuit blocks CB1 to CBN, and a second interface region disposed along a second side and on the D4 side of the first to Nth circuit blocks CB1 to CBN. A local line LLG formed using a wiring layer lower than an Ith layer is provided between the adjacent circuit blocks as at least one of a signal line and a power supply line. Global lines GLG and GLD formed using the Ith or higher wiring layer are provided along the direction D1 over the circuit block disposed between the nonadjacent circuit blocks as at least one of a signal line and a power supply line.
摘要翻译：集成电路装置包括第一至第N电路块CB1至CBN，沿第一至第N电路块CB1至CBN的第四侧和第二侧设置的第一接口区域以及沿着第二侧设置的第二接口区域，在第一至第N电路块CB1至CBN的D4侧。使用低于第I层的布线层形成的局部线LLG设置在相邻的电路块之间，作为信号线和电源线中的至少一个。使用第I或更高布线层形成的全局线GLG和GLD沿着方向D1设置在布置在不相邻电路块之间的电路块上，作为信号线和电源线中的至少一个。

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