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1. 发明授权

US06927442B2 Charge pump device 失效
标题翻译：电荷泵装置
公开(公告)号：US06927442B2
公开(公告)日：2005-08-09
申请号：US10329722
申请日：2002-12-26
申请人： Satoru Kaneko , Toshiyuki Ohkoda , Takao Myono
发明人： Satoru Kaneko , Toshiyuki Ohkoda , Takao Myono
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8222 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L27/08 , H01L27/092 , H02M3/07 , H01L29/72
CPC分类号： H01L27/0921 , H01L27/0623 , H02M3/07 , H02M3/073
摘要： A semiconductor device for a charge pump device suitable for providing large current capacity and preventing a latch up from occurring is offered. A first and a second N-type epitaxial silicon layers are stacked on a P-type single crystalline silicon substrate, and P-type well regions are formed in the second epitaxial silicon layer. P+-type buried layers abutting on bottoms of the P-type well regions and N+-type buried layers abutting on bottoms of the P+-type buried layers and electrically isolating the P-type well regions from the single crystalline silicon substrate are formed. An MOS transistor is formed in each of the P-type well regions and a drain layer of the MOS transistor and each of the P-type well regions are electrically connected.
摘要翻译：提供了适用于提供大电流容量并防止发生闩锁的用于电荷泵装置的半导体器件。在P型单晶硅衬底上堆叠第一和第二N型外延硅层，在第二外延硅层中形成P型阱区。邻接在P型阱区域的底部上的P +型掩埋层和与P +型掩埋层的底部邻接并与P型阱区域与单晶硅衬底电隔离的N +型掩埋层。在每个P型阱区和MOS晶体管的漏极层中形成MOS晶体管，并且每个P型阱区电连接。

2. 发明授权

US06881997B2 Charge pump device 有权
标题翻译：电荷泵装置
公开(公告)号：US06881997B2
公开(公告)日：2005-04-19
申请号：US10329718
申请日：2002-12-26
申请人： Satoru Kaneko , Toshiyuki Ohkoda , Takao Myono
发明人： Satoru Kaneko , Toshiyuki Ohkoda , Takao Myono
IPC分类号： H01L27/02 , H01L27/06 , H01L27/092 , H02M3/07 , H01L27/108
CPC分类号： H02M3/073 , H01L27/0222 , H01L27/0623 , H01L27/0928 , H02M2003/075 , H02M2003/078
摘要： In a charge pump device, occurrence of a latch up can be prevented and current capacity can be increased. An N-type epitaxial silicon layer is formed on a P-type single crystalline silicon substrate, P-type well regions are formed in the N-type epitaxial silicon layer separated from each other, and P-type lower isolation layers and P-type upper isolation layers are formed between the P-type well regions. Then a charge transfer MOS transistor is formed in each of the P-type well regions. The P-type single crystalline silicon substrate is biased to a ground potential or a negative potential.
摘要翻译：在电荷泵装置中，可以防止闩锁的发生，并且可以增加电流容量。在P型单晶硅衬底上形成N型外延硅层，在分离的N型外延硅层中形成P型阱区，P型下隔离层和P型在P型阱区之间形成上隔离层。然后在每个P型阱区中形成电荷转移MOS晶体管。 P型单晶硅衬底被偏压到接地电位或负电位。

3. 发明授权

US06864543B2 High breakdown voltage CMOS device 有权
标题翻译：高击穿电压CMOS器件
公开(公告)号：US06864543B2
公开(公告)日：2005-03-08
申请号：US10329643
申请日：2002-12-26
申请人： Satoru Kaneko , Toshiyuki Ohkoda , Takao Myono
发明人： Satoru Kaneko , Toshiyuki Ohkoda , Takao Myono
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8249 , H01L27/02 , H01L27/06 , H01L27/08 , H01L27/092 , H02M3/07 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H02M3/073 , H01L27/0222 , H01L27/0623 , H01L27/0921
摘要： A semiconductor device for a charge pump device suitable for providing large current capacity and preventing a latch up from occurring is offered. A first and a second N-type epitaxial silicon layers are stacked on a P-type single crystalline silicon substrate, and a P-type well region is formed in the second epitaxial silicon layer. A P+-type buried layer is formed abutting on a bottom of the P-type well region, and an MOS transistor is formed in the P-type well region. The MOS transistor has a first source layer N+S of high impurity concentration, a first drain layer N+D of high impurity concentration and a second source layer N−S and/or a second drain layer N−D of low impurity concentration, which is diffused deeper than the first source layer N+S of high impurity concentration and the first drain layer N+D of high impurity concentration.
摘要翻译：提供了适用于提供大电流容量并防止发生闩锁的用于电荷泵装置的半导体器件。第一和第二N型外延硅层堆叠在P型单晶硅衬底上，并且在第二外延硅层中形成P型阱区。在P型阱区的底部形成P +型掩埋层，在P型阱区中形成MOS晶体管。 MOS晶体管具有高杂质浓度的第一源极层N + S，高杂质浓度的第一漏极层N + D和低杂质浓度的第二源极层NS和/或第二漏极层ND，其被扩散更深高杂质浓度的第一源极层N + S和杂质浓度高的第一漏极层N + D。

4. 发明授权

US06822298B2 Large current capacity semiconductor device 有权
标题翻译：大电流容量半导体器件
公开(公告)号：US06822298B2
公开(公告)日：2004-11-23
申请号：US10329851
申请日：2002-12-26
申请人： Satoru Kaneko , Toshiyuki Ohkoda , Takao Myono
发明人： Satoru Kaneko , Toshiyuki Ohkoda , Takao Myono
IPC分类号： H01L2976
CPC分类号： H01L21/823892 , H01L21/8249 , H01L27/0222 , H01L27/0623 , H01L27/0921
摘要： A semiconductor device for a charge pump device suitable for providing large current capacity and preventing a latch up from occurring is offered. An N-type epitaxial silicon layer is formed on a P-type single crystalline silicon substrate, and a P-type well region is formed in the N-type epitaxial silicon layer. A P+-type buried layer abutting on a bottom of the P-type well region and an N+-type buried layer partially overlapping with the P+-type buried layer and electrically isolating the P-type well region from the single crystalline silicon substrate are formed. And then, an MOS transistor is formed in the P-type well region.
摘要翻译：提供了适用于提供大电流容量并防止发生闩锁的用于电荷泵装置的半导体器件。在P型单晶硅衬底上形成N型外延硅层，在N型外延硅层中形成P型阱区。形成邻接在P型阱区的底部的P +型掩埋层和与P +型掩埋层部分重叠并将P型阱区与单晶硅衬底电隔离的N +型掩埋层。然后，在P型阱区域中形成MOS晶体管。

5. 发明申请

US20050056898A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20050056898A1
公开(公告)日：2005-03-17
申请号：US10969625
申请日：2004-10-20
申请人： Satoru Kaneko , Toshiyuki Ohkoda , Takao Myono
发明人： Satoru Kaneko , Toshiyuki Ohkoda , Takao Myono
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8238 , H01L21/8249 , H01L27/02 , H01L27/06 , H01L27/092 , H03K19/0185 , H01L29/76
CPC分类号： H01L21/823892 , H01L21/8249 , H01L27/0222 , H01L27/0623 , H01L27/0921
摘要： A semiconductor device for a charge pump device suitable for providing large current capacity and preventing a latch up from occurring is offered. An N-type epitaxial silicon layer is formed on a P-type single crystalline silicon substrate, and a P-type well region is formed in the N-type epitaxial silicon layer. A P+-type buried layer abutting on a bottom of the P-type well region and an N+-type buried layer partially overlapping with the P+-type buried layer and electrically isolating the P-type well region from the single crystalline silicon substrate are formed. And then, an MOS transistor is formed in the P-type well region.
摘要翻译：提供了适用于提供大电流容量并防止发生闩锁的用于电荷泵装置的半导体器件。在P型单晶硅衬底上形成N型外延硅层，在N型外延硅层中形成P型阱区。形成邻接在P型阱区的底部的P +型掩埋层和与P +型掩埋层部分重叠并将P型阱区与单晶硅衬底电隔离的N +型掩埋层。然后，在P型阱区域中形成MOS晶体管。

6. 发明授权

US06864525B2 Charge pump device 有权
标题翻译：电荷泵装置
公开(公告)号：US06864525B2
公开(公告)日：2005-03-08
申请号：US10329842
申请日：2002-12-26
申请人： Satoru Kaneko , Toshiyuki Ohkoda , Takao Myono
发明人： Satoru Kaneko , Toshiyuki Ohkoda , Takao Myono
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8249 , H01L27/02 , H01L27/06 , H02M3/07 , H01L29/72
CPC分类号： H01L27/0218 , H01L27/0623 , H02M3/073
摘要： A latch up in a charge pump device is prevented as well as a withstand voltage of an MOS transistor used in the charge pump device is increased with this invention. A first and a second N-type epitaxial silicon layers are stacked on a P-type single crystalline silicon substrate, and P-type well regions are formed in the second epitaxial silicon layer separated from each other. A P-type isolation layer is formed between the P-type well regions. A P+-type buried layer is formed abutting on a bottom of each of the well regions, an N+-type buried layer is formed abutting on a bottom of the P+-type buried layer, and a transistor for charge transfer is formed in each of the P-type well regions.
摘要翻译：防止电荷泵装置中的闩锁，并且通过本发明，电荷泵装置中使用的MOS晶体管的耐受电压也增加。在P型单晶硅衬底上堆叠第一和第二N型外延硅层，并且在彼此分离的第二外延硅层中形成P型阱区。在P型阱区之间形成P型隔离层。形成邻接在每个阱区的底部的P +型掩埋层，在P +型掩埋层的底部邻接形成N +型掩埋层，并且在每个中形成电荷转移用晶体管 P型井区。

7. 发明授权

US06515535B2 Charge pump circuit 有权
标题翻译：电荷泵电路
公开(公告)号：US06515535B2
公开(公告)日：2003-02-04
申请号：US09769034
申请日：2001-01-25
申请人： Takao Myono
发明人： Takao Myono
IPC分类号： G05F110
CPC分类号： H02M3/073 , H02M2003/075
摘要： Charge transfer MOS transistors M1 and M2 at front two stages are constructed of an N-channel type, and charge transfer MOS transistors at rear two stages are constructed of an P-channel type. Inverting level shift circuits S1 and S2 and non-inverting level shift circuits S3 and S4, which can produces an intermediate potential are provided. Because of such a configuration, a charge pump circuit which can realize high efficiency and provide a large output current can be realized. In addition, the gate/source voltage Vgs (transistors are in the ON state) of the charge transfer MOS transistors can be uniformed to 2 Vdd.
摘要翻译：前两级的电荷转移MOS晶体管M1和M2由N沟道型构成，后两级的电荷转移MOS晶体管由P沟道型构成。提供可产生中间电位的反相电平移位电路S1和S2以及非反相电平移位电路S3和S4。由于这样的结构，可以实现能够实现高效率并且提供大的输出电流的电荷泵电路。此外，电荷转移MOS晶体管的栅/源电压Vgs（晶体管处于导通状态）可以均匀化为2Vdd。

8. 发明授权

US06400210B2 Charge-pump circuit for boosting voltage stepwise 失效
标题翻译：电荷泵电路，逐步升压
公开(公告)号：US06400210B2
公开(公告)日：2002-06-04
申请号：US09732944
申请日：2000-12-08
申请人： Takao Myono
发明人： Takao Myono
IPC分类号： G05F302
CPC分类号： H02M3/07 , H02M3/073
摘要： A charge-pump circuit comprising diodes D1 and D2, which are connected in series; capacitors C1A and C1B, which are connected to the juncture of the diodes D1 and D2; a clock driver 11, for supplying a clock to the capacitor C1B; and switches S1, S2 and S3, which are used to connect the capacitors C1A and C1B to the juncture of the diodes D1 and D2 in series or in parallel, consonant with the voltage level of the clock, wherein a boosted voltage is output by the diode D2.
摘要翻译：包括串联连接的二极管D1和D2的电荷泵电路; 连接到二极管D1和D2的接合点的电容器C1A和C1B; 时钟驱动器11，用于向电容器C1B提供时钟; 以及开关S1，S2和S3，其用于将电容器C1A和C1B串联或并联连接到二极管D1和D2的接合部，这与开关的时钟的电压电平相符合，其中升压电压由二极管D2。

9. 发明申请

US20060164135A1 Driver circuit 审中-公开
标题翻译：驱动电路
公开(公告)号：US20060164135A1
公开(公告)日：2006-07-27
申请号：US11337809
申请日：2006-01-24
申请人： Takao Myono , Yoshitaka Onaya
发明人： Takao Myono , Yoshitaka Onaya
IPC分类号： H03B1/00
CPC分类号： H02M1/08 , H01L27/0222 , H03K17/163
摘要： An abnormal reduction in a positive high power supply electric potential VH outputted by a positive booster charge pump circuit at switching of an output stage inverter in a driver circuit is prevented. An output of an inverter INV2 is applied to an input terminal of an inverter INV4 for controlling an output transistor, and an output of the inverter INV4 is applied to a gate of an N-channel type MOS transistor of the output stage inverter INV6. The inverter INV4 is made of a P-channel type MOS transistor, a first resistor and an N-channel type MOS transistor connected between a positive high power supply electric potential VH and a negative high power supply electric potential VL, making a connecting node between the first resistor and the N-channel type MOS transistor an output terminal of the inverter INV4.
摘要翻译：防止在驱动器电路中的输出级反相器的切换时由正升压器电荷泵电路输出的正高电源电位VH的异常减小。反相器INV2的输出被施加到用于控制输出晶体管的反相器INV 4的输入端，并且反相器INV4的输出被施加到输出级反相器的N沟道型MOS晶体管的栅极 INV反相器INV4由连接在正高电源电位VH和负高电源电位VL之间的P沟道型MOS晶体管，第一电阻器和N沟道型MOS晶体管构成，使得在第一电阻器和N沟道型MOS晶体管之间的连接节点是反相器INV4的输出端子。

10. 发明授权

US06946899B2 Charge pump circuit 有权
标题翻译：电荷泵电路
公开(公告)号：US06946899B2
公开(公告)日：2005-09-20
申请号：US10263405
申请日：2002-10-02
申请人： Takao Myono
发明人： Takao Myono
IPC分类号： G05F1/10 , H02M3/07 , G05F3/02
CPC分类号： H02M3/073 , H02M2003/075
摘要： Charge transfer MOS transistors M1 and M2 at front two stages are constructed of an N-channel type, and charge transfer MOS transistors at rear two stages are constructed of an P-channel type. Inverting level shift circuits S1 and S2 and non-inverting level shift circuits S3 and S4, which can produces an intermediate potential are provided. Because of such a configuration, a charge pump circuit which can realize high efficiency and provide a large output current can be realized. In addition, the gate/source voltage Vgs (transistors are in the ON state) of the charge transfer MOS transistors can be uniformed to 2Vdd.
摘要翻译：前两级的电荷转移MOS晶体管M 1和M 2由N沟道型构成，后两级的电荷转移MOS晶体管由P沟道型构成。提供可产生中间电位的反相电平移位电路S 1和S 2以及非反相电平移位电路S 3和S 4。由于这样的结构，可以实现能够实现高效率并且提供大的输出电流的电荷泵电路。此外，电荷转移MOS晶体管的栅极/源极电压Vgs（晶体管处于导通状态）可以均匀化为2Vdd。

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