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1. 发明授权

US5469081A Circuit for interconnecting integrated semiconductor circuits 失效
标题翻译：用于互连集成半导体电路的电路
公开(公告)号：US5469081A
公开(公告)日：1995-11-21
申请号：US292142
申请日：1994-08-08
申请人： Satomi Horita , Yasushi Aoki , Masahiro Wakana , Hiroshi Okamoto , Kiyohiko Chiba , Shizue Daikoku
发明人： Satomi Horita , Yasushi Aoki , Masahiro Wakana , Hiroshi Okamoto , Kiyohiko Chiba , Shizue Daikoku
IPC分类号： H03K19/017 , H03K19/0175 , H03K19/0185
CPC分类号： H03K19/018507
摘要： An interconnection circuit having a circuit portion which is provided in one of two integrated semiconductors to be connected, for limiting the amplitude in voltage of the signal output from said one circuit, and another circuit portion which is provided in the other one of the two circuits, for discriminating the logic level of the signal input thereinto based on a threshold level set at an intermediate level between said amplitude. The amplitude of the logic signal transferred across the two circuits is thus compressed, thereby deereasing delay time for the signal to transfer between the two circuits.
摘要翻译：一种互连电路，具有设置在要连接的两个集成半导体中的一个中的电路部分，用于限制从所述一个电路输出的信号的电压幅度，以及设置在两个电路中的另一个中的另一个电路部分用于基于在所述幅度之间的中间电平设置的阈值电平来区分其中输入的信号的逻辑电平。因此，两个电路之间传输的逻辑信号的幅度被压缩，从而消除了在两个电路之间传输信号的延迟时间。

2. 发明授权

US06445237B1 Flip-flop circuit 有权
公开(公告)号：US06445237B1
公开(公告)日：2002-09-03
申请号：US09771642
申请日：2001-01-30
申请人： Satomi Horita
发明人： Satomi Horita
IPC分类号： H03K3037
摘要： Flip-flop circuits FF1 to FF6 are each constructed as a pair of cascade connected latch circuits 21 and 22 in an arbitrarily combination. The latch circuits L1 and L2 each comprises an input stage push-pull circuit PP and an output stage hold circuit HD as CVSL circuit. The latch circuit L1 includes an input stage having two pairs of nMOSTs 2 to 5 receiving input data DP and DN inputted thereto and connected in series each and in parallel connection of the pairs and a pair of nMOSTs 1 to 6 receiving a clock CP inputted thereto and connected to the opposite sides of the parallel connection. The output stage hold circuit HD includes a CVSI circuit having two pairs of nMOSTs 7 and 10 and a pair of pMOSTs 12 and 13 and an nMOST 11 receiving a clock CN inputted thereto. Thus obtained flip-flop (FF) circuit permits construction of a high density semiconductor integrated circuit (IC) with fast operation and low power consumption.

3. 发明授权

US06351170B1 Low power consumption type digital logic circuit 有权
标题翻译：低功耗型数字逻辑电路
公开(公告)号：US06351170B1
公开(公告)日：2002-02-26
申请号：US09583038
申请日：2000-05-30
申请人： Tsugio Takahashi , Satomi Horita
发明人： Tsugio Takahashi , Satomi Horita
IPC分类号： H03K1718
CPC分类号： H03K19/096 , H03K3/037
摘要： A gated clock type logic circuit is provided in which timing designing for a supply of a clock can be made easy and a period of time required for designing can be shortened. The gated clock type logic circuit has a gate circuit designed to allow a clock signal inputted in accordance with a level of a clock enabling signal to be passed or to be masked. An output of the gate circuit to control a latching timing of a latch circuit for receiving data is fed to a clock input terminal of the latch circuit. The gated clock type logic circuit is provided with a selector which receives an input data and an output data from the latch circuit and selects either of the input data or the output data by using a data enabling signal as a selecting signal and outputs it. An output from the selector is fed to a data input terminal of the latch circuit.
摘要翻译：提供了一种门控时钟型逻辑电路，其中可以使时钟供应的定时设计变得容易，并且可以缩短设计所需的时间段。门控时钟型逻辑电路具有门电路，其被设计为允许根据时钟使能信号的电平输入的时钟信号被通过或被屏蔽。用于控制用于接收数据的锁存电路的锁存定时的门电路的输出被馈送到锁存电路的时钟输入端。门控时钟型逻辑电路设置有选择器，其接收来自锁存电路的输入数据和输出数据，并通过使用数据使能信号作为选择信号来选择输入数据或输出数据中的任一个并输出。选择器的输出被馈送到锁存电路的数据输入端。

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