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1. 发明授权

US08188594B2 Input/output package architectures 有权
标题翻译：输入/输出包体系结构
公开(公告)号：US08188594B2
公开(公告)日：2012-05-29
申请号：US12587175
申请日：2009-10-01
申请人： Sanka Ganesan , Kemal Aygun , Chandrashekhar Ramaswamy , Eric Palmer , Henning Braunisch
发明人： Sanka Ganesan , Kemal Aygun , Chandrashekhar Ramaswamy , Eric Palmer , Henning Braunisch
IPC分类号： H01L23/34 , H01L23/10 , H01L23/28 , H01L23/495 , H01L23/48 , H01L23/52 , H01L23/04
CPC分类号： H01L23/34 , H01L23/367 , H01L23/498 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L23/50 , H01L23/66 , H01L2223/6627 , H01L2224/16225 , H01L2224/32245 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/15192 , H01L2924/19032 , H01L2224/0401
摘要： A high-speed I/O trace is part of an I/O package architecture for an integrated circuit package substrate. The integrated circuit package substrate includes an integrated heat spreader footprint on a die-side and the I/O trace to couple with an IC device to be disposed inside the IHS footprint. The I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint. The high-speed I/O trace can sustain a data flow rate from a processor in a range from 5 gigabits per second (Gb/s) to 40 Gb/s.
摘要翻译：高速I / O迹线是集成电路封装基板的I / O封装架构的一部分。集成电路封装衬底包括在芯片侧的集成的散热器占地面积，并且I / O迹线与要设置在IHS占地面积内的IC器件耦合。 I / O跟踪包括IHS封装之外的引脚输出端子，以连接到要设置在IHS占用空间之外的IC器件。高速I / O跟踪可以维持从5吉比特每秒（Gb / s）到40 Gb / s的处理器的数据流速。

2. 发明授权

US07705447B2 Input/output package architectures, and methods of using same 有权
公开(公告)号：US07705447B2
公开(公告)日：2010-04-27
申请号：US12286212
申请日：2008-09-29
申请人： Sanka Ganesan , Kemal Aygun , Chandrashekhar Ramaswamy , Eric Palmer , Henning Braunisch
发明人： Sanka Ganesan , Kemal Aygun , Chandrashekhar Ramaswamy , Eric Palmer , Henning Braunisch
IPC分类号： H01L23/34 , H01L23/495 , H01L23/10 , H01L23/28
CPC分类号： H01L23/34 , H01L23/367 , H01L23/498 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L23/50 , H01L23/66 , H01L2223/6627 , H01L2224/16225 , H01L2224/32245 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/15192 , H01L2924/19032 , H01L2224/0401
摘要： A high-speed I/O trace is part of an I/O package architecture for an integrated circuit package substrate. The integrated circuit package substrate includes an integrated heat spreader footprint on a die-side and the I/O trace to couple with an IC device to be disposed inside the IHS footprint. The I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint. The high-speed I/O trace can sustain a data flow rate from a processor in a range from 5 gigabits per second (Gb/s) to 40 Gb/s.

3. 发明申请

US20100096743A1 Input/output package architectures, and methods of using same 有权
标题翻译：输入/输出包体系结构及其使用方法
公开(公告)号：US20100096743A1
公开(公告)日：2010-04-22
申请号：US12587175
申请日：2009-10-01
申请人： Sanka Ganesan , Kemal Aygun , Chandrashekhar Ramaswamy , Eric Palmer , Henning Braunisch
发明人： Sanka Ganesan , Kemal Aygun , Chandrashekhar Ramaswamy , Eric Palmer , Henning Braunisch
IPC分类号： H01L23/36 , H01L23/48
CPC分类号： H01L23/34 , H01L23/367 , H01L23/498 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L23/50 , H01L23/66 , H01L2223/6627 , H01L2224/16225 , H01L2224/32245 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/15192 , H01L2924/19032 , H01L2224/0401
摘要： A high-speed I/O trace is part of an I/O package architecture for an integrated circuit package substrate. The integrated circuit package substrate includes an integrated heat spreader footprint on a die-side and the I/O trace to couple with an IC device to be disposed inside the IHS footprint. The I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint. The high-speed I/O trace can sustain a data flow rate from a processor in a range from 5 gigabits per second (Gb/s) to 40 Gb/s.
摘要翻译：高速I / O迹线是集成电路封装基板的I / O封装架构的一部分。集成电路封装衬底包括在芯片侧的集成的散热器占地面积，并且I / O迹线与要设置在IHS占地面积内的IC器件耦合。 I / O跟踪包括IHS封装之外的引脚输出端子，以连接到要设置在IHS占用空间之外的IC器件。高速I / O跟踪可以维持从5吉比特每秒（Gb / s）到40 Gb / s的处理器的数据流速。

4. 发明申请

US20100078781A1 INPUT/OUTPUT PACKAGE ARCHITECTURES, AND METHODS OF USING SAME 有权
标题翻译：输入/输出包装结构及其使用方法
公开(公告)号：US20100078781A1
公开(公告)日：2010-04-01
申请号：US12286212
申请日：2008-09-29
申请人： Sanka Ganesan , Kemal Aygun , Chandrashekhar Ramaswamy , Eric Palmer , Henning Braunisch
发明人： Sanka Ganesan , Kemal Aygun , Chandrashekhar Ramaswamy , Eric Palmer , Henning Braunisch
IPC分类号： H01L23/50 , H01L21/60
CPC分类号： H01L23/34 , H01L23/367 , H01L23/498 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L23/50 , H01L23/66 , H01L2223/6627 , H01L2224/16225 , H01L2224/32245 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/15192 , H01L2924/19032 , H01L2224/0401
摘要： A high-speed I/O trace is part of an I/O package architecture for an integrated circuit package substrate. The integrated circuit package substrate includes an integrated heat spreader footprint on a die-side and the I/O trace to couple with an IC device to be disposed inside the IHS footprint. The I/O trace includes a pin-out terminal outside the IHS footprint to couple to an IC device to be disposed outside the IHS footprint. The high-speed I/O trace can sustain a data flow rate from a processor in a range from 5 gigabits per second (Gb/s) to 40 Gb/s.
摘要翻译：高速I / O迹线是集成电路封装基板的I / O封装架构的一部分。集成电路封装衬底包括在芯片侧的集成的散热器占地面积，并且I / O迹线与要设置在IHS占地面积内的IC器件耦合。 I / O跟踪包括IHS封装之外的引脚输出端子，以连接到要设置在IHS占用空间之外的IC器件。高速I / O跟踪可以维持从5吉比特每秒（Gb / s）到40 Gb / s的处理器的数据流速。

5. 发明申请

US20070117339A1 VIA INCLUDING MULTIPLE ELECTRICAL PATHS 有权
标题翻译：通过多种电气方式
公开(公告)号：US20070117339A1
公开(公告)日：2007-05-24
申请号：US11626606
申请日：2007-01-24
申请人： Todd Myers , Nicholas Watts , Eric Palmer , Renee Defeo , Jui Lim
发明人： Todd Myers , Nicholas Watts , Eric Palmer , Renee Defeo , Jui Lim
IPC分类号： H01L21/00 , H01L21/20 , H01L23/02
CPC分类号： H01L23/49827 , H01L2924/0002 , H05K1/115 , H05K3/064 , H05K3/403 , H05K3/4644 , H05K2201/09645 , H05K2201/09827 , H01L2924/00
摘要： A method for forming an plurality of paths on a substrate includes drilling an opening for a via to a depth to expose a first pad and a second pad, lining the opening with a conductive material, and insulating a first portion of the lining in the opening from a second portion of the lining in the opening to form a first electrical path contacting the first pad and a second electrical path contacting the second pad.
摘要翻译：一种用于在基板上形成多个路径的方法包括：将用于通孔的开口钻出一定深度，以暴露第一垫和第二垫，用导电材料衬套开口，并将开口的第一部分在开口从开口中的衬里的第二部分形成接触第一焊盘的第一电路径和接触第二焊盘的第二电路径。

6. 发明申请

US20050224989A1 Passive within via 有权
标题翻译：被动内部通过
公开(公告)号：US20050224989A1
公开(公告)日：2005-10-13
申请号：US10815464
申请日：2004-03-31
申请人： Todd Myers , Nicholas Watts , Eric Palmer , Jui Lim
发明人： Todd Myers , Nicholas Watts , Eric Palmer , Jui Lim
IPC分类号： H01G4/005 , H01L21/48 , H01L23/498 , H01L23/66 , H05K1/11 , H05K1/16 , H05K3/40
CPC分类号： H01L21/76897 , H01L21/486 , H01L23/481 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/64 , H01L23/66 , H01L2223/6616 , H01L2924/0002 , H01L2924/15311 , H01L2924/1902 , H05K1/115 , H05K1/162 , H05K1/165 , H05K1/167 , H05K3/06 , H05K3/4053 , H05K3/421 , H05K2201/086 , H05K2201/09509 , H05K2201/09563 , H05K2201/0959 , H05K2201/09645 , H05K2201/09663 , H05K2201/09763 , H05K2201/09809 , H05K2201/09827 , H05K2201/09981 , Y10S257/916 , Y10T29/435 , Y10T29/49002 , Y10T29/49126 , Y10T29/4913 , Y10T29/49131 , Y10T29/49133 , Y10T29/49147 , Y10T29/49165 , H01L2924/00
摘要： A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.
摘要翻译：形成与通孔相关的器件的方法包括形成开口或通孔，并在通孔内形成至少一对导电通路。还公开了一种在其中具有一对导电路径的通孔。

7. 发明授权

US06362823B1 Intellectual structure for single-point visual representation of n-dimensional points using broken-line parallel coordinates 失效
标题翻译：使用虚线平行坐标的n维点的单点视觉表示的智能结构
公开(公告)号：US06362823B1
公开(公告)日：2002-03-26
申请号：US09344600
申请日：1999-06-25
申请人： Robert R. Johnson , Marc Palmer , Eric Palmer , Rodney D. Millar
发明人： Robert R. Johnson , Marc Palmer , Eric Palmer , Rodney D. Millar
IPC分类号： G06T1120
CPC分类号： G06T11/206
摘要： A method for utilizing an intellectual structure for visualizing a system of multi-variate data points in a parallel coordinate system, identifying an area of interest within the system, and then transforming a selected portion of the system for visualization in single-point representations of n-dimensional points using broken-line parallel coordinates, where the n point representations of conventional parallel coordinates are brought back into a single point representation that is the single point vector resultant of n dimensional spaces viewable in familiar three dimensional display space.
摘要翻译：一种用于利用智能结构来可视化平行坐标系中的多变量数据点的系统的方法，识别系统内的感兴趣区域，然后在n的单点表示中变换用于可视化的系统的选定部分使用虚线平行坐标的维度点，其中常规平行坐标的n点表示被带回单点表示，其是在熟悉的三维显示空间中可见的n维空间的单点向量结果。

8. 发明授权

US4643324A Waste bin having fire preventing lid 失效
标题翻译：垃圾桶有防火盖
公开(公告)号：US4643324A
公开(公告)日：1987-02-17
申请号：US841450
申请日：1986-03-19
申请人： Eric Palmer
发明人： Eric Palmer
IPC分类号： B65F1/14 , B65F1/16 , B65D25/00
CPC分类号： B65F1/16 , B65F1/14 , B65F2001/1494
摘要： The disclosure relates to a waste bin having an inner steel container for refuse and an outer thermoplastic hood form cover having a domed top wall and side ports through which refuse may be deposited in the container. A lid for the container is mounted on the underside of the top wall of the cover and is supported on a central stud extending through the cover by means of a polythene washer held on the stud by a nut. If a fire should develop in the container the resulting heat will cause the washer to melt releasing the cover to fall onto the top of the container therefore preventing air flow into the container to restrict and extinguish the fire.
摘要翻译：本公开涉及具有用于垃圾的内钢容器的垃圾箱和具有圆顶顶壁和侧端口的外部热塑性罩盖形式盖，垃圾可通过该端口沉积在容器中。用于容器的盖子安装在盖的顶壁的下侧上，并且通过由螺母保持在螺柱上的聚乙烯垫圈支撑在延伸穿过盖的中心柱上。如果在容器内发生火灾，则所产生的热量将导致洗衣机熔化而释放盖子以落入容器的顶部，从而防止空气流入容器以限制和熄灭火。

9. 发明申请

US20050133918A1 Via including multiple electrical paths 有权
标题翻译：通过包括多个电路径
公开(公告)号：US20050133918A1
公开(公告)日：2005-06-23
申请号：US10740957
申请日：2003-12-17
申请人： Todd Myers , Nicholas Watts , Eric Palmer , Renee Defeo , Jui Lim
发明人： Todd Myers , Nicholas Watts , Eric Palmer , Renee Defeo , Jui Lim
IPC分类号： H01L23/02 , H01L23/498 , H05K1/11 , H05K3/06 , H05K3/40 , H05K3/46
CPC分类号： H01L23/49827 , H01L2924/0002 , H05K1/115 , H05K3/064 , H05K3/403 , H05K3/4644 , H05K2201/09645 , H05K2201/09827 , H01L2924/00
摘要： A system includes a device having at least one integrated circuit. The integrated circuit further includes a first layer of conductive material, a second layer of conductive material, and a via having multiple electrical paths for interconnecting the first layer of conductive material and the second layer of conductive material. A method for forming a via includes drilling an opening to a depth to expose a first pad and a second pad, lining the opening with a conductive material, and insulating a first portion of the lining in the opening from a second portion of the lining in the opening to form a first electrical path contacting the first pad and a second electrical path contacting the second pad.
摘要翻译：一种系统包括具有至少一个集成电路的装置。集成电路还包括第一导电材料层，第二导电材料层，以及具有用于互连导电材料的第一层和第二导电材料层的多条电路的通路。用于形成通孔的方法包括将开口钻出一定深度以露出第一垫和第二垫，用导电材料衬套开口，并将开口中的衬里的第一部分与衬里的第二部分绝缘所述开口形成接触所述第一焊盘的第一电路径和与所述第二焊盘接触的第二电路径。

10. 发明申请

US20050121769A1 Stacked integrated circuit packages and methods of making the packages 审中-公开
标题翻译：堆叠集成电路封装和制造封装的方法
公开(公告)号：US20050121769A1
公开(公告)日：2005-06-09
申请号：US10729544
申请日：2003-12-05
申请人： Nicholas Watts , Eric Palmer , Jui Lim , Todd Myers , Boonsri Wangmaneerat
发明人： Nicholas Watts , Eric Palmer , Jui Lim , Todd Myers , Boonsri Wangmaneerat
IPC分类号： H01L21/44 , H01L21/98 , H01L23/04 , H01L23/498 , H01L25/10
CPC分类号： H01L25/50 , H01L23/4985 , H01L25/105 , H01L2224/16 , H01L2225/1058 , H01L2924/15311 , H01L2924/15331
摘要： In some embodiments, a method includes providing a substrate, providing a coverlay blank, laminating the coverlay blank to the substrate, and forming at least one opening in the coverlay blank by photolithography.
摘要翻译：在一些实施例中，一种方法包括提供衬底，提供覆盖层坯料，将覆盖层坯料层压到衬底上，以及通过光刻法在覆盖层坯料中形成至少一个开口。

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