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1. 发明授权

US07817761B2 Test techniques for a delay-locked loop receiver interface 有权
标题翻译：延迟锁定环路接收机接口的测试技术
公开(公告)号：US07817761B2
公开(公告)日：2010-10-19
申请号：US11756674
申请日：2007-06-01
申请人： Meei-Ling Chiang , Dwight K. Elvey , Sanjeev Maheshwari , Emerson S. Fang
发明人： Meei-Ling Chiang , Dwight K. Elvey , Sanjeev Maheshwari , Emerson S. Fang
IPC分类号： H04L7/00 , H03L7/06
CPC分类号： G01R31/3016 , G01R31/31725 , H03L7/07 , H03L7/0814 , H03L7/091
摘要： An integrated circuit includes a variable delay circuit configured to generate at least one delayed clock signal based on a first clock signal and a first control signal. The integrated circuit includes a control circuit configured to generate a count value based on a second input signal and a second control signal. The first clock signal is a first version of the at least one delayed clock signal. At least one of the second input signal and the second control signal is a second version of the at least one delayed clock signal and the count value is indicative of a frequency characteristic of the at least one delayed clock signal. The integrated circuit is configured to monotonically vary the first control signal over a range of values and the count value is determined for individual values of the control signal.
摘要翻译：集成电路包括可变延迟电路，其被配置为基于第一时钟信号和第一控制信号产生至少一个延迟的时钟信号。集成电路包括配置为基于第二输入信号和第二控制信号产生计数值的控制电路。第一时钟信号是至少一个延迟时钟信号的第一版本。所述第二输入信号和所述第二控制信号中的至少一个是所述至少一个延迟时钟信号的第二版本，并且所述计数值指示所述至少一个延迟的时钟信号的频率特性。集成电路被配置为在一个值的范围内单调地改变第一控制信号，并且针对控制信号的各个值确定计数值。

2. 发明申请

US20080273528A1 PHASE SELECT CIRCUIT WITH REDUCED HYSTERESIS EFFECT 有权
标题翻译：相位选择电路具有减少的滞后效应
公开(公告)号：US20080273528A1
公开(公告)日：2008-11-06
申请号：US11742860
申请日：2007-05-01
申请人： Sanjeev Maheshwari , Meei-Ling Chiang , Emerson S. Fang
发明人： Sanjeev Maheshwari , Meei-Ling Chiang , Emerson S. Fang
IPC分类号： H04L12/50
CPC分类号： H04L7/0337 , H03L7/07 , H03L7/0814 , H04L7/0008 , H04L7/0025
摘要： A phase signal select circuit includes a supporting path coupled to a tri-state inverter circuit. The supporting path reduces effects of hysteresis on signal transfer. An apparatus includes at least one input node responsive to a respective one of at least one input signal. The apparatus includes at least one circuit coupled to a respective one of the at least one input node and coupled to an output node. Individual ones of the at least one circuit are configured to provide a version of the respective input signal to the output node in response to a first state of a respective select signal. The apparatus includes at least one second circuit coupled to a respective one of the at least one circuit. The at least one second circuit is configured to toggle nodes of the at least one circuit in response to a second state of the respective select signal.
摘要翻译：相位信号选择电路包括耦合到三态反相器电路的支撑路径。支持路径减少了滞后对信号传输的影响。一种装置包括响应于至少一个输入信号中的相应一个的至少一个输入节点。该装置包括耦合到至少一个输入节点中的相应一个并耦合到输出节点的至少一个电路。所述至少一个电路中的各个电路被配置为响应于相应选择信号的第一状态而将相应输入信号的形式提供给输出节点。该装置包括耦合到至少一个电路中的相应一个电路的至少一个第二电路。至少一个第二电路被配置为响应于相应选择信号的第二状态来切换至少一个电路的节点。

3. 发明申请

US20080272814A1 PARALLEL MULTIPLEXING DUTY CYCLE ADJUSTMENT CIRCUIT WITH PROGRAMMABLE RANGE CONTROL 有权
标题翻译：具有可编程范围控制的并行多路复用占空比调整电路
公开(公告)号：US20080272814A1
公开(公告)日：2008-11-06
申请号：US11742845
申请日：2007-05-01
申请人： Meei-Ling Chiang , Sanjeev Maheshwari , Emerson S. Fang
发明人： Meei-Ling Chiang , Sanjeev Maheshwari , Emerson S. Fang
IPC分类号： H03K3/017
CPC分类号： H03K3/017
摘要： A receive interface circuit includes a duty cycle adjustment circuit that adjusts the duty cycle of a reference clock signal based, at least in part, on a selected number of duty cycle adjustment units and a selected range of duty cycle adjustment. The duty cycle adjustment circuit may select as the reference clock signal one of a clock signal and at least a lower version of the clock signal in parallel with the duty cycle adjustment.
摘要翻译：接收接口电路包括占空比调整电路，其至少部分地基于选定数量的占空比调整单元和所选择的占空比调整范围来调整参考时钟信号的占空比。占空比调整电路可以与占空比调整并行地选择时钟信号和至少较低版本的时钟信号之一作为参考时钟信号。

4. 发明授权

US07750711B2 Phase select circuit with reduced hysteresis effect 有权
标题翻译：具有减小滞后效应的相位选择电路
公开(公告)号：US07750711B2
公开(公告)日：2010-07-06
申请号：US11742860
申请日：2007-05-01
申请人： Sanjeev Maheshwari , Meei-Ling Chiang , Emerson S. Fang
发明人： Sanjeev Maheshwari , Meei-Ling Chiang , Emerson S. Fang
IPC分类号： H03H11/26
CPC分类号： H04L7/0337 , H03L7/07 , H03L7/0814 , H04L7/0008 , H04L7/0025
摘要： A phase signal select circuit includes a supporting path coupled to a tri-state inverter circuit. The supporting path reduces effects of hysteresis on signal transfer. An apparatus includes at least one input node responsive to a respective one of at least one input signal. The apparatus includes at least one circuit coupled to a respective one of the at least one input node and coupled to an output node. Individual ones of the at least one circuit are configured to provide a version of the respective input signal to the output node in response to a first state of a respective select signal. The apparatus includes at least one second circuit coupled to a respective one of the at least one circuit. The at least one second circuit is configured to toggle nodes of the at least one circuit in response to a second state of the respective select signal.
摘要翻译：相位信号选择电路包括耦合到三态反相器电路的支撑通路。支持路径减少了滞后对信号传输的影响。一种装置包括响应于至少一个输入信号中的相应一个的至少一个输入节点。该装置包括耦合到至少一个输入节点中的相应一个并耦合到输出节点的至少一个电路。所述至少一个电路中的各个电路被配置为响应于相应选择信号的第一状态而将相应输入信号的形式提供给输出节点。该装置包括耦合到至少一个电路中的相应一个电路的至少一个第二电路。至少一个第二电路被配置为响应于相应选择信号的第二状态来切换至少一个电路的节点。

5. 发明授权

US07545190B2 Parallel multiplexing duty cycle adjustment circuit with programmable range control 有权
标题翻译：并行多路复用占空比调节电路，具有可编程范围控制
公开(公告)号：US07545190B2
公开(公告)日：2009-06-09
申请号：US11742845
申请日：2007-05-01
申请人： Meei-Ling Chiang , Sanjeev Maheshwari , Emerson S. Fang
发明人： Meei-Ling Chiang , Sanjeev Maheshwari , Emerson S. Fang
IPC分类号： H03K3/017
CPC分类号： H03K3/017
摘要： A receive interface circuit includes a duty cycle adjustment circuit that adjusts the duty cycle of a reference clock signal based, at least in part, on a selected number of duty cycle adjustment units and a selected range of duty cycle adjustment. The duty cycle adjustment circuit may select as the reference clock signal one of a clock signal and at least a lower version of the clock signal in parallel with the duty cycle adjustment.
摘要翻译：接收接口电路包括占空比调整电路，其至少部分地基于选定数量的占空比调整单元和所选择的占空比调整范围来调整参考时钟信号的占空比。占空比调整电路可以与占空比调整并行地选择时钟信号和至少较低版本的时钟信号之一作为参考时钟信号。

6. 发明申请

US20080297216A1 TEST TECHNIQUES FOR A DELAY-LOCKED LOOP RECEIVER INTERFACE 有权
标题翻译：延迟环路接收机接口的测试技术
公开(公告)号：US20080297216A1
公开(公告)日：2008-12-04
申请号：US11756674
申请日：2007-06-01
申请人： Meei-Ling Chiang , Dwight K. Elvey , Sanjeev Maheshwari , Emerson S. Fang
发明人： Meei-Ling Chiang , Dwight K. Elvey , Sanjeev Maheshwari , Emerson S. Fang
IPC分类号： H03L7/06 , G01R31/28
CPC分类号： G01R31/3016 , G01R31/31725 , H03L7/07 , H03L7/0814 , H03L7/091
摘要： An integrated circuit includes a variable delay circuit configured to generate at least one delayed clock signal based on a first clock signal and a first control signal. The integrated circuit includes a control circuit configured to generate a count value based on a second input signal and a second control signal. The first clock signal is a first version of the at least one delayed clock signal. At least one of the second input signal and the second control signal is a second version of the at least one delayed clock signal and the count value is indicative of a frequency characteristic of the at least one delayed clock signal. The integrated circuit is configured to monotonically vary the first control signal over a range of values and the count value is determined for individual values of the control signal.
摘要翻译：集成电路包括可变延迟电路，其被配置为基于第一时钟信号和第一控制信号产生至少一个延迟的时钟信号。集成电路包括配置为基于第二输入信号和第二控制信号产生计数值的控制电路。第一时钟信号是至少一个延迟时钟信号的第一版本。所述第二输入信号和所述第二控制信号中的至少一个是所述至少一个延迟时钟信号的第二版本，并且所述计数值指示所述至少一个延迟的时钟信号的频率特性。集成电路被配置为在一个值的范围内单调地改变第一控制信号，并且针对控制信号的各个值确定计数值。

7. 发明授权

US06295016B1 Pipeline analog to digital (A/D) converter with relaxed accuracy requirement for sample and hold stage 有权
标题翻译：管道模拟数字（A / D）转换器，对采样和保持级具有放宽的精度要求
公开(公告)号：US06295016B1
公开(公告)日：2001-09-25
申请号：US09506208
申请日：2000-02-17
申请人： Meei-Ling Chiang
发明人： Meei-Ling Chiang
IPC分类号： H03M138
CPC分类号： H03M1/0602 , H03M1/0695 , H03M1/442
摘要： A pipeline analog to digital (A/D) converter for converting an analog input signal into a digital representation of the analog signal. The pipeline A/D converter has a sample and hold stage, the sample and hold stage sampling and holding the analog input signal and outputting a sampled and held signal. The pipeline A/D converter also has a first analog signal converter stage, the first analog converter stage producing a digital output based on the sampled and held signal, from which a most significant bit of the digital representation of the analog input signal is derived. The first analog converter stage produces a residue signal based on a comparison of the analog input signal and an analog representation of the digital output. The pipeline A/D converter has at least one additional stage, the additional stage producing a subsequent digital output based on the residue signal produced by the first analog signal converter stage, at least one bit which is less significant than the most significant bit being derived from the subsequent digital output.
摘要翻译：一种用于将模拟输入信号转换为模拟信号的数字表示的流水线模数（A / D）转换器。流水线A / D转换器具有采样和保持级，采样和保持级采样并保持模拟输入信号并输出采样和保持的信号。流水线A / D转换器还具有第一模拟信号转换器级，第一模拟转换器级基于采样和保持的信号产生数字输出，从中得到模拟输入信号的数字表示的最高有效位。第一模拟转换器级基于模拟输入信号和数字输出的模拟表示的比较产生残留信号。流水线A / D转换器具有至少一个附加级，附加级基于由第一模拟信号转换器级产生的残余信号产生后续的数字输出，至少一个比所得到的最高有效位的有效位少从后续的数字输出。

8. 发明授权

US06323800B1 Pipeline analog to digital (a/d) converter with lengthened hold operation of a first stage 有权
公开(公告)号：US06323800B1
公开(公告)日：2001-11-27
申请号：US09506316
申请日：2000-02-17
申请人： Meei-Ling Chiang
发明人： Meei-Ling Chiang
IPC分类号： H03M138
CPC分类号： H03M1/442 , H03M1/0695
摘要： A pipeline analog to digital (A/D) converter having a sample and hold stage which samples an analog input signal during a primary clock signal and holds during a secondary clock signal. The A/D converter has an analog signal converter stage which converts and latches the sampled and held voltage signal into a digital output during the secondary clock signal. The analog signal converter stage generating a residue signal based on a comparison of the sampled and held voltage signal and from an analog representation of the digital output, the analog signal converter stage samples the sampled and held voltage signal during the secondary clock signal and holds the residue signal during the primary clock signal. The primary and secondary clock signals together form a two phase nonoverlapping clock having a regular period with a length defined by the duty cycles of the primary and secondary clock signals. The duty cycle of the primary clock signal being less than the duty cycle of the secondary clock signal. According to another aspect of the invention, an A/D converter has a sample and hold stage which samples an analog input signal during a first clock signal and holds a sampled voltage signal during a second clock signal. The A/D converter has an analog signal converter stage, which converts and latches the sampled and held voltage signal into a digital output during the second clock signal. The analog signal converter stage generating a residue signal based on a comparison of the analog input signal and from an analog representation of the digital output, the analog signal converter stage samples the analog input signal during the first clock signal and holds the residue signal during a third clock signal. The first clock signal and the second clock signal form a first two phase nonoverlapping clock and the third clock pulse signal forms a second two phase nonoverlapping clock with a fourth clock pulse signal. The fourth clock signal having a duty cycle of less than, greater than or equal to 50% of the period of the second nonoverlapping clock, and the pulse of the first clock signal and the pulse of the second clock signal both overlapping with the pulse of the fourth clock signal. The duty cycle of the first clock signal is optionally less than the duty cycle of the second clock signal.

9. 发明申请

US20110304407A1 AUTOMATIC AMPLITUDE CONTROL FOR VOLTAGE CONTROLLED OSCILLATOR 有权
标题翻译：电压控制振荡器的自动振幅控制
公开(公告)号：US20110304407A1
公开(公告)日：2011-12-15
申请号：US12813071
申请日：2010-06-10
申请人： Meei-Ling Chiang , Dennis M. Fischette , Alvin Leng Sun Loke , Michael M. Oshima
发明人： Meei-Ling Chiang , Dennis M. Fischette , Alvin Leng Sun Loke , Michael M. Oshima
IPC分类号： H03L5/00
CPC分类号： H03L5/00 , H03L7/099 , H03L7/10
摘要： A circuit and method for calibrating a VCO (voltage controlled oscillator) is disclosed. In one embodiment, a circuit includes a VCO and a bias control circuit coupled to a tail node of the VCO. An amplitude control unit may also be coupled to the tail node, wherein the amplitude control unit is configured to determine the amplitude of a VCO output signal based on a voltage present on the tail node. The amplitude control unit may also be configured to generate a bias voltage based on the amplitude of the VCO output signal and a target voltage. The bias control circuit may be coupled to receive the bias voltage from the amplitude control unit and may be further configured to adjust the voltage on the tail node based on the received bias voltage.
摘要翻译：公开了一种用于校准VCO（压控振荡器）的电路和方法。在一个实施例中，电路包括耦合到VCO的尾部节点的VCO和偏置控制电路。幅度控制单元还可以耦合到尾部节点，其中，幅度控制单元被配置为基于存在于尾部节点上的电压来确定VCO输出信号的幅度。幅度控制单元还可以被配置为基于VCO输出信号的幅度和目标电压来产生偏置电压。偏置控制电路可以被耦合以从幅度控制单元接收偏置电压，并且还可以被配置为基于所接收的偏置电压来调整尾部节点上的电压。

10. 发明授权

US06337651B1 Pipeline analog to digital (A/D) converter with relaxed accuracy requirement for sample and hold stage 有权
标题翻译：管道模拟数字（A / D）转换器，对采样和保持级具有放宽的精度要求
公开(公告)号：US06337651B1
公开(公告)日：2002-01-08
申请号：US09506284
申请日：2000-02-17
申请人： Meei-Ling Chiang
发明人： Meei-Ling Chiang
IPC分类号： H03M138
CPC分类号： H03M1/442 , H03M1/0695
摘要： A pipeline analog to digital (A/D) converter. The pipeline A/D converter having a sample and hold amplifier stage, the sample and hold amplifier stage sampling an analog input signal during a first clock pulse signal. The pipeline A/D converter having an analog signal converter stage, the analog signal converter stage sampling the analog input signal during a first clock pulse signal. According to another aspect of the invention, the pipeline A/D converter converts an analog input signal into a digital representation of the analog input signal. The pipeline A/D converter has a clock generator, the clock generator generating a first clock pulse signal, a second clock pulse signal and a third clock pulse signal. A sample and hold stage samples an analog input signal during the pulse of the first clock signal and holds a sampled voltage signal during the pulse of the second clock signal. A first analog signal converter stage converts and latches the sampled and held voltage signal into a digital output during the pulse of the second clock signal, a most significant bit of the digital representation of the analog input signal being derived from the digital output. The first analog signal converter stage generating a residue signal based on a comparison of the analog input signal and from an analog representation of the digital output. The first analog signal converter stage sampling the analog input signal during the pulse of the first clock signal and holding the residue signal during the pulse of the third clock signal.
摘要翻译：一种管线模数（A / D）转换器。具有采样和保持放大器级的流水线A / D转换器，采样和保持放大器级在第一时钟脉冲信号期间对模拟输入信号进行采样。具有模拟信号转换器级的管线A / D转换器，模拟信号转换器级在第一时钟脉冲信号期间对模拟输入信号进行采样。根据本发明的另一方面，流水线A / D转换器将模拟输入信号转换为模拟输入信号的数字表示。管线A / D转换器具有时钟发生器，时钟发生器产生第一时钟脉冲信号，第二时钟脉冲信号和第三时钟脉冲信号。采样和保持级在第一时钟信号的脉冲期间采样模拟输入信号，并且在第二时钟信号的脉冲期间保持采样的电压信号。第一模拟信号转换器级在第二时钟信号的脉冲期间将采样和保持的电压信号转换并锁存为数字输出，模拟输入信号的数字表示的最高有效位是从数字输出导出的。第一模拟信号转换器级基于模拟输入信号与数字输出的模拟表示的比较产生残留信号。第一模拟信号转换器级在第一时钟信号的脉冲期间对模拟输入信号进行采样，并在第三时钟信号的脉冲期间保持残留信号。

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