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1. 发明授权

US09065477B2 Linear and DC-accurate frontend DAC and input structure 有权
标题翻译：线性和直流精度前端DAC和输入结构
公开(公告)号：US09065477B2
公开(公告)日：2015-06-23
申请号：US14179279
申请日：2014-02-12
申请人： Sanjay Rajasekhar , Abhilasha Kawle , Roberto S Maurino , Srikanth Nittala
发明人： Sanjay Rajasekhar , Abhilasha Kawle , Roberto S Maurino , Srikanth Nittala
IPC分类号： H03M1/66
CPC分类号： H03M1/0678 , H03M1/0863 , H03M3/464 , Y10T307/76
摘要： A digital-to-analog (DAC) element may include a plurality of switches arranged to form two circuit branches between a current source and a first and a second outputs. The first circuit branch may include two switches defining parallel current paths between the current source and the first output terminal. The second circuit branch may include two switches defining parallel current paths between the current source and the second output terminal. A control circuit, responsive to an input signal that selects one of the circuit branches, may provide control signals to close one of switches in the selected circuit branch in a first portion of a clock cycle and to close the other of the switches in the selected circuit branch in a second portion of the clock cycle.
摘要翻译：数模（DAC）元件可以包括布置成在电流源和第一和第二输出之间形成两个电路分支的多个开关。第一电路支路可以包括限定电流源和第一输出端之间的并联电流路径的两个开关。第二电路支路可以包括定义电流源和第二输出端之间的并联电流路径的两个开关。响应于选择电路分支之一的输入信号的控制电路可以提供控制信号以在时钟周期的第一部分中关闭所选择的电路分支中的一个开关，并且关闭所选择的开关中的另一个电路在时钟周期的第二部分中分支。

2. 发明申请

US20090102694A1 High Speed Parallel Procesing Digita Path for SAR ADC 有权
标题翻译： SAR ADC的高速并行处理数字通路
公开(公告)号：US20090102694A1
公开(公告)日：2009-04-23
申请号：US12254678
申请日：2008-10-20
申请人： Srikanth Nittala , Jeremy Gorbold , Mahesh Madhavan
发明人： Srikanth Nittala , Jeremy Gorbold , Mahesh Madhavan
IPC分类号： H03M1/34
CPC分类号： H03M1/462 , H03M1/0673 , H03M1/468 , H03M1/687
摘要： The analog-to-digital for converter (ADC) for converting an analog value into a digital equivalent using a parallel digital data path is disclosed. In one example embodiment, the ADC includes a switched capacitor DAC having an input to receive an analog value via analog sample and hold circuit. A comparator is coupled to the switched capacitor DAC. A successive approximation register (SAR) is coupled to the comparator. A plurality of logic blocks is coupled to the SAR. A plurality of thermometric encoders is coupled to the associated plurality of logic blocks. A plurality of MUXs is coupled to the associated plurality of thermometric encoders and the comparator, wherein the plurality of MUXs having associated outputs that is coupled to the input of the switched capacitor DAC.
摘要翻译：公开了用于使用并行数字数据路径将模拟值转换成数字等效的用于转换器（ADC）的模拟数字转换器。在一个示例实施例中，ADC包括具有经由模拟采样和保持电路接收模拟值的输入的开关电容器DAC。比较器耦合到开关电容器DAC。逐次逼近寄存器（SAR）耦合到比较器。多个逻辑块耦合到SAR。多个温度测量编码器耦合到相关联的多个逻辑块。多个MUX耦合到相关联的多个温度测量编码器和比较器，其中多个MUX具有耦合到开关电容器DAC的输入的相关输出。

3. 发明授权

US07839319B2 High speed parallel procesing digita path for SAR ADC 有权
标题翻译： SAR ADC的高速并行处理数字通路
公开(公告)号：US07839319B2
公开(公告)日：2010-11-23
申请号：US12254678
申请日：2008-10-20
申请人： Srikanth Nittala , Jeremy Gorbold , Mahesh Madhavan
发明人： Srikanth Nittala , Jeremy Gorbold , Mahesh Madhavan
IPC分类号： H03M1/34
CPC分类号： H03M1/462 , H03M1/0673 , H03M1/468 , H03M1/687
摘要： The analog-to-digital for converter (ADC) for converting an analog value into a digital equivalent using a parallel digital data path is disclosed. In one example embodiment, the ADC includes a switched capacitor DAC having an input to receive an analog value via analog sample and hold circuit. A comparator is coupled to the switched capacitor DAC. A successive approximation register (SAR) is coupled to the comparator. A plurality of logic blocks is coupled to the SAR. A plurality of thermometric encoders is coupled to the associated plurality of logic blocks. A plurality of MUXs is coupled to the associated plurality of thermometric encoders and the comparator, wherein the plurality of MUXs having associated outputs that is coupled to the input of the switched capacitor DAC.
摘要翻译：公开了用于使用并行数字数据路径将模拟值转换成数字等效的用于转换器（ADC）的模拟数字转换器。在一个示例实施例中，ADC包括具有经由模拟采样和保持电路接收模拟值的输入的开关电容器DAC。比较器耦合到开关电容器DAC。逐次逼近寄存器（SAR）耦合到比较器。多个逻辑块耦合到SAR。多个温度测量编码器耦合到相关联的多个逻辑块。多个MUX耦合到相关联的多个温度测量编码器和比较器，其中多个MUX具有耦合到开关电容器DAC的输入的相关输出。

4. 发明授权

US07439898B1 Parallel digital processing for reducing delay in SAR ADC logic 有权
标题翻译：用于减少SAR ADC逻辑延迟的并行数字处理
公开(公告)号：US07439898B1
公开(公告)日：2008-10-21
申请号：US11755761
申请日：2007-05-31
申请人： Srikanth Nittala , Jeremy Gorbold , Mahesh Madhavan
发明人： Srikanth Nittala , Jeremy Gorbold , Mahesh Madhavan
IPC分类号： H03M1/34
CPC分类号： H03M1/462 , H03M1/0673 , H03M1/468 , H03M1/687
摘要： The analog-to-digital for converter (ADC) for converting an analog value into a digital equivalent using a parallel digital data path is disclosed. In one example embodiment, the ADC includes a switched capacitor DAC having an input to receive an analog value via analog sample and hold circuit. A comparator is coupled to the switched capacitor DAC. A successive approximation register (SAR) is coupled to the comparator. A plurality of logic blocks is coupled to the SAR. A plurality of thermometric encoders is coupled to the associated plurality of logic blocks. A plurality of MUXs is coupled to the associated plurality of thermometric encoders and the comparator, wherein the plurality of MUXs having associated outputs that is coupled to the input of the switched capacitor DAC.
摘要翻译：公开了用于使用并行数字数据路径将模拟值转换成数字等效的用于转换器（ADC）的模拟数字转换器。在一个示例实施例中，ADC包括具有经由模拟采样和保持电路接收模拟值的输入的开关电容器DAC。比较器耦合到开关电容器DAC。逐次逼近寄存器（SAR）耦合到比较器。多个逻辑块耦合到SAR。多个温度测量编码器耦合到相关联的多个逻辑块。多个MUX耦合到相关联的多个温度测量编码器和比较器，其中多个MUX具有耦合到开关电容器DAC的输入的相关输出。

5. 发明授权

US08769364B2 System and method for digital gain error correction 有权
标题翻译：数字增益纠错系统和方法
公开(公告)号：US08769364B2
公开(公告)日：2014-07-01
申请号：US13277396
申请日：2011-10-20
申请人： Srikanth Nittala
发明人： Srikanth Nittala
IPC分类号： G06F11/00 , G06F11/30 , G08C25/00 , H03M13/00 , H04L1/00 , H04N1/405 , G06F5/01 , H03M1/06
CPC分类号： G06F11/00 , G06F5/01 , H03M1/0641 , H03M13/00 , H04N1/4052
摘要： A method for correcting digital gain error for a digital code includes receiving the digital code, generating a random number, adding a first dither to the digital code, in which a magnitude of the first dither is determined based on the random number, performing an operation on the digital code including the added dither with a factor to generate a scaled digital code, and subtracting a second dither corresponding to the first dither from the scaled digital code.
摘要翻译：一种用于校正数字码的数字增益误差的方法包括：接收数字码，产生一个随机数，根据该随机数确定第一个抖动的大小，将第一个抖动加到数字码上，执行一个操作包括具有产生缩放的数字代码的因子的添加的抖动的数字代码，以及从缩放的数字代码中减去对应于第一抖动的第二抖动。

6. 发明授权

US07023372B1 Method and apparatus for segmented, switched analog/digital converter 有权
标题翻译：用于分段，开关模拟/数字转换器的方法和装置
公开(公告)号：US07023372B1
公开(公告)日：2006-04-04
申请号：US11054064
申请日：2005-02-09
申请人： Ramesh Singh , Eamonn Byrne , Asif Ahmad , Srikanth Nittala , Shubha Govindachar
发明人： Ramesh Singh , Eamonn Byrne , Asif Ahmad , Srikanth Nittala , Shubha Govindachar
IPC分类号： H03M1/12
CPC分类号： H03M1/0682 , H03M1/468 , H03M1/806
摘要： A switched-capacitor circuit for use in analog-to-digital conversion samples an input signal with respect to a reference voltage such that it significantly reduces a DAC settling time interval during each bit trial. In one exemplary embodiment, the switched-capacitor circuit having first and second groups of capacitor banks is coupled to a first input of a comparator and to a control circuit which provides control signals such that during a switching sequence, an equal value of capacitance is selected from each of the first and second groups of capacitor banks to reduce the DAC settling time interval, thereby improving the conversion rate.
摘要翻译：用于模数转换的开关电容电路针对参考电压对输入信号进行采样，从而在每个位试验期间显着降低DAC稳定时间间隔。在一个示例性实施例中，具有第一组和第二组电容器组的开关电容器电路耦合到比较器的第一输入端，并提供给控制电路，该控制电路提供控制信号，使得在切换序列期间，选择相等的电容值从第一组和第二组电容器组中的每一个减少DAC建立时间间隔，从而提高转换速率。

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