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1. 发明授权

US6114212A Methods of fabricating bipolar junction transistors having an increased safe operating area 有权
标题翻译：制造具有增加的安全操作区域的双极结型晶体管的方法
公开(公告)号：US6114212A
公开(公告)日：2000-09-05
申请号：US152945
申请日：1998-09-14
申请人： Sang-yong Lee , Soo-seong Kim , Jun-soo Kim
发明人： Sang-yong Lee , Soo-seong Kim , Jun-soo Kim
IPC分类号： H01L29/73 , H01L21/266 , H01L21/331 , H01L29/08 , H01L29/732
CPC分类号： H01L29/66295 , H01L21/266 , H01L29/0804 , H01L29/732
摘要： A bipolar junction transistor includes a semiconductor substrate having a surface, a base region of first conductivity type in the substrate, and an emitter region of second conductivity type extending from the surface into the base region to form a generally concave semiconductor junction having an apex oriented towards the surface. The emitter region preferably includes a plurality of contiguous emitter subregions extending from the surface into the base region in an arcuate manner and merging to form the generally concave semiconductor junction. The transistor preferably includes an emitter terminal electrically contacting the emitter region at an emitter contact area on the surface, the emitter contact area having a central portion substantially centered with respect to the apex of the semiconductor junction. To produce the bipolar junction transistor, a base layer of first conductivity type is provided in a semiconductor substrate, ions of second conductivity type implanted through the base layer surface in portions of the base layer surface increasing in area from a central portion of the base layer surface laterally towards outer portions of the base layer surface, and the implanted ions diffused into the base layer to thereby create the emitter region and the concave semiconductor junction. Preferably, the ions are implanted by depositing an oxide or other masking layer on the base layer, selectively etching the masking layer to expose the plurality of surface portions, and then implanting the ions into the exposed surface portions.
摘要翻译：双极结晶体管包括具有表面的半导体衬底，衬底中的第一导电类型的基极区域和从表面延伸到基极区域的第二导电类型的发射极区域，以形成具有顶点取向的大致凹入的半导体结朝向表面。发射极区域优选地包括多个连续的发射极子区域，其以弓形方式从表面延伸到基极区域并且合并以形成大体上凹的半导体结。晶体管优选地包括在表面上的发射极接触区域处电接触发射极区域的发射极端子，发射极接触区域具有基本上相对于半导体结的顶点居中的中心部分。为了制造双极结型晶体管，在半导体衬底中设置第一导电型的基极层，从基底层表面的基底层表面的部分注入的基底层表面的部分的离子从基底层的中心部分增加的第二导电型离子表面横向朝向基底层表面的外部部分，并且注入的离子扩散到基底层中，从而产生发射极区域和凹入的半导体结。优选地，通过在基底层上沉积氧化物或其它掩蔽层来注入离子，选择性地蚀刻掩模层以暴露多个表面部分，然后将离子注入到暴露的表面部分中。

2. 发明授权

US5872391A Bipolar junction transistors having an increased safe operating area 失效
标题翻译：具有增加的安全操作区域的双极结晶体管
公开(公告)号：US5872391A
公开(公告)日：1999-02-16
申请号：US674092
申请日：1996-07-01
申请人： Sang-yong Lee , Soo-seong Kim , Jun-soo Kim
发明人： Sang-yong Lee , Soo-seong Kim , Jun-soo Kim
IPC分类号： H01L29/73 , H01L21/266 , H01L21/331 , H01L29/08 , H01L29/732 , H01L27/082 , H01L27/02 , H01L29/70
CPC分类号： H01L29/66295 , H01L21/266 , H01L29/0804 , H01L29/732
摘要： A bipolar junction transistor includes a semiconductor substrate having a surface, a base region of first conductivity type in the substrate, and an emitter region of second conductivity type extending from the surface into the base region to form a generally concave semiconductor junction having an apex oriented towards the surface. The emitter region preferably includes a plurality of contiguous emitter subregions extending from the surface into the base region in an arcuate manner and merging to form the generally concave semiconductor junction. The transistor preferably includes an emitter terminal electrically contacting the emitter region at an emitter contact area on the surface, the emitter contact area having a central portion substantially centered with respect to the apex of the semiconductor junction. To produce the bipolar junction transistor, a base layer of first conductivity type is provided in a semiconductor substrate, ions of second conductivity type implanted through the base layer surface in portions of the base layer surface increasing in area from a central portion of the base layer surface laterally towards outer portions of the base layer surface, and the implanted ions diffused into the base layer to thereby create the emitter region and the concave semiconductor junction. Preferably, the ions are implanted by depositing an oxide or other masking layer on the base layer, selectively etching the masking layer to expose the plurality of surface portions, and then implanting the ions into the exposed surface portions.
摘要翻译：双极结晶体管包括具有表面的半导体衬底，衬底中的第一导电类型的基极区域和从表面延伸到基极区域的第二导电类型的发射极区域，以形成具有顶点取向的大致凹入的半导体结朝向表面。发射极区域优选地包括多个连续的发射极子区域，其以弓形方式从表面延伸到基极区域并且合并以形成大体上凹的半导体结。晶体管优选地包括在表面上的发射极接触区域处电接触发射极区域的发射极端子，发射极接触区域具有基本上相对于半导体结的顶点居中的中心部分。为了制造双极结型晶体管，在半导体衬底中设置第一导电型的基极层，从基底层表面的基底层表面的部分注入的基底层表面的部分的离子从基底层的中心部分增加的第二导电型离子表面横向朝向基底层表面的外部部分，并且注入的离子扩散到基底层中，从而产生发射极区域和凹入的半导体结。优选地，通过在基底层上沉积氧化物或其它掩蔽层来注入离子，选择性地蚀刻掩模层以暴露多个表面部分，然后将离子注入到暴露的表面部分中。

3. 发明授权

US5893736A Methods of forming insulated gate semiconductor devices having spaced epitaxial JFET regions therein 失效
标题翻译：在其中形成具有间隔开的外延JFET区域的绝缘栅极半导体器件的方法
公开(公告)号：US5893736A
公开(公告)日：1999-04-13
申请号：US722839
申请日：1996-09-27
申请人： Sang-yong Lee , Soo-seong Kim
发明人： Sang-yong Lee , Soo-seong Kim
IPC分类号： H01L21/336 , H01L29/08 , H01L29/739 , H01L29/78 , H01L21/8236 , H01L21/28
CPC分类号： H01L29/66712 , H01L29/7395 , H01L29/7802 , H01L29/0847
摘要： An insulated gate semiconductor device includes a relatively highly doped epitaxial JFET region. The epitaxial JFET region forms a P-N junction with the base region of the device, but is spaced from the insulated gate electrode by a more lightly doped epitaxial accumulation region. The use of a spaced JFET region provides a number of important performance advantages over prior art power MOSFETs or IGBTs. By spacing the highly doped JFET region from the top face, the devices of the present invention are, among other things, capable of sustaining higher breakdown voltages without a significant increase in forward on-state resistance. For example, by using a more lightly doped accumulation region underneath the gate electrode, in place of a more highly doped JFET region, the punch-through voltage of the device is increased and electric field crowding at the base junction at the top of the face is decreased. In contrast to those JFET regions in the prior art which are formed by performing a high dose implant and/or high dose diffusion of first conductivity type dopants, the devices according to the present invention reduce the adverse influences on threshold voltage caused by high dose implants of ions adjacent the periphery of the base regions.
摘要翻译：绝缘栅半导体器件包括相对高掺杂的外延JFET区域。外延JFET区域与器件的基极区域形成P-N结，但是通过更轻掺杂的外延累积区域与绝缘栅电极间隔开。与现有技术的功率MOSFET或IGBT相比，使用间隔的JFET区域提供了许多重要的性能优点。通过将高掺杂JFET区域与顶面间隔开，除了别的以外，本发明的器件能够承受更高的击穿电压，而不会明显增加正向导通电阻。例如，通过在栅电极下方使用更轻掺杂的累积区，代替更高掺杂的JFET区，器件的穿通电压增加，并且在表面顶部的基极结处的电场拥挤减少。与通过执行第一导电类型掺杂剂的高剂量注入和/或高剂量扩散形成的现有技术中的那些JFET区域相反，根据本发明的器件减少了由高剂量植入物引起的对阈值电压的不利影响的邻近基底区域的周边的离子。

4. 发明授权

US06448588B2 Insulated gate bipolar transistor having high breakdown voltage in reverse blocking mode 有权
标题翻译：绝缘栅双极晶体管在反向阻断模式下具有高击穿电压
公开(公告)号：US06448588B2
公开(公告)日：2002-09-10
申请号：US09790816
申请日：2001-02-23
申请人： Chong Man Yun , Soo-seong Kim , Young-dae Kwon
发明人： Chong Man Yun , Soo-seong Kim , Young-dae Kwon
IPC分类号： H01L2974
CPC分类号： H01L29/66333 , H01L29/1095 , H01L29/7395
摘要： An insulated gate bipolar transistor having a high breakdown voltage in a reverse blocking mode and a method for fabricating the same are provided. The insulated gate bipolar transistor includes a relatively low-concentration lower buffer layer and a relatively high-concentration upper buffer layer. The low-concentration lower buffer layer contacts a semiconductor substrate having a high concentration of first conductivity type impurities used as a collector region, and the high-concentration upper buffer layer contacts a drift region of a second conductivity type. The conductivity type of the upper buffer layer is second conductivity type impurities, and the conductivity type of the lower buffer layer is substantially intrinsic, or first conductivity type impurities, or second conductivity type impurities. According to the present invention, due to the high-concentration upper buffer layer, the thickness of the drift region can be reduced, and during a forward continuity, a switching speed can be improved. Simultaneously, due the low-concentration lower buffer layer, the breakdown voltage of a device can be increased in a reverse blocking mode.
摘要翻译：提供了具有反向阻断模式的高击穿电压的绝缘栅双极晶体管及其制造方法。绝缘栅双极晶体管包括相对低浓度的下缓冲层和相对高浓度的上缓冲层。低浓度下缓冲层接触具有用作集电极区的高浓度第一导电型杂质的半导体衬底，并且高浓度上缓冲层接触第二导电类型的漂移区。上缓冲层的导电类型是第二导电型杂质，下缓冲层的导电类型基本上是本征的，或者是第一导电型杂质或第二导电型杂质。根据本发明，由于高浓度上缓冲层，可以减小漂移区的厚度，并且在正向连续性期间，可以提高切换速度。同时，由于低浓度下缓冲层，器件的击穿电压可以以反向阻断模式增加。

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