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1. 发明申请

US20080138960A1 METHOD OF MANUFACTURING A STACK-TYPE SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造堆叠型半导体器件的方法
公开(公告)号：US20080138960A1
公开(公告)日：2008-06-12
申请号：US11936965
申请日：2007-11-08
申请人： Sang-Yeob Han , Chang-Ki Hong , Bo-Un Yoon , Young-Ho Koh , Seong-Kyu Yun , Jong-Heun Lim
发明人： Sang-Yeob Han , Chang-Ki Hong , Bo-Un Yoon , Young-Ho Koh , Seong-Kyu Yun , Jong-Heun Lim
IPC分类号： H01L21/30
CPC分类号： H01L21/76254 , H01L21/3212 , H01L21/32139
摘要： A method of manufacturing a stack-type semiconductor device, in which a first substrate and a second substrate are prepared so that the first substrate has a surface layer and the second substrate has an insulation layer. The first substrate and the second substrate are attached to each other to allow the surface layer to make contact with the insulation layer. The first substrate is partially separated from the second substrate to allow the surface layer to remain on a central portion of the second substrate. A sacrificial layer pattern is then formed on an edge portion of the second substrate having the surface layer. The sacrificial layer pattern and the surface layer are planarized. Thus, the sacrificial layer pattern may reduce damage to the edge portion of the second substrate so that the second substrate may have an improved flatness.
摘要翻译：制造堆叠型半导体器件的方法，其中制备第一衬底和第二衬底，使得第一衬底具有表面层，并且第二衬底具有绝缘层。第一基板和第二基板彼此附接以允许表面层与绝缘层接触。第一衬底与第二衬底部分地分离以允许表面层保留在第二衬底的中心部分上。然后在具有表面层的第二基板的边缘部分上形成牺牲层图案。牺牲层图案和表面层被平坦化。因此，牺牲层图案可以减小对第二基板的边缘部分的损伤，使得第二基板可以具有改善的平坦度。

2. 发明授权

US07678625B2 Methods of fabricating semiconductor devices including channel layers having improved defect density and surface roughness characteristics 有权
标题翻译：制造半导体器件的方法包括具有改进的缺陷密度和表面粗糙度特性的沟道层
公开(公告)号：US07678625B2
公开(公告)日：2010-03-16
申请号：US11962742
申请日：2007-12-21
申请人： Jong-Heun Lim , Chang-Ki Hong , Bo-Un Yoon , Seong-Kyu Yun , Suk-Hun Choi , Sang-Yeob Han
发明人： Jong-Heun Lim , Chang-Ki Hong , Bo-Un Yoon , Seong-Kyu Yun , Suk-Hun Choi , Sang-Yeob Han
IPC分类号： H01L21/84
CPC分类号： H01L21/02675 , H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L29/78
摘要： A method of fabricating a semiconductor device including a channel layer includes forming a single crystalline semiconductor layer on a semiconductor substrate. The single crystalline semiconductor layer includes a protrusion extending from a surface thereof. A first polishing process is performed on the single crystalline semiconductor layer to remove a portion of the protrusion such that the single crystalline semiconductor layer includes a remaining portion of the protrusion. A second polishing process different from the first polishing process is performed to remove the remaining portion of the protrusion and define a substantially planar single crystalline semiconductor layer having a substantially uniform thickness. A sacrificial layer may be formed on the single crystalline semiconductor layer and used as a polish stop for the first polishing process to define a sacrificial layer pattern, which may be removed prior to the second polishing process. Related methods of fabricating stacked semiconductor memory devices are also discussed.
摘要翻译：制造包括沟道层的半导体器件的方法包括在半导体衬底上形成单晶半导体层。单晶半导体层包括从其表面延伸的突起。在单晶半导体层上执行第一抛光工艺以去除突起的一部分，使得单晶半导体层包括突起的剩余部分。执行与第一抛光工艺不同的第二抛光工艺以去除突起的剩余部分并限定具有基本上均匀厚度的基本上平面的单晶半导体层。可以在单晶半导体层上形成牺牲层，并且用作第一抛光工艺的抛光止挡件以限定可在第二抛光工艺之前去除的牺牲层图案。还讨论了制造叠层半导体存储器件的相关方法。

3. 发明授权

US08008172B2 Methods of forming semiconductor devices including multistage planarization and crystalization of a semiconductor layer 有权
标题翻译：形成半导体器件的方法包括半平面化和半导体层的结晶化
公开(公告)号：US08008172B2
公开(公告)日：2011-08-30
申请号：US12070220
申请日：2008-02-15
申请人： Jong-Heun Lim , Chang-Ki Hong , Bo-Un Yoon , Seong-Kyu Yun , Suk-Hun Choi , Sang-Yeob Han
发明人： Jong-Heun Lim , Chang-Ki Hong , Bo-Un Yoon , Seong-Kyu Yun , Suk-Hun Choi , Sang-Yeob Han
IPC分类号： H01L21/20 , H01L21/36 , H01L21/76 , H01L21/302 , H01L21/461
CPC分类号： H01L21/76229 , H01L21/3212
摘要： A method of forming a semiconductor device includes: forming a pattern having trenches on a semiconductor substrate; forming a semiconductor layer on the semiconductor device that fills the trenches; planarizing the semiconductor layer using a first planarization process without exposing the pattern; performing an epitaxy growth process on the first planarized semiconductor layer to form a crystalline semiconductor layer; and planarizing the crystalline semiconductor layer until the pattern is exposed to form a crystalline semiconductor pattern.
摘要翻译：一种形成半导体器件的方法包括：在半导体衬底上形成具有沟槽的图案; 在所述半导体器件上形成填充所述沟槽的半导体层; 使用第一平坦化工艺平坦化半导体层而不暴露图案; 在所述第一平坦化半导体层上进行外延生长工艺以形成晶体半导体层; 并且平坦化晶体半导体层直到图案被曝光以形成晶体半导体图案。

4. 发明申请

US20080200007A1 Methods of forming semiconductor devices 有权
标题翻译：形成半导体器件的方法
公开(公告)号：US20080200007A1
公开(公告)日：2008-08-21
申请号：US12070220
申请日：2008-02-15
申请人： Jong-Heun Lim , Chang-Ki Hong , Bo-Un Yoon , Seong-Kyu Yun , Suk-Hun Choi , Sang-Yeob Han
发明人： Jong-Heun Lim , Chang-Ki Hong , Bo-Un Yoon , Seong-Kyu Yun , Suk-Hun Choi , Sang-Yeob Han
IPC分类号： H01L21/762
CPC分类号： H01L21/76229 , H01L21/3212
摘要： A method of forming a semiconductor device includes: forming a pattern having trenches on a semiconductor substrate; forming a semiconductor layer on the semiconductor device that fills the trenches; planarizing the semiconductor layer using a first planarization process without exposing the pattern; performing an epitaxy growth process on the first planarized semiconductor layer to form a crystalline semiconductor layer; and planarizing the crystalline semiconductor layer until the pattern is exposed to form a crystalline semiconductor pattern.
摘要翻译：一种形成半导体器件的方法包括：在半导体衬底上形成具有沟槽的图案; 在所述半导体器件上形成填充所述沟槽的半导体层; 使用第一平坦化工艺平坦化半导体层而不暴露图案; 在所述第一平坦化半导体层上进行外延生长工艺以形成晶体半导体层; 并且平坦化晶体半导体层直到图案被曝光以形成晶体半导体图案。

5. 发明授权

US07932163B2 Methods of forming stacked semiconductor devices with single-crystal semiconductor regions 有权
标题翻译：用单晶半导体区形成叠层半导体器件的方法
公开(公告)号：US07932163B2
公开(公告)日：2011-04-26
申请号：US12029572
申请日：2008-02-12
申请人： Jong-Heun Lim , Chang-Ki Hong , Bo-Un Yoon , Dae-Lok Bae , Seong-Kyu Yun , Suk-Hun Choi
发明人： Jong-Heun Lim , Chang-Ki Hong , Bo-Un Yoon , Dae-Lok Bae , Seong-Kyu Yun , Suk-Hun Choi
IPC分类号： H01L21/30 , H01L21/46
CPC分类号： H01L27/0688 , H01L21/2007 , H01L21/8221
摘要： Spaced apart bonding surfaces are formed on a first substrate. A second substrate is bonded to the bonding surfaces of the first substrate and cleaved to leave respective semiconductor regions from the second substrate on respective ones of the spaced apart bonding surfaces of the first substrate. The bonding surfaces may include surfaces of at least one insulating region on the first substrate, and at least one active device may be formed in and/or on at least one of the semiconductor regions. A device isolation region may be formed adjacent the at least one of the semiconductor regions.
摘要翻译：间隔开的接合表面形成在第一基底上。第二衬底被结合到第一衬底的接合表面并且被切割以在第一衬底的相应的间隔的结合表面上的第二衬底上留下相应的半导体区域。接合表面可以包括第一衬底上的至少一个绝缘区域的表面，并且至少一个有源器件可以形成在半导体区域中的至少一个中和/或至少一个半导体区域中。器件隔离区域可以形成为与半导体区域中的至少一个相邻。

6. 发明申请

US20080200009A1 Methods of Forming Stacked Semiconductor Devices with Single-Crystal Semiconductor Regions 有权
标题翻译：用单晶半导体区形成叠层半导体器件的方法
公开(公告)号：US20080200009A1
公开(公告)日：2008-08-21
申请号：US12029572
申请日：2008-02-12
申请人： Jong-Heun Lim , Chang-Ki Hong , Bo-Un Yoon , Dae-Lok Bae , Seong-Kyu Yun , Suk-Hun Choi
发明人： Jong-Heun Lim , Chang-Ki Hong , Bo-Un Yoon , Dae-Lok Bae , Seong-Kyu Yun , Suk-Hun Choi
IPC分类号： H01L21/46
CPC分类号： H01L27/0688 , H01L21/2007 , H01L21/8221
摘要： Spaced apart bonding surfaces are formed on a first substrate. A second substrate is bonded to the bonding surfaces of the first substrate and cleaved to leave respective semiconductor regions from the second substrate on respective ones of the spaced apart bonding surfaces of the first substrate. The bonding surfaces may include surfaces of at least one insulating region on the first substrate, and at least one active device may be formed in and/or on at least one of the semiconductor regions. A device isolation region may be formed adjacent the at least one of the semiconductor regions.
摘要翻译：间隔开的接合表面形成在第一基底上。第二衬底被结合到第一衬底的接合表面并且被切割以在第一衬底的相应的间隔的结合表面上的第二衬底上留下相应的半导体区域。接合表面可以包括第一衬底上的至少一个绝缘区域的表面，并且至少一个有源器件可以形成在半导体区域中的至少一个中和/或至少一个半导体区域中。器件隔离区域可以形成为与半导体区域中的至少一个相邻。

7. 发明申请

US20080247219A1 Resistive Random Access Memory Devices Including Sidewall Resistive Layers and Related Methods 审中-公开
标题翻译：包括侧壁电阻层的电阻随机存取存储器件及相关方法
公开(公告)号：US20080247219A1
公开(公告)日：2008-10-09
申请号：US12062042
申请日：2008-04-03
申请人： Suk-Hun Choi , In-Gyu Baek , Seong-Kyu Yun , Jong-Heun Lim , Chagn-Ki Hong , Bo-Un Yoon
发明人： Suk-Hun Choi , In-Gyu Baek , Seong-Kyu Yun , Jong-Heun Lim , Chagn-Ki Hong , Bo-Un Yoon
IPC分类号： G11C11/00 , H01C17/00
CPC分类号： H01L45/04 , H01C17/06533 , H01L27/2409 , H01L27/2472 , H01L45/1233 , H01L45/146 , H01L45/1666 , Y10T29/49082
摘要： A resistive random access memory (RRAM) device may include a first metal pattern on a substrate, a first insulating layer on the first metal pattern and on the substrate, an electrode, a second insulating layer on the first insulating layer, a resistive memory layer, and a second metal pattern. Portions of the first metal pattern may be between the substrate and the first insulating layer, and the first insulating layer may have a first opening therein exposing a portion of the first metal pattern. The electrode may be in the opening with the electrode being electrically coupled with the exposed portion of the first metal pattern. The first insulating layer may be between the second insulating layer and the substrate, and the second insulating layer may have a second opening therein exposing a portion of the electrode. The resistive memory layer may be on side faces of the second opening and on portions of the electrode, and the second metal pattern may be in the second opening with the resistive memory layer between the second metal pattern and the side faces of the second opening and between the second metal pattern and the electrode. Related methods are also discussed.
摘要翻译：电阻随机存取存储器（RRAM）器件可以包括衬底上的第一金属图案，第一金属图案上的第一绝缘层和衬底上的第一绝缘层，电极，第一绝缘层上的第二绝缘层，电阻存储层，和第二金属图案。第一金属图案的部分可以在基板和第一绝缘层之间，并且第一绝缘层可以具有其中暴露第一金属图案的一部分的第一开口。电极可以在开口中，其中电极与第一金属图案的暴露部分电耦合。第一绝缘层可以在第二绝缘层和衬底之间，并且第二绝缘层可以具有暴露电极的一部分的第二开口。电阻性存储层可以在第二开口的侧面和电极的部分上，并且第二金属图案可以在第二开口中，第二金属图案和第二开口的侧面之间的电阻性存储层，在第二金属图案和电极之间。还讨论了相关方法。

8. 发明申请

US20090098804A1 Apparatus for polishing a wafer and method for detecting a polishing end point by the same 有权
标题翻译：用于抛光晶片的装置和用于检测抛光终点的方法
公开(公告)号：US20090098804A1
公开(公告)日：2009-04-16
申请号：US12285852
申请日：2008-10-15
申请人： Jong-Heun Lim , Sung-Ho Shin , Bo-Un Yoon , Chang-Ki Hong
发明人： Jong-Heun Lim , Sung-Ho Shin , Bo-Un Yoon , Chang-Ki Hong
IPC分类号： B24B49/12 , B24B9/00 , B24B21/02
CPC分类号： B24B9/065 , B24B21/02 , B24B37/013 , B24B49/12
摘要： A wafer polishing apparatus includes a polishing tape extending between two guide rollers, a first surface of the polishing tape contacting a surface of a wafer to be polished, a polishing head including a pusher pad, the pusher pad adapted to push the polishing tape against the surface of the wafer to be polished, a color image sensor adjacent to the polishing tape, the color image sensor being adapted to detect a color image of the polishing tape and to output a signal corresponding to the detected color image, and a controller connected to the color image sensor, the controller being adapted to receive the signal output from the color image sensor and to determine when a color of the color image detected by the color image sensor changes, a change in the color image indicating a polishing end point.
摘要翻译：晶片抛光装置包括在两个导辊之间延伸的研磨带，抛光带的与待抛光晶片的表面接触的第一表面，包括推动垫的抛光头，该推动垫适于将抛光带推向要抛光的晶片的表面，邻近抛光带的彩色图像传感器，彩色图像传感器适于检测研磨带的彩色图像并输出与检测到的彩色图像相对应的信号，以及控制器，连接到所述彩色图像传感器，所述控制器适于接收从彩色图像传感器输出的信号，并且确定由彩色图像传感器检测到的彩色图像的颜色何时改变指示抛光终点的彩色图像的变化。

9. 发明授权

US08038508B2 Apparatus for polishing a wafer and method for detecting a polishing end point by the same 有权
标题翻译：用于抛光晶片的装置和用于检测抛光终点的方法
公开(公告)号：US08038508B2
公开(公告)日：2011-10-18
申请号：US12285852
申请日：2008-10-15
申请人： Jong-Heun Lim , Sung-Ho Shin , Bo-Un Yoon , Chang-Ki Hong
发明人： Jong-Heun Lim , Sung-Ho Shin , Bo-Un Yoon , Chang-Ki Hong
IPC分类号： B24B49/00
CPC分类号： B24B9/065 , B24B21/02 , B24B37/013 , B24B49/12
摘要： A wafer polishing apparatus includes a polishing tape extending between two guide rollers, a first surface of the polishing tape contacting a surface of a wafer to be polished, a polishing head including a pusher pad, the pusher pad adapted to push the polishing tape against the surface of the wafer to be polished, a color image sensor adjacent to the polishing tape, the color image sensor being adapted to detect a color image of the polishing tape and to output a signal corresponding to the detected color image, and a controller connected to the color image sensor, the controller being adapted to receive the signal output from the color image sensor and to determine when a color of the color image detected by the color image sensor changes, a change in the color image indicating a polishing end point.
摘要翻译：晶片抛光装置包括在两个导辊之间延伸的研磨带，抛光带的与待抛光晶片的表面接触的第一表面，包括推动垫的抛光头，该推动垫适于将抛光带推向要抛光的晶片的表面，邻近抛光带的彩色图像传感器，彩色图像传感器适于检测研磨带的彩色图像并输出与检测到的彩色图像相对应的信号，以及控制器，连接到所述彩色图像传感器，所述控制器适于接收从彩色图像传感器输出的信号，并且确定由彩色图像传感器检测到的彩色图像的颜色何时改变指示抛光终点的彩色图像的变化。

10. 发明申请

US20080164503A1 Ferroelectric Memory Devices Having a Protruding Bottom Electrode and Methods of Forming the Same 审中-公开
标题翻译：具有突起底电极的铁电存储器件及其形成方法
公开(公告)号：US20080164503A1
公开(公告)日：2008-07-10
申请号：US11970770
申请日：2008-01-08
申请人： Suk-Hun Choi , Chang-Ki Hong , Jung-Hyeon Kim , Jun-Young Lee , Jong-Heun Lim , Seong-Kyu Yun
发明人： Suk-Hun Choi , Chang-Ki Hong , Jung-Hyeon Kim , Jun-Young Lee , Jong-Heun Lim , Seong-Kyu Yun
IPC分类号： G11C11/22 , H01L29/78 , H01L21/02
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/82
摘要： A ferroelectric memory device and methods of forming the same are provided. Forming a ferroelectric device includes forming an insulation layer over a substrate having a conductive region, forming a bottom electrode electrically connected to the conductive region in the insulation layer, recessing the insulation layer, and forming a ferroelectric layer and an upper electrode layer covering the bottom electrode over the recessed insulation layer, The bottom electrode protrudes over an upper surface of the recessed insulation layer.
摘要翻译：提供了铁电存储器件及其形成方法。形成铁电体器件包括在具有导电区域的衬底上形成绝缘层，形成与绝缘层中的导电区域电连接的底部电极，使绝缘层凹陷，并形成覆盖底部的铁电层和上电极层电极在凹陷绝缘层上方，底部电极突出在凹陷绝缘层的上表面上。

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