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1. 发明申请

US20070053228A1 Flash memory device and voltage generating circuit for the same 有权
标题翻译：闪存器件和电压发生电路相同
公开(公告)号：US20070053228A1
公开(公告)日：2007-03-08
申请号：US11482447
申请日：2006-07-07
申请人： Sang-Wan Nam , Dae-Han Kim
发明人： Sang-Wan Nam , Dae-Han Kim
IPC分类号： G11C5/14
CPC分类号： G11C8/08 , G11C16/08 , G11C16/12
摘要： A flash memory device and a voltage generating circuit for the same. The flash memory includes a memory cell array configured with a plurality of memory cells, a voltage generating circuit for generating a plurality of constant voltages to be applied to the memory cell array, and a selection circuit for selecting one constant voltage among the plurality of the constant voltages and applying the selected one constant voltage to the memory cell array. The voltage generating circuit discharges a leakage current input by the selection circuit through a voltage division path, which generates the constant voltages.
摘要翻译：一种闪存器件及其电压产生电路。闪存包括配置有多个存储单元的存储单元阵列，用于产生施加到存储单元阵列的多个恒定电压的电压产生电路，以及用于选择多个存储单元中的一个恒定电压的选择电路将所选择的一个恒定电压施加到存储单元阵列。电压产生电路通过分压路径对由选择电路输入的漏电流进行放电，产生恒定电压。

2. 发明授权

US07372747B2 Flash memory device and voltage generating circuit for the same 有权
标题翻译：闪存器件和电压发生电路相同
公开(公告)号：US07372747B2
公开(公告)日：2008-05-13
申请号：US11482447
申请日：2006-07-07
申请人： Sang-Wan Nam , Dae-Han Kim
发明人： Sang-Wan Nam , Dae-Han Kim
IPC分类号： G11C5/14
CPC分类号： G11C8/08 , G11C16/08 , G11C16/12
摘要： A flash memory device and a voltage generating circuit for the same. The flash memory includes a memory cell array configured with a plurality of memory cells, a voltage generating circuit for generating a plurality of constant voltages to be applied to the memory cell array, and a selection circuit for selecting one constant voltage among the plurality of the constant voltages and applying the selected one constant voltage to the memory cell array. The voltage generating circuit discharges a leakage current input by the selection circuit through a voltage division path, which generates the constant voltages.
摘要翻译：一种闪存器件及其电压产生电路。闪存包括配置有多个存储单元的存储单元阵列，用于产生施加到存储单元阵列的多个恒定电压的电压产生电路，以及用于选择多个存储单元中的一个恒定电压的选择电路将所选择的一个恒定电压施加到存储单元阵列。电压产生电路通过分压路径对由选择电路输入的漏电流进行放电，产生恒定电压。

3. 发明申请

US20070201277A1 NOR flash memory device with a serial sensing operation and method of sensing data bits in a NOR flash memory device 审中-公开
公开(公告)号：US20070201277A1
公开(公告)日：2007-08-30
申请号：US11789624
申请日：2007-04-25
申请人： Sang-Wan Nam , Young-Ho Lim , Dae-Han Kim
发明人： Sang-Wan Nam , Young-Ho Lim , Dae-Han Kim
IPC分类号： G11C16/04 , G11C16/06 , G11C11/34
CPC分类号： G11C16/26
摘要： In a NOR flash memory device with a serial sensing operation, and method of sensing data bits in a NOR flash memory device, the device includes a multilevel cell, a sense amplifying circuit, a data buffer, a data latch circuit, and a control logic circuit. The sense amplifying circuit serially detects plural data bits stored in the multilevel cell. The data buffer is provided to buffer the data bit detected by the sense amplifier. The data latch circuit stores an output value of the data buffer for a time. The control logic circuit regulates the sense amplifying circuit to detect a lower data bit stored in the multilevel cell in response to a higher data bit held in the data latch. Here, the control logic circuit initializes an output terminal of the data buffer before or while sensing each of the plural data bits by the sense amplifier. According to the invention, a stabilized serial sensing operation can be conducted because the data line is conditioned to a uniform charge level regardless of the level of the data bit previously sensed.

4. 发明申请

US20060215449A1 NOR flash memory device with a serial sensing operation and method of sensing data bits in a NOR flash memory device 失效
标题翻译：具有串行感测操作的NOR闪存器件和用于检测NOR闪存器件中的数据位的方法
公开(公告)号：US20060215449A1
公开(公告)日：2006-09-28
申请号：US11263716
申请日：2005-11-01
申请人： Sang-Wan Nam , Young-Ho Lim , Dae-Han Kim
发明人： Sang-Wan Nam , Young-Ho Lim , Dae-Han Kim
IPC分类号： G11C16/04
CPC分类号： G11C16/26
摘要： In a NOR flash memory device with a serial sensing operation, and method of sensing data bits in a NOR flash memory device, the device includes a multilevel cell, a sense amplifying circuit, a data buffer, a data latch circuit, and a control logic circuit. The sense amplifying circuit serially detects plural data bits stored in the multilevel cell. The data buffer is provided to buffer the data bit detected by the sense amplifier. The data latch circuit stores an output value of the data buffer for a time. The control logic circuit regulates the sense amplifying circuit to detect a lower data bit stored in the multilevel cell in response to a higher data bit held in the data latch. Here, the control logic circuit initializes an output terminal of the data buffer before or while sensing each of the plural data bits by the sense amplifier. According to the invention, a stabilized serial sensing operation can be conducted because the data line is conditioned to a uniform charge level regardless of the level of the data bit previously sensed.
摘要翻译：在具有串行感测操作的NOR闪存器件中，以及在NOR闪存器件中检测数据位的方法，该器件包括多电平单元，读出放大电路，数据缓冲器，数据锁存电路和控制逻辑电路。感测放大电路串行地检测存储在多电平单元中的多个数据位。提供数据缓冲器以缓冲由读出放大器检测到的数据位。数据锁存电路一次存储数据缓冲器的输出值。控制逻辑电路调节感测放大电路，以响应于数据锁存器中保持的较高数据位来检测存储在多电平单元中的较低数据位。这里，控制逻辑电路在感测放大器感测每个多个数据位之前或期间初始化数据缓冲器的输出端。根据本发明，可以进行稳定的串行感测操作，因为无论前面感测到的数据位的电平如何，数据线被调节到均匀的电荷电平。

5. 发明授权

US07885118B2 Flash memory device and voltage generating circuit for the same 失效
标题翻译：闪存器件和电压发生电路相同
公开(公告)号：US07885118B2
公开(公告)日：2011-02-08
申请号：US12401784
申请日：2009-03-11
申请人： Sang-Wan Nam , Dae-Han Kim
发明人： Sang-Wan Nam , Dae-Han Kim
IPC分类号： G11C11/34
CPC分类号： G11C16/30 , G11C5/145
摘要： Disclosed is a flash memory device which includes a memory core, a high voltage generating circuit and a reference voltage generating circuit. The high voltage generating circuit is configured to generate a high voltage to be supplied to the memory core. The reference voltage generating circuit is configured to generate at least one reference voltage to be supplied to the high voltage generating circuit. The reference voltage generating circuit includes a first reference voltage generator configured to generate a first reference voltage in response to a supply voltage, and a second reference voltage generator configured to generate a second reference voltage in response to the first reference voltage. The at least one reference voltage supplied to the high voltage generating circuit includes the second reference voltage.
摘要翻译：公开了一种闪速存储器件，其包括存储器芯，高电压产生电路和参考电压产生电路。高电压产生电路被配置为产生要提供给存储器芯的高电压。参考电压产生电路被配置为产生要提供给高电压发生电路的至少一个参考电压。参考电压产生电路包括被配置为响应于电源电压产生第一参考电压的第一参考电压发生器和被配置为响应于第一参考电压产生第二参考电压的第二参考电压发生器。提供给高电压产生电路的至少一个参考电压包括第二参考电压。

6. 发明授权

US07773419B2 NOR flash memory device with a serial sensing operation and method of sensing data bits in a NOR flash memory device 有权
标题翻译：具有串行感测操作的NOR闪存器件和用于检测NOR闪存器件中的数据位的方法
公开(公告)号：US07773419B2
公开(公告)日：2010-08-10
申请号：US12366266
申请日：2009-02-05
申请人： Sang-Wan Nam , Young-Ho Lim , Dae-Han Kim
发明人： Sang-Wan Nam , Young-Ho Lim , Dae-Han Kim
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/26
摘要： In a NOR flash memory device with a serial sensing operation, and method of sensing data bits in a NOR flash memory device, the device includes a multilevel cell, a sense amplifying circuit, a data buffer, a data latch circuit, and a control logic circuit. The sense amplifying circuit serially detects plural data bits stored in the multilevel cell. The data buffer is provided to buffer the data bit detected by the sense amplifier. The data latch circuit stores an output value of the data buffer for a time. The control logic circuit regulates the sense amplifying circuit to detect a lower data bit stored in the multilevel cell in response to a higher data bit held in the data latch. Here, the control logic circuit initializes an output terminal of the data buffer before or while sensing each of the plural data bits by the sense amplifier. According to the invention, a stabilized serial sensing operation can be conducted because the data line is conditioned to a uniform charge level regardless of the level of the data bit previously sensed.
摘要翻译：在具有串行感测操作的NOR闪存器件中，以及在NOR闪存器件中检测数据位的方法，该器件包括多电平单元，读出放大电路，数据缓冲器，数据锁存电路和控制逻辑电路。感测放大电路串行地检测存储在多电平单元中的多个数据位。提供数据缓冲器以缓冲由读出放大器检测到的数据位。数据锁存电路一次存储数据缓冲器的输出值。控制逻辑电路调节感测放大电路，以响应于数据锁存器中保持的较高数据位来检测存储在多电平单元中的较低数据位。这里，控制逻辑电路在感测放大器感测每个多个数据位之前或期间初始化数据缓冲器的输出端。根据本发明，可以进行稳定的串行感测操作，因为无论前面感测到的数据位的电平如何，数据线被调节到均匀的电荷电平。

7. 发明申请

US20090147575A1 NOR FLASH MEMORY DEVICE WITH A SERIAL SENSING OPERATION AND METHOD OF SENSING DATA BITS IN A NOR FLASH MEMORY DEVICE 有权
标题翻译：具有串行感测操作的NOR闪存存储器件和在NOR闪存存储器件中感测数据位的方法
公开(公告)号：US20090147575A1
公开(公告)日：2009-06-11
申请号：US12366266
申请日：2009-02-05
申请人： Sang-Wan Nam , Young-Ho Lim , Dae-Han Kim
发明人： Sang-Wan Nam , Young-Ho Lim , Dae-Han Kim
IPC分类号： G11C16/00 , G11C16/06 , G11C7/00
CPC分类号： G11C16/26
摘要： In a NOR flash memory device with a serial sensing operation, and method of sensing data bits in a NOR flash memory device, the device includes a multilevel cell, a sense amplifying circuit, a data buffer, a data latch circuit, and a control logic circuit. The sense amplifying circuit serially detects plural data bits stored in the multilevel cell. The data buffer is provided to buffer the data bit detected by the sense amplifier. The data latch circuit stores an output value of the data buffer for a time. The control logic circuit regulates the sense amplifying circuit to detect a lower data bit stored in the multilevel cell in response to a higher data bit held in the data latch. Here, the control logic circuit initializes an output terminal of the data buffer before or while sensing each of the plural data bits by the sense amplifier. According to the invention, a stabilized serial sensing operation can be conducted because the data line is conditioned to a uniform charge level regardless of the level of the data bit previously sensed.
摘要翻译：在具有串行感测操作的NOR闪存器件以及NOR闪存器件中的数据位检测方法中，器件包括多电平单元，读出放大电路，数据缓冲器，数据锁存电路和控制逻辑电路。感测放大电路串行地检测存储在多电平单元中的多个数据位。提供数据缓冲器以缓冲由读出放大器检测到的数据位。数据锁存电路一次存储数据缓冲器的输出值。控制逻辑电路调节感测放大电路，以响应于数据锁存器中保持的较高数据位来检测存储在多电平单元中的较低数据位。这里，控制逻辑电路在感测放大器感测每个多个数据位之前或期间初始化数据缓冲器的输出端。根据本发明，可以进行稳定的串行感测操作，因为无论前面感测到的数据位的电平如何，数据线被调节到均匀的电荷电平。

8. 发明授权

US07227790B2 NOR flash memory device with a serial sensing operation and method of sensing data bits in a NOR flash memory device 失效
标题翻译：具有串行感测操作的NOR闪存器件和用于检测NOR闪存器件中的数据位的方法
公开(公告)号：US07227790B2
公开(公告)日：2007-06-05
申请号：US11263716
申请日：2005-11-01
申请人： Sang-Wan Nam , Young-Ho Lim , Dae-Han Kim
发明人： Sang-Wan Nam , Young-Ho Lim , Dae-Han Kim
IPC分类号： G11C7/06
CPC分类号： G11C16/26
摘要： In a NOR flash memory device with a serial sensing operation, and method of sensing data bits in a NOR flash memory device, the device includes a multilevel cell, a sense amplifying circuit, a data buffer, a data latch circuit, and a control logic circuit. The sense amplifying circuit serially detects plural data bits stored in the multilevel cell. The data buffer is provided to buffer the data bit detected by the sense amplifier. The data latch circuit stores an output value of the data buffer for a time. The control logic circuit regulates the sense amplifying circuit to detect a lower data bit stored in the multilevel cell in response to a higher data bit held in the data latch. Here, the control logic circuit initializes an output terminal of the data buffer before or while sensing each of the plural data bits by the sense amplifier. According to the invention, a stabilized serial sensing operation can be conducted because the data line is conditioned to a uniform charge level regardless of the level of the data bit previously sensed.
摘要翻译：在具有串行感测操作的NOR闪存器件中，以及在NOR闪存器件中检测数据位的方法，该器件包括多电平单元，读出放大电路，数据缓冲器，数据锁存电路和控制逻辑电路。感测放大电路串行地检测存储在多电平单元中的多个数据位。提供数据缓冲器以缓冲由读出放大器检测到的数据位。数据锁存电路一次存储数据缓冲器的输出值。控制逻辑电路调节感测放大电路，以响应于数据锁存器中保持的较高数据位来检测存储在多电平单元中的较低数据位。这里，控制逻辑电路在感测放大器感测每个多个数据位之前或期间初始化数据缓冲器的输出端。根据本发明，可以进行稳定的串行感测操作，因为无论前面感测到的数据位的电平如何，数据线被调节到均匀的电荷电平。

9. 发明授权

US09812206B2 3D flash memory device having different dummy word lines and data storage devices including same 有权
公开(公告)号：US09812206B2
公开(公告)日：2017-11-07
申请号：US14162905
申请日：2014-01-24
申请人： Sang-Wan Nam , Kitae Park
发明人： Sang-Wan Nam , Kitae Park
IPC分类号： G11C11/34 , G11C16/04 , G11C16/16 , G11C16/34 , G11C16/08 , G11C16/10
CPC分类号： G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/3427
摘要： A three-dimensional (3D) flash memory includes a first dummy word line disposed between a ground select line and a lowermost main word line, and a second dummy word line of different word line configuration disposed between a string select line and an upper most main word line.

10. 发明授权

US09659662B2 Nonvolatile memory device and method of erasing nonvolatile memory device 有权
公开(公告)号：US09659662B2
公开(公告)日：2017-05-23
申请号：US14501352
申请日：2014-09-30
申请人： Sang-Wan Nam , Kang-Bin Lee , Kihwan Choi
发明人： Sang-Wan Nam , Kang-Bin Lee , Kihwan Choi
IPC分类号： G11C16/16 , G11C16/04
CPC分类号： G11C16/16 , G11C11/16 , G11C16/0483
摘要： A method is provided for erasing a nonvolatile memory device, including multiple memory blocks formed in a direction perpendicular to a substrate, each memory block having multiple strings connected to a bit line. The method includes selecting a memory block to be erased using a power supply voltage; unselecting a remaining memory block, other than the selected memory block, using a negative voltage; setting a bias condition to reduce leakage currents of the unselected memory block; and performing an erase operation on the selected memory block.

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