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1. 发明申请

US20120052682A1 POLISHING SLURRY AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME 审中-公开
标题翻译：抛光浆和使用其制造半导体器件的方法
公开(公告)号：US20120052682A1
公开(公告)日：2012-03-01
申请号：US13204862
申请日：2011-08-08
申请人： Sang-Kyun Kim , Jong-Won Lee , Eui-Hoon Jung , Bo-Un Yoon , Sang-Hyun Park , Seung-Jae Lee , Yun-Jeong Kim
发明人： Sang-Kyun Kim , Jong-Won Lee , Eui-Hoon Jung , Bo-Un Yoon , Sang-Hyun Park , Seung-Jae Lee , Yun-Jeong Kim
IPC分类号： H01L21/302 , C09K13/00
CPC分类号： H01L21/3212 , C09G1/02 , C09K3/1409 , C09K3/1463
摘要： A polishing slurry for polishing an aluminum film includes an abrasive agent, an oxidizing agent, an anti-corrosion agent, and a removal rate reducing agent that is an anionic compound exhibiting a negative charge in the slurry. The polishing slurry can be used in a method of manufacturing a semiconductor device.
摘要翻译：用于抛光铝膜的抛光浆料包括研磨剂，氧化剂，防腐蚀剂和作为在浆料中显示负电荷的阴离子化合物的去除速率还原剂。抛光浆料可用于制造半导体器件的方法中。

2. 发明授权

US08735250B2 Methods of forming gates of semiconductor devices 有权
标题翻译：形成半导体器件栅极的方法
公开(公告)号：US08735250B2
公开(公告)日：2014-05-27
申请号：US13241957
申请日：2011-09-23
申请人： Jong-Won Lee , Bo-Un Yoon , Seung-Jae Lee
发明人： Jong-Won Lee , Bo-Un Yoon , Seung-Jae Lee
IPC分类号： H01L21/8234
CPC分类号： H01L21/28008 , H01L21/28105 , H01L21/823842 , H01L29/42376 , H01L29/49 , H01L29/513 , H01L29/66545
摘要： Methods of forming gates of semiconductor devices are provided. The methods may include forming a first recess in a first substrate region having a first conductivity type and forming a second recess in a second substrate region having a second conductivity type. The methods may also include forming a high-k layer in the first and second recesses. The methods may further include providing a first metal on the high-k layer in the first and second substrate regions, the first metal being provided within the second recess. The methods may additionally include removing at least portions of the first metal from the second recess while protecting materials within the first recess from removal. The methods may also include, after removing at least portions of the first metal from the second recess, providing a second metal within the second recess.
摘要翻译：提供了形成半导体器件的栅极的方法。所述方法可以包括在具有第一导电类型的第一衬底区域中形成第一凹槽，并在具有第二导电类型的第二衬底区域中形成第二凹部。所述方法还可以包括在第一和第二凹部中形成高k层。所述方法还可以包括在第一和第二衬底区域中的高k层上提供第一金属，第一金属设置在第二凹槽内。所述方法还可以包括从第二凹部移除第一金属的至少一部分，同时保护第一凹槽内的材料不被去除。所述方法还可以包括在从第二凹部去除第一金属的至少一部分之后，在第二凹部内提供第二金属。

3. 发明申请

US20120088358A1 Methods of Forming Gates of Semiconductor Devices 有权
标题翻译：半导体器件门形成方法
公开(公告)号：US20120088358A1
公开(公告)日：2012-04-12
申请号：US13241957
申请日：2011-09-23
申请人： Jong-Won Lee , Bo-Un Yoon , Seung-Jae Lee
发明人： Jong-Won Lee , Bo-Un Yoon , Seung-Jae Lee
IPC分类号： H01L21/336
CPC分类号： H01L21/28008 , H01L21/28105 , H01L21/823842 , H01L29/42376 , H01L29/49 , H01L29/513 , H01L29/66545
摘要： Methods of forming gates of semiconductor devices are provided. The methods may include forming a first recess in a first substrate region having a first conductivity type and forming a second recess in a second substrate region having a second conductivity type. The methods may also include forming a high-k layer in the first and second recesses. The methods may further include providing a first metal on the high-k layer in the first and second substrate regions, the first metal being provided within the second recess. The methods may additionally include removing at least portions of the first metal from the second recess while protecting materials within the first recess from removal. The methods may also include, after removing at least portions of the first metal from the second recess, providing a second metal within the second recess.
摘要翻译：提供了形成半导体器件的栅极的方法。所述方法可以包括在具有第一导电类型的第一衬底区域中形成第一凹槽，并在具有第二导电类型的第二衬底区域中形成第二凹部。所述方法还可以包括在第一和第二凹部中形成高k层。所述方法还可以包括在第一和第二衬底区域中的高k层上提供第一金属，第一金属设置在第二凹槽内。所述方法还可以包括从第二凹部移除第一金属的至少一部分，同时保护第一凹槽内的材料不被去除。所述方法还可以包括在从第二凹部去除第一金属的至少一部分之后，在第二凹部内提供第二金属。

4. 发明申请

US20100015729A1 METHODS OF FORMING A THIN FERROELECTRIC LAYER AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING THE SAME 失效
标题翻译：形成薄膜层的方法和制造包括其的半导体器件的方法
公开(公告)号：US20100015729A1
公开(公告)日：2010-01-21
申请号：US12503440
申请日：2009-07-15
申请人： Suk-Hun Choi , Jong-Won Lee , Chang-Ki Hong , Bo-Un Yoon
发明人： Suk-Hun Choi , Jong-Won Lee , Chang-Ki Hong , Bo-Un Yoon
IPC分类号： H01L21/28
CPC分类号： H01L27/11507 , H01L21/3105 , H01L21/31053 , H01L28/55
摘要： In methods of forming a thin ferroelectric layer and methods of manufacturing a semiconductor device, a preliminary ferroelectric layer is formed on a substrate by depositing a metal oxide including lead, zirconium and titanium. The surface of the preliminary ferroelectric layer is polished using a slurry composition including an acrylic acid polymer, abrasive particles, and water to form a thin ferroelectric layer on the substrate. The slurry composition may reduce a polishing rate of the preliminary ferroelectric layer such that removal of a bulk portion of the preliminary ferroelectric layer may be suppressed and the surface roughness of the preliminary ferroelectric layer may be improved.
摘要翻译：在形成薄铁电体层的方法和制造半导体器件的方法中，通过沉积包括铅，锆和钛的金属氧化物，在衬底上形成初步铁电层。使用包括丙烯酸聚合物，磨料颗粒和水的浆料组合物对预制铁电层的表面进行抛光，以在基材上形成薄铁电层。浆料组合物可以降低预备铁电体层的抛光速率，从而可以抑制初级铁电层的体积部分的去除，并且可以提高预铁电层的表面粗糙度。

5. 发明授权

US08617991B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08617991B2
公开(公告)日：2013-12-31
申请号：US13526960
申请日：2012-06-19
申请人： Jung-Chan Lee , Yoo-Jung Lee , Ki-Hyung Ko , Dae-Young Kwak , Seung-Jae Lee , Jae-Sung Hur , Sang-Bom Kang , Cheol Kim , Bo-Un Yoon
发明人： Jung-Chan Lee , Yoo-Jung Lee , Ki-Hyung Ko , Dae-Young Kwak , Seung-Jae Lee , Jae-Sung Hur , Sang-Bom Kang , Cheol Kim , Bo-Un Yoon
IPC分类号： H01L21/44
CPC分类号： H01L29/4983 , H01L21/76895 , H01L21/82345 , H01L29/49 , H01L29/66545 , H01L29/78
摘要： A method of manufacturing a semiconductor device includes forming an interlayer dielectric film that has first and second trenches on first and second regions of a substrate, respectively, forming a first metal layer along a sidewall and a bottom surface of the first trench and along a top surface of the interlayer dielectric film in the first region, forming a second metal layer along a sidewall and a bottom surface of the second trench and along a top surface of the interlayer dielectric film in the second region, forming a first sacrificial layer pattern on the first metal layer such that the first sacrificial layer fills a portion of the first trench, forming a first electrode layer by etching the first metal layer and the second metal layer using the first sacrificial layer pattern, and removing the first sacrificial layer pattern.
摘要翻译：一种制造半导体器件的方法包括：在衬底的第一和第二区域上分别形成具有第一和第二沟槽的层间电介质膜，沿着第一沟槽的侧壁和底表面沿顶部形成第一金属层在所述第一区域中的所述层间电介质膜的表面，沿着所述第二沟槽的侧壁和底表面沿着所述第二区域中的所述层间电介质膜的顶表面形成第二金属层，在所述第二区域中形成第一牺牲层图案第一金属层，使得第一牺牲层填充第一沟槽的一部分，通过使用第一牺牲层图案蚀刻第一金属层和第二金属层形成第一电极层，以及去除第一牺牲层图案。

6. 发明申请

US20090155991A1 Methods of fabricating a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20090155991A1
公开(公告)日：2009-06-18
申请号：US12292195
申请日：2008-11-13
申请人： Jong-Won Lee , Sang-Yeob Han , Chang-Ki Hong , Bo-Un Yoon , Jae-Dong Lee
发明人： Jong-Won Lee , Sang-Yeob Han , Chang-Ki Hong , Bo-Un Yoon , Jae-Dong Lee
IPC分类号： H01L21/4763
CPC分类号： H01L21/76897 , H01L27/10855 , H01L27/10873 , H01L27/10888 , H01L29/6653
摘要： A method of fabricating a contact plug of a semiconductor device is provided, the method includes forming a gate pattern on a substrate, forming a capping pattern to cover an upper surface and sidewalls of the gate pattern, forming an interlayer insulation layer on the substrate such that the interlayer insulation layer exposes an upper surface of the capping pattern, and removing a portion of the capping pattern and the interlayer insulation layer such that the upper surface of the capping pattern is planarized.
摘要翻译：提供了制造半导体器件的接触插塞的方法，该方法包括在衬底上形成栅极图案，形成覆盖图案的上表面和侧壁的封盖图案，在衬底上形成层间绝缘层，如层间绝缘层暴露封盖图案的上表面，并且去除封盖图案和层间绝缘层的一部分，使得封盖图案的上表面被平坦化。

7. 发明授权

US08084344B2 Methods of fabricating a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08084344B2
公开(公告)日：2011-12-27
申请号：US12292195
申请日：2008-11-13
申请人： Jong-Won Lee , Sang-Yeob Han , Chang-Ki Hong , Bo-Un Yoon , Jae-Dong Lee
发明人： Jong-Won Lee , Sang-Yeob Han , Chang-Ki Hong , Bo-Un Yoon , Jae-Dong Lee
IPC分类号： H01L21/4763
CPC分类号： H01L21/76897 , H01L27/10855 , H01L27/10873 , H01L27/10888 , H01L29/6653
摘要： A method of fabricating a contact plug of a semiconductor device is provided, the method includes forming a gate pattern on a substrate, forming a capping pattern to cover an upper surface and sidewalls of the gate pattern, forming an interlayer insulation layer on the substrate such that the interlayer insulation layer exposes an upper surface of the capping pattern, and removing a portion of the capping pattern and the interlayer insulation layer such that the upper surface of the capping pattern is planarized.
摘要翻译：提供了制造半导体器件的接触插塞的方法，该方法包括在衬底上形成栅极图案，形成覆盖图案的上表面和侧壁的封盖图案，在衬底上形成层间绝缘层，如层间绝缘层暴露封盖图案的上表面，并且去除封盖图案和层间绝缘层的一部分，使得封盖图案的上表面被平坦化。

8. 发明授权

US08399327B2 Methods of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08399327B2
公开(公告)日：2013-03-19
申请号：US13240560
申请日：2011-09-22
申请人： Jong-Won Lee , Jae-Seok Kim , Bo-Un Yoon
发明人： Jong-Won Lee , Jae-Seok Kim , Bo-Un Yoon
IPC分类号： H01L21/336
CPC分类号： H01L21/823842 , H01L21/823437 , H01L29/165 , H01L29/66545 , H01L29/66628 , H01L29/7835
摘要： A method includes forming a plurality of dummy gate structures on a substrate, each dummy gate structure including a dummy gate electrode and a dummy gate mask, forming a first insulation layer on the substrate and the dummy gate structures to fill a first space between the dummy gate structures, planarizing upper portions of the first insulation layer and the dummy gate structures, removing the remaining first insulation layer to expose a portion of the substrate, forming an etch stop layer on the remaining dummy gate structures and the exposed portion of the substrate, forming a second insulation layer on the etch stop layer to fill a second space between the dummy gate structures, planarizing upper portions of the second insulation layer and the etch stop layer to expose the dummy gate electrodes, removing the exposed dummy gate electrodes to form trenches, and forming metal gate electrodes in the trenches.
摘要翻译：一种方法包括在衬底上形成多个虚拟栅极结构，每个虚拟栅极结构包括伪栅极电极和伪栅极掩模，在衬底上形成第一绝缘层和虚拟栅极结构以填充虚拟栅极结构之间的第一空间栅极结构，平坦化第一绝缘层和伪栅极结构的上部，去除剩余的第一绝缘层以暴露衬底的一部分，在剩余的虚设栅极结构和衬底的暴露部分上形成蚀刻停止层，在所述蚀刻停止层上形成第二绝缘层以填充所述虚拟栅极结构之间的第二空间，平坦化所述第二绝缘层的上部和所述蚀刻停止层以暴露所述伪栅电极，去除所述暴露的伪栅电极以形成沟槽并且在沟槽中形成金属栅电极。

9. 发明申请

US20120122283A1 METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120122283A1
公开(公告)日：2012-05-17
申请号：US13240560
申请日：2011-09-22
申请人： Jong-Won LEE , Jae-Seok Kim , Bo-Un Yoon
发明人： Jong-Won LEE , Jae-Seok Kim , Bo-Un Yoon
IPC分类号： H01L21/336 , H01L21/28
CPC分类号： H01L21/823842 , H01L21/823437 , H01L29/165 , H01L29/66545 , H01L29/66628 , H01L29/7835
摘要： A method includes forming a plurality of dummy gate structures on a substrate, each dummy gate structure including a dummy gate electrode and a dummy gate mask, forming a first insulation layer on the substrate and the dummy gate structures to fill a first space between the dummy gate structures, planarizing upper portions of the first insulation layer and the dummy gate structures, removing the remaining first insulation layer to expose a portion of the substrate, forming an etch stop layer on the remaining dummy gate structures and the exposed portion of the substrate, forming a second insulation layer on the etch stop layer to fill a second space between the dummy gate structures, planarizing upper portions of the second insulation layer and the etch stop layer to expose the dummy gate electrodes, removing the exposed dummy gate electrodes to form trenches, and forming metal gate electrodes in the trenches.
摘要翻译：一种方法包括在衬底上形成多个虚拟栅极结构，每个虚拟栅极结构包括伪栅极电极和伪栅极掩模，在衬底上形成第一绝缘层和虚拟栅极结构以填充虚拟栅极结构之间的第一空间栅极结构，平坦化第一绝缘层和伪栅极结构的上部，去除剩余的第一绝缘层以暴露衬底的一部分，在剩余的虚设栅极结构和衬底的暴露部分上形成蚀刻停止层，在所述蚀刻停止层上形成第二绝缘层以填充所述虚拟栅极结构之间的第二空间，平坦化所述第二绝缘层的上部和所述蚀刻停止层以暴露所述伪栅电极，去除所述暴露的伪栅电极以形成沟槽并且在沟槽中形成金属栅电极。

10. 发明授权

US08124526B2 Methods of forming a thin ferroelectric layer and methods of manufacturing a semiconductor device including the same 失效
标题翻译：形成薄铁电体层的方法和制造其的半导体器件的制造方法
公开(公告)号：US08124526B2
公开(公告)日：2012-02-28
申请号：US12503440
申请日：2009-07-15
申请人： Suk-Hun Choi , Jong-Won Lee , Chang-Ki Hong , Bo-Un Yoon
发明人： Suk-Hun Choi , Jong-Won Lee , Chang-Ki Hong , Bo-Un Yoon
IPC分类号： H01L21/4763
CPC分类号： H01L27/11507 , H01L21/3105 , H01L21/31053 , H01L28/55
摘要： In methods of forming a thin ferroelectric layer and methods of manufacturing a semiconductor device, a preliminary ferroelectric layer is formed on a substrate by depositing a metal oxide including lead, zirconium and titanium. The surface of the preliminary ferroelectric layer is polished using a slurry composition including an acrylic acid polymer, abrasive particles, and water to form a thin ferroelectric layer on the substrate. The slurry composition may reduce a polishing rate of the preliminary ferroelectric layer such that removal of a bulk portion of the preliminary ferroelectric layer may be suppressed and the surface roughness of the preliminary ferroelectric layer may be improved.
摘要翻译：在形成薄铁电体层的方法和制造半导体器件的方法中，通过沉积包括铅，锆和钛的金属氧化物，在衬底上形成初步铁电层。使用包括丙烯酸聚合物，磨料颗粒和水的浆料组合物对预制铁电层的表面进行抛光，以在基材上形成薄铁电层。浆料组合物可以降低预备铁电体层的抛光速率，从而可以抑制初级铁电层的体积部分的去除，并且可以提高预铁电层的表面粗糙度。

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