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1. 发明授权

US08563383B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08563383B2
公开(公告)日：2013-10-22
申请号：US13252621
申请日：2011-10-04
申请人： Sang-Jin Kim , Jong-Chan Shin , Yong-Kug Bae , Myeong-Cheol Kim , Do-Hyoung Kim
发明人： Sang-Jin Kim , Jong-Chan Shin , Yong-Kug Bae , Myeong-Cheol Kim , Do-Hyoung Kim
IPC分类号： H01L21/336
CPC分类号： H01L21/823425 , H01L21/823437 , H01L29/66545 , H01L29/66628 , H01L29/7834
摘要： A method of manufacturing a semiconductor device includes forming a plurality of gate structures including a metal on a substrate having an isolation layer, forming first insulating interlayer patterns covering sidewalls of the gate structures, forming first capping layer patterns and a second capping layer pattern on the gate structures and the first insulating interlayer patterns, the first capping layer patterns covering upper faces of the gate structures, and the second capping layer pattern overlapping the isolation layer, partially removing the first insulating interlayer patterns using the first and the second capping layer patterns as etching masks to form first openings that expose portions of the substrate, forming metal silicide patterns on the portions of the substrate exposed in the forming of the first openings, and forming conductive structures on the metal silicide patterns.
摘要翻译：制造半导体器件的方法包括在具有隔离层的衬底上形成包括金属的多个栅极结构，形成覆盖栅极结构的侧壁的第一绝缘层间图案，形成第一覆盖层图案和第二覆盖层图案栅极结构和第一绝缘层间图案，第一覆盖层图案覆盖栅极结构的上表面，第二覆盖层图案与隔离层重叠，使用第一和第二覆盖层图案部分地去除第一绝缘层间图案，如蚀刻掩模以形成暴露基板部分的第一开口，在形成第一开口的裸露部分上形成金属硅化物图案，并在金属硅化物图案上形成导电结构。

2. 发明申请

US20120122284A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120122284A1
公开(公告)日：2012-05-17
申请号：US13252621
申请日：2011-10-04
申请人： Sang-Jin KIM , Jong-Chan Shin , Yong-Kug Bae , Myeong-Cheol Kim , Do-Hyoung Kim
发明人： Sang-Jin KIM , Jong-Chan Shin , Yong-Kug Bae , Myeong-Cheol Kim , Do-Hyoung Kim
IPC分类号： H01L21/336
CPC分类号： H01L21/823425 , H01L21/823437 , H01L29/66545 , H01L29/66628 , H01L29/7834
摘要： A method of manufacturing a semiconductor device includes forming a plurality of gate structures including a metal on a substrate having an isolation layer, forming first insulating interlayer patterns covering sidewalls of the gate structures, forming first capping layer patterns and a second capping layer pattern on the gate structures and the first insulating interlayer patterns, the first capping layer patterns covering upper faces of the gate structures, and the second capping layer pattern overlapping the isolation layer, partially removing the first insulating interlayer patterns using the first and the second capping layer patterns as etching masks to form first openings that expose portions of the substrate, forming metal silicide patterns on the portions of the substrate exposed in the forming of the first openings, and forming conductive structures on the metal silicide patterns.
摘要翻译：制造半导体器件的方法包括在具有隔离层的衬底上形成包括金属的多个栅极结构，形成覆盖栅极结构的侧壁的第一绝缘层间图案，形成第一覆盖层图案和第二覆盖层图案栅极结构和第一绝缘层间图案，第一覆盖层图案覆盖栅极结构的上表面，第二覆盖层图案与隔离层重叠，使用第一和第二覆盖层图案部分地去除第一绝缘层间图案，如蚀刻掩模以形成暴露基板部分的第一开口，在形成第一开口的裸露部分上形成金属硅化物图案，并在金属硅化物图案上形成导电结构。

3. 发明授权

US08900944B2 Methods of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08900944B2
公开(公告)日：2014-12-02
申请号：US13307270
申请日：2011-11-30
申请人： Soo-Yeon Jeong , Myeong-Cheol Kim , Do-Hyoung Kim , Do-Haing Lee , Nam-Myun Cho , In-Ho Kim
发明人： Soo-Yeon Jeong , Myeong-Cheol Kim , Do-Hyoung Kim , Do-Haing Lee , Nam-Myun Cho , In-Ho Kim
IPC分类号： H01L21/8238 , H01L29/49 , H01L29/66 , H01L21/768 , H01L21/285
CPC分类号： H01L27/088 , H01L21/28518 , H01L21/76897 , H01L29/45 , H01L29/49 , H01L29/66545
摘要： A method of manufacturing a semiconductor device includes forming a gate structure through a first insulating interlayer on a substrate such that the gate structure includes a spacer on a sidewall thereof, forming a first hard mask on the gate structure, partially removing the first insulating interlayer using the first hard mask as an etching mask to form a first contact hole such that the first contact hole exposes a top surface of the substrate, forming a metal silicide pattern on the top surface of the substrate exposed by the first contact hole, and forming a plug electrically connected to the metal silicide pattern.
摘要翻译：一种制造半导体器件的方法包括通过基板上的第一绝缘中间层形成栅极结构，使得栅极结构在其侧壁上包括间隔物，在栅极结构上形成第一硬掩模，使用所述第一硬掩模作为蚀刻掩模以形成第一接触孔，使得所述第一接触孔暴露所述基板的顶表面，在所述基板的由所述第一接触孔暴露的所述顶表面上形成金属硅化物图案，并形成插头电连接到金属硅化物图案。

4. 发明申请

US20120156867A1 METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120156867A1
公开(公告)日：2012-06-21
申请号：US13307270
申请日：2011-11-30
申请人： Soo-Yeon Jeong , Myeong-Cheol Kim , Do-Hyoung Kim , Do-Haing Lee , Nam-Myun Cho , In-Ho Kim
发明人： Soo-Yeon Jeong , Myeong-Cheol Kim , Do-Hyoung Kim , Do-Haing Lee , Nam-Myun Cho , In-Ho Kim
IPC分类号： H01L21/283
CPC分类号： H01L27/088 , H01L21/28518 , H01L21/76897 , H01L29/45 , H01L29/49 , H01L29/66545
摘要： A method of manufacturing a semiconductor device includes forming a gate structure through a first insulating interlayer on a substrate such that the gate structure includes a spacer on a sidewall thereof, forming a first hard mask on the gate structure, partially removing the first insulating interlayer using the first hard mask as an etching mask to form a first contact hole such that the first contact hole exposes a top surface of the substrate, forming a metal silicide pattern on the top surface of the substrate exposed by the first contact hole, and forming a plug electrically connected to the metal silicide pattern.
摘要翻译：一种制造半导体器件的方法包括通过基板上的第一绝缘中间层形成栅极结构，使得栅极结构在其侧壁上包括间隔物，在栅极结构上形成第一硬掩模，使用所述第一硬掩模作为蚀刻掩模以形成第一接触孔，使得所述第一接触孔暴露所述基板的顶表面，在所述基板的由所述第一接触孔暴露的所述顶表面上形成金属硅化物图案，并形成插头电连接到金属硅化物图案。

5. 发明授权

US08592265B2 Method for manufacturing semiconductor device having a metal gate electrode 有权
标题翻译：具有金属栅电极的半导体器件的制造方法
公开(公告)号：US08592265B2
公开(公告)日：2013-11-26
申请号：US13242382
申请日：2011-09-23
申请人： Dong-Kwon Kim , Young-Ju Park , Dong-Hyuk Yeam , Yoo-Jung Lee , Myeong-Cheol Kim , Do-Hyoung Kim , Heung-Sik Park
发明人： Dong-Kwon Kim , Young-Ju Park , Dong-Hyuk Yeam , Yoo-Jung Lee , Myeong-Cheol Kim , Do-Hyoung Kim , Heung-Sik Park
IPC分类号： H01L21/338
CPC分类号： H01L21/28132 , H01L21/28114 , H01L29/42376 , H01L29/4966 , H01L29/66545 , H01L29/6656
摘要： Example embodiments relate to a method for manufacturing a semiconductor device, wherein a metal gate electrode therein may be formed without a void in a lower portion of the metal gate electrode. The method may include providing a substrate, forming a dummy gate electrode on the substrate, forming a gate spacer on the substrate to be contiguous to the dummy gate electrode, forming a first recess by simultaneously removing a portion of the dummy gate electrode and a portion of the gate spacer, the first recess having an upper end wider than a lower end, forming a second recess by removing the dummy gate electrode remaining after forming the first recess, and forming a metal gate electrode by depositing a metal to fill the first and second recesses.
摘要翻译：示例性实施例涉及用于制造半导体器件的方法，其中可以在金属栅电极的下部中形成其中的金属栅极电极，而不产生空隙。该方法可以包括提供衬底，在衬底上形成虚拟栅电极，在衬底上形成与虚拟栅电极相邻的栅极间隔物，通过同时去除虚设栅电极的一部分形成第一凹槽，所述第一凹部具有比下端更宽的上端，通过去除在形成所述第一凹部之后残留的所述虚设栅电极形成第二凹槽，以及通过沉积金属以填充所述第一凹部而形成金属栅电极，以填充所述第一凹部第二个凹槽

6. 发明申请

US20130023118A1 METHOD FOR FORMING PATTERN AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING THE SAME 审中-公开
标题翻译：用于形成图案的方法和使用其制造半导体器件的方法
公开(公告)号：US20130023118A1
公开(公告)日：2013-01-24
申请号：US13493321
申请日：2012-06-11
申请人： Soo-Yeon Jeong , Dong-Kwon Kim , Do-Hyoung Kim , Myeong-Cheol Kim
发明人： Soo-Yeon Jeong , Dong-Kwon Kim , Do-Hyoung Kim , Myeong-Cheol Kim
IPC分类号： H01L21/311 , H01L21/768
CPC分类号： H01L21/31144 , H01L21/76811 , H01L21/76816
摘要： There is provided a method for forming a pattern comprising, forming a first layer on an underlying layer including a substrate, forming a first mask pattern including a first opening pattern on the first layer, and forming a second mask pattern including a second opening pattern on the first mask pattern, wherein the second opening pattern includes a first region overlapping the first opening pattern and a second region not overlapping the first opening pattern, and etching is performed using the second mask pattern such that a third opening pattern corresponding to the first region and exposing an upper surface of the underlying layer is formed in the first layer, and a fourth opening pattern corresponding to the second region is formed in the first mask pattern.
摘要翻译：提供了一种用于形成图案的方法，包括：在包括基底的下层上形成第一层，在第一层上形成包括第一开口图案的第一掩模图案，以及在第一层上形成包括第二开口图案的第二掩模图案第一掩模图案，其中第二开口图案包括与第一开口图案重叠的第一区域和不与第一开口图案重叠的第二区域，并且使用第二掩模图案进行蚀刻，使得对应于第一开口图案的第一开口图案并且在第一层中形成下面的层的上表面，并且在第一掩模图案中形成与第二区域对应的第四开口图案。

7. 发明申请

US20120135577A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120135577A1
公开(公告)日：2012-05-31
申请号：US13304936
申请日：2011-11-28
申请人： Doo-Young LEE , Ki Il Kim , Myeong-Cheol Kim , Do-Hyoung Kim , Do-Hsing Lee
发明人： Doo-Young LEE , Ki Il Kim , Myeong-Cheol Kim , Do-Hyoung Kim , Do-Hsing Lee
IPC分类号： H01L21/336 , H01L21/28
CPC分类号： H01L29/78 , H01L21/76829 , H01L21/76832 , H01L21/76895 , H01L21/76897 , H01L29/66545
摘要： A method of manufacturing a semiconductor device, including the second sacrificial layer receiving a gate structure include a metal and a spacer on a sidewall of the gate structure therethrough being formed on a substrate. The second sacrificial layer is removed. A second etch stop layer and an insulating interlayer are sequentially formed on the gate structure, the spacer and the substrate. An opening passing through the insulating interlayer is formed to expose a portion of the gate structure, a portion of the spacer and a portion of the second etch stop layer on a portion of the substrate. The second etch stop layer being exposed through the opening is removed. The contact being electrically connected to the gate structure and the substrate and filling the opening is formed. The semiconductor device having the metal gate electrode and the shared contact has a desired leakage current characteristic and resistivity characteristics.
摘要翻译：包括接收栅极结构的第二牺牲层的半导体器件的制造方法包括在基板上形成的栅极结构的侧壁上的金属和间隔物。去除第二牺牲层。在栅极结构，间隔物和衬底上依次形成第二蚀刻停止层和绝缘中间层。形成通过绝缘中间层的开口以暴露栅极结构的一部分，间隔物的一部分和第二蚀刻停止层的一部分在衬底的一部分上。去除通过开口露出的第二蚀刻停止层。形成与栅极结构和基板电连接并填充开口的触点。具有金属栅电极和共用触点的半导体器件具有期望的漏电流特性和电阻率特性。

8. 发明申请

US20120088359A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120088359A1
公开(公告)日：2012-04-12
申请号：US13242382
申请日：2011-09-23
申请人： Dong-Kwon Kim , Young-Ju Park , Dong-Hyuk Yeam , Yoo-Jung Lee , Myeong-Cheol Kim , Do-Hyoung Kim , Heung-Sik Park
发明人： Dong-Kwon Kim , Young-Ju Park , Dong-Hyuk Yeam , Yoo-Jung Lee , Myeong-Cheol Kim , Do-Hyoung Kim , Heung-Sik Park
IPC分类号： H01L21/336
CPC分类号： H01L21/28132 , H01L21/28114 , H01L29/42376 , H01L29/4966 , H01L29/66545 , H01L29/6656
摘要： Example embodiments relate to a method for manufacturing a semiconductor device, wherein a metal gate electrode therein may be formed without a void in a lower portion of the metal gate electrode. The method may include providing a substrate, forming a dummy gate electrode on the substrate, forming a gate spacer on the substrate to be contiguous to the dummy gate electrode, forming a first recess by simultaneously removing a portion of the dummy gate electrode and a portion of the gate spacer, the first recess having an upper end wider than a lower end, forming a second recess by removing the dummy gate electrode remaining after forming the first recess, and forming a metal gate electrode by depositing a metal to fill the first and second recesses.
摘要翻译：示例性实施例涉及用于制造半导体器件的方法，其中可以在金属栅电极的下部中形成其中的金属栅极电极，而不产生空隙。该方法可以包括提供衬底，在衬底上形成虚拟栅电极，在衬底上形成与虚拟栅电极相邻的栅极间隔物，通过同时去除虚拟栅电极的一部分形成第一凹槽，所述第一凹部具有比下端更宽的上端，通过去除在形成所述第一凹部之后残留的所述虚设栅电极形成第二凹槽，以及通过沉积金属以填充所述第一凹部而形成金属栅电极，以填充所述第一凹部第二个凹槽

9. 发明授权

US08927355B2 Method of manufacturing semiconductor devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08927355B2
公开(公告)日：2015-01-06
申请号：US13304936
申请日：2011-11-28
申请人： Doo-Young Lee , Ki Il Kim , Myeong-Cheol Kim , Do-Hyoung Kim , Do-Hsing Lee
发明人： Doo-Young Lee , Ki Il Kim , Myeong-Cheol Kim , Do-Hyoung Kim , Do-Hsing Lee
IPC分类号： H01L21/339 , H01L21/768 , H01L29/78 , H01L29/66
CPC分类号： H01L29/78 , H01L21/76829 , H01L21/76832 , H01L21/76895 , H01L21/76897 , H01L29/66545
摘要： A method of manufacturing a semiconductor device, including the second sacrificial layer receiving a gate structure include a metal and a spacer on a sidewall of the gate structure therethrough being formed on a substrate. The second sacrificial layer is removed. A second etch stop layer and an insulating interlayer are sequentially formed on the gate structure, the spacer and the substrate. An opening passing through the insulating interlayer is formed to expose a portion of the gate structure, a portion of the spacer and a portion of the second etch stop layer on a portion of the substrate. The second etch stop layer being exposed through the opening is removed. The contact being electrically connected to the gate structure and the substrate and filling the opening is formed. The semiconductor device having the metal gate electrode and the shared contact has a desired leakage current characteristic and resistivity characteristics.
摘要翻译：包括接收栅极结构的第二牺牲层的半导体器件的制造方法包括在基板上形成的栅极结构的侧壁上的金属和间隔物。去除第二牺牲层。在栅极结构，间隔物和衬底上依次形成第二蚀刻停止层和绝缘中间层。形成通过绝缘中间层的开口以暴露栅极结构的一部分，间隔物的一部分和第二蚀刻停止层的一部分在衬底的一部分上。去除通过开口露出的第二蚀刻停止层。形成与栅极结构和基板电连接并填充开口的触点。具有金属栅电极和共用触点的半导体器件具有期望的漏电流特性和电阻率特性。

10. 发明授权

US08254299B2 Multimedia broadcast/multicast service cells reconfigurations 有权
标题翻译：多媒体广播/组播服务小区重新配置
公开(公告)号：US08254299B2
公开(公告)日：2012-08-28
申请号：US11909714
申请日：2006-03-29
申请人： Myeong-Cheol Kim
发明人： Myeong-Cheol Kim
IPC分类号： H04H20/21
CPC分类号： H04W72/005 , H04W48/08 , H04W48/10 , H04W56/00
摘要： The invention proposes a method for indicating the validity of physical channels of a control cell and a neighboring cell carrying point-to-multipoint service data in a wireless communication system. The method includes the following steps: generating a message comprising configuration information for each of said channels; including validity information with the message for deriving the validity timing of the configuration information for each of said channels; and transmitting the message to a mobile terminal (10) through the control cell. The invention also proposes a mobile equipment (10) and a Radio Network Controller (111), respectively adapted to implement the above method.
摘要翻译：本发明提出了一种用于指示无线通信系统中控制小区和携带点对多点业务数据的相邻小区的物理信道的有效性的方法。该方法包括以下步骤：产生包括每个所述信道的配置信息的消息; 包括具有用于导出每个所述信道的配置信息的有效性定时的消息的有效性信息; 以及通过所述控制小区将所述消息发送到移动终端（10）。本发明还提出了分别适于实现上述方法的移动设备（10）和无线网络控制器（111）。

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