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1. 发明申请

US20150260196A1 FLY WHEEL 审中-公开
标题翻译：飞轮
公开(公告)号：US20150260196A1
公开(公告)日：2015-09-17
申请号：US14423250
申请日：2013-07-03
申请人： Sang Tae AHN , Chun Young AHN
发明人： Sang Tae Ahn , Chun Young Ahn
IPC分类号： F04D29/26 , F16F15/30
CPC分类号： F04D29/26 , B60Y2400/162 , F01D1/32 , F03G3/08 , F16F15/30 , F16F2226/00
摘要： Provided is a fly wheel, including: a fly wheel body provided with a receiving part in which air is filled and mounted on driving shaft; a blade radially coupled to the fly wheel body, including a ventilation passage formed therein to be communicated with the receiving part and a puncturing part formed on an outer race thereof to be communicated with the ventilation passage, and generating thrust by discharging the air filled in the receiving part to the puncturing part at the time of rotating the driving shaft; and a check valve installed on the fly wheel body and being opened and closed by a pressure difference between the receiving part and the outside.
摘要翻译：本发明提供一种飞轮，包括：飞轮主体，其设置有容纳部，空气被填充并安装在驱动轴上; 径向耦合到所述飞轮主体的叶片，包括形成在其中的通风通道，以与所述接收部分连通，以及形成在其外圈上的穿刺部分，以与所述通风通道连通，并且通过排出填充的空气产生推力所述接收部在旋转所述驱动轴时到达所述穿刺部; 以及安装在飞轮体上并通过接收部和外部之间的压力差打开和关闭的止回阀。

2. 发明授权

US09695836B2 Fly wheel 有权
公开(公告)号：US09695836B2
公开(公告)日：2017-07-04
申请号：US14423250
申请日：2013-07-03
申请人： Sang Tae Ahn , Chun Young Ahn
发明人： Sang Tae Ahn , Chun Young Ahn
IPC分类号： F01D1/32 , F04D29/26 , F03G3/08 , F16F15/30
CPC分类号： F04D29/26 , B60Y2400/162 , F01D1/32 , F03G3/08 , F16F15/30 , F16F2226/00
摘要： Provided is a fly wheel, including: a fly wheel body provided with a receiving part in which air is filled and mounted on driving shaft; a blade radially coupled to the fly wheel body, including a ventilation passage formed therein to be communicated with the receiving part and a puncturing part formed on an outer race thereof to be communicated with the ventilation passage, and generating thrust by discharging the air filled in the receiving part to the puncturing part at the time of rotating the driving shaft; and a check valve installed on the fly wheel body and being opened and closed by a pressure difference between the receiving part and the outside.

3. 发明授权

US08178921B2 Semiconductor device having reduced standby leakage current and increased driving current and method for manufacturing the same 有权
标题翻译：具有降低的待机漏电流和增加的驱动电流的半导体器件及其制造方法
公开(公告)号：US08178921B2
公开(公告)日：2012-05-15
申请号：US12638233
申请日：2009-12-15
申请人： Dong Sun Sheen , Sang Tae Ahn , Seok Pyo Song , Hyeon Ju An
发明人： Dong Sun Sheen , Sang Tae Ahn , Seok Pyo Song , Hyeon Ju An
IPC分类号： H01L29/78
CPC分类号： H01L29/78609 , H01L29/66795 , H01L29/7851
摘要： A semiconductor device includes a semiconductor substrate having an active region which includes a gate forming zone and an isolation region; an isolation layer formed in the isolation region of the semiconductor substrate to expose side surfaces of a portion of the active region including the gate forming zone, such that the portion of the active region including the gate forming zone constitutes a fin pattern; a silicon epitaxial layer formed on the active region including the fin pattern; and a gate formed to cover the fin pattern on which the silicon epitaxial layer is formed.
摘要翻译：半导体器件包括具有包括栅极形成区和隔离区的有源区的半导体衬底; 隔离层，其形成在所述半导体衬底的隔离区域中，以暴露包括所述栅极形成区的有源区的一部分的侧表面，使得包括所述栅极形成区的有源区的所述部分构成鳍状图案; 形成在包括鳍状图案的有源区上的硅外延层; 以及形成为覆盖其上形成有硅外延层的鳍图案的栅极。

4. 发明申请

US20130157453A1 METHODS OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20130157453A1
公开(公告)日：2013-06-20
申请号：US13602104
申请日：2012-09-01
申请人： Sang Tae Ahn
发明人： Sang Tae Ahn
IPC分类号： H01L21/28
CPC分类号： H01L29/788 , B82Y10/00 , B82Y40/00 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L29/0673 , H01L29/42332 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： A method of manufacturing a semiconductor device includes forming first auxiliary patterns, alternately forming first material layers and second material layers on the sidewalls of the first auxiliary patterns so that a gap region between the first auxiliary patterns adjacent to each other is filled, removing the second material layers, and forming charge storage layers in respective regions from which the second material layers have been removed.
摘要翻译：一种制造半导体器件的方法包括：形成第一辅助图案，在第一辅助图案的侧壁上交替地形成第一材料层和第二材料层，使得填充彼此相邻的第一辅助图案之间的间隙区域，材料层，并且在已经从其去除了第二材料层的各个区域中形成电荷存储层。

5. 发明授权

US08202807B2 Template derivative for forming ultra-low dielectric layer and method of forming ultra-low dielectric layer using the same 有权
标题翻译：用于形成超低介电层的模板衍生物和使用其形成超低介电层的方法
公开(公告)号：US08202807B2
公开(公告)日：2012-06-19
申请号：US11964950
申请日：2007-12-27
申请人： Sung Kyu Min , Ja Chun Ku , Chan Bae Kim , Sang Tae Ahn , Chai O Chung , Hyeon Ju An , Hyo Seok Lee , Eun Jeong Kim
发明人： Sung Kyu Min , Ja Chun Ku , Chan Bae Kim , Sang Tae Ahn , Chai O Chung , Hyeon Ju An , Hyo Seok Lee , Eun Jeong Kim
IPC分类号： H01L21/31
CPC分类号： H01L21/31695 , C08B37/0012 , C08L83/04 , C09D105/16 , C09D183/02 , H01L21/02126 , H01L21/02203 , H01L21/02208 , H01L21/02282 , H01L21/02337
摘要： A reactive cyclodextrin derivative or a reactive glucose derivative is used as a template derivative for forming an ultra-low dielectric layer. A layer is formed of the reactive cyclodextrin derivative or the reactive glucose derivative capped with Si—H and then cured in an atmosphere of hydrogen peroxide to form the ultra-low dielectric layer.
摘要翻译：使用反应性环糊精衍生物或反应性葡萄糖衍生物作为形成超低介电层的模板衍生物。由反应性环糊精衍生物或用Si-H封端的反应性葡萄糖衍生物形成层，然后在过氧化氢气氛中固化形成超低介电层。

6. 发明授权

US07563654B2 Method of manufacturing semiconductor device for formation of pin transistor 有权
标题翻译：用于形成pin晶体管的半导体器件的制造方法
公开(公告)号：US07563654B2
公开(公告)日：2009-07-21
申请号：US11647759
申请日：2006-12-29
申请人： Dong Sun Sheen , Seok Pyo Song , Sang Tae Ahn , Hyeon Ju An , Hyun Chul Sohn
发明人： Dong Sun Sheen , Seok Pyo Song , Sang Tae Ahn , Hyeon Ju An , Hyun Chul Sohn
IPC分类号： H01L21/335
CPC分类号： H01L27/0886 , H01L27/1214
摘要： A method for manufacturing a semiconductor device is disclosed. The method includes the steps of defining a trench into a field region of a semiconductor substrate having an active region and the field region; partially filing the trench with a flowable insulation layer; completely filling the trench with an isolation structure by depositing a close-packed insulation layer on the flowable insulation layer in the trench; etching through a portion of the close-packed insulation layer and etching into a partial thickness of the flowable insulation layer of the insulation structure to expose a portion of the active region; cleaning the resultant substrate having the active region relatively projected; forming spacers on etched portions of the flowable insulation layer where bowing occurs during the cleaning step; and forming gates on the active region and the insulation structure to border the exposed portion of the active region.
摘要翻译：公开了一种制造半导体器件的方法。该方法包括以下步骤：将沟槽定义为具有有源区域和场区域的半导体衬底的场区域; 用可流动的绝缘层部分地填充沟槽; 通过在沟槽中的可流动绝缘层上沉积紧密堆积的绝缘层，通过隔离结构完全填充沟槽; 蚀刻通过所述紧密封装绝缘层的一部分并蚀刻成所述绝缘结构的可流动绝缘层的部分厚度以暴露所述有源区的一部分; 清洁具有相对投影的活性区域的所得基材; 在清洁步骤中发生弯曲的可流动绝缘层的蚀刻部分上形成间隔物; 以及在所述有源区和所述绝缘结构上形成栅极以与所述有源区的所述暴露部分相接触。

7. 发明授权

US06949447B2 Method for fabricating isolation layer in semiconductor device 失效
标题翻译：在半导体器件中制造隔离层的方法
公开(公告)号：US06949447B2
公开(公告)日：2005-09-27
申请号：US10738399
申请日：2003-12-17
申请人： Sang Tae Ahn , Sung Woong Chung , Hyun Chul Sohn
发明人： Sang Tae Ahn , Sung Woong Chung , Hyun Chul Sohn
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224
摘要： A method for fabricating an isolation layer in a semiconductor device is disclosed. The disclosed method comprises steps of: forming a trench on a semiconductor substrate; forming a flowing insulating layer within the trench; making the insulating layer precise; and forming a precise insulating layer over an upper surface of the whole structure on which the flowing insulating layer is formed. According to the method of fabricating an isolation layer in a semiconductor device, occurrence of fine pores at adjacent active regions of sidewalls in a trench can be prevented.
摘要翻译：公开了一种在半导体器件中制造隔离层的方法。所公开的方法包括以下步骤：在半导体衬底上形成沟槽; 在沟槽内形成流动的绝缘层; 使绝缘层精确; 并在其上形成有流动绝缘层的整个结构的上表面上形成精确的绝缘层。根据在半导体器件中制造隔离层的方法，可以防止在沟槽中的侧壁的相邻有源区产生细孔。

8. 发明授权

US08530330B2 Method for manufacturing a semiconductor device capable of preventing the decrease of the width of an active region 有权
标题翻译：一种能够防止活性区域的宽度减小的半导体装置的制造方法
公开(公告)号：US08530330B2
公开(公告)日：2013-09-10
申请号：US12100455
申请日：2008-04-10
申请人： Sang Tae Ahn , Ja Chun Ku , Eun Jeong Kim , Wan Soo Kim
发明人： Sang Tae Ahn , Ja Chun Ku , Eun Jeong Kim , Wan Soo Kim
IPC分类号： H01L21/76
CPC分类号： H01L21/823481 , H01L21/76224
摘要： A method for manufacturing a semiconductor device that can prevent the loss of an isolation structure and that can also stably form epi-silicon layers is described. The method for manufacturing a semiconductor device includes defining trenches in a semiconductor substrate having active regions and isolation regions. The trenches are partially filled with a first insulation layer. An etch protection layer is formed on the surfaces of the trenches that are filled with the first insulation layer. A second insulation layer is filled in the trenches formed with the etch protection layer to form an isolation structure in the isolation regions of the semiconductor substrate. Finally, portions of the active regions of the semiconductor substrate are recessed such that the isolation structure has a height higher than the active regions of the semiconductor substrate.
摘要翻译：描述了可以防止隔离结构的损失并且还可以稳定地形成外延硅层的半导体器件的制造方法。半导体器件的制造方法包括在具有有源区和隔离区的半导体衬底中限定沟槽。沟槽部分地填充有第一绝缘层。在填充有第一绝缘层的沟槽的表面上形成蚀刻保护层。在由蚀刻保护层形成的沟槽中填充第二绝缘层，以在半导体衬底的隔离区域中形成隔离结构。最后，半导体衬底的有源区的部分被凹入，使得隔离结构的高度高于半导体衬底的有源区。

9. 发明授权

US07763523B2 Method for forming device isolation structure of semiconductor device using annealing steps to anneal flowable insulation layer 失效
标题翻译：使用退火步骤对可流动绝缘层进行退火的半导体器件的器件隔离结构的方法
公开(公告)号：US07763523B2
公开(公告)日：2010-07-27
申请号：US12045073
申请日：2008-03-10
申请人： Sang Tae Ahn , Ja Chun Ku , Eun Jeong Kim
发明人： Sang Tae Ahn , Ja Chun Ku , Eun Jeong Kim
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , H01L21/0206 , H01L21/02164 , H01L21/02222 , H01L21/02282 , H01L21/02318 , H01L21/02337 , H01L21/3125 , H01L21/316 , H01L21/76227
摘要： A method for forming a device isolation structure of a semiconductor device using at least three annealing steps to anneal a flowable insulation layer is presented. The method includes the steps of forming a hard mask pattern on a semiconductor substrate having active regions exposing a device isolation region of the semiconductor substrate; etching the device isolation region of the semiconductor substrate exposed through the hard mask pattern, and therein forming a trench; forming a flowable insulation layer to fill a trench; first annealing the flowable insulation layer at least three times; second annealing the first annealed flowable insulation layer; removing the second annealed flowable insulation layer until the hard mask pattern is exposed; and removing the exposed hard mask pattern.
摘要翻译：提出了使用至少三个退火步骤形成半导体器件的器件隔离结构以退火可流动绝缘层的方法。该方法包括以下步骤：在具有暴露半导体衬底的器件隔离区域的有源区的半导体衬底上形成硬掩模图案; 蚀刻通过硬掩模图案曝光的半导体衬底的器件隔离区，并且其中形成沟槽; 形成可流动的绝缘层以填充沟槽; 首先将可流动绝缘层退火至少三次; 对所述第一退火可流动绝缘层进行第二退火; 去除所述第二退火的可流动绝缘层，直到所述硬掩模图案被暴露; 并去除暴露的硬掩模图案。

10. 发明授权

US07687371B2 Method of forming isolation structure of semiconductor device for preventing excessive loss during recess gate formation 失效
标题翻译：形成半导体器件的隔离结构的方法，用于防止在凹陷栅极形成期间的过度损耗
公开(公告)号：US07687371B2
公开(公告)日：2010-03-30
申请号：US12243133
申请日：2008-10-01
申请人： Dong Sun Sheen , Seok Pyo Song , Sang Tae Ahn , Hyeon Ju An
发明人： Dong Sun Sheen , Seok Pyo Song , Sang Tae Ahn , Hyeon Ju An
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： An isolation structure of a semiconductor device is formed by forming a hard mask layer on a semiconductor substrate having active and field regions to expose the field region. A trench is defined by etching the exposed field region of the semiconductor substrate using the hard mask as an etch mask. An SOG layer is formed in the trench partially filling the trench. An amorphous aluminum oxide layer is formed on the resultant substrate including the SOG layer. An HDP layer is formed on the amorphous aluminum oxide layer to completely fill the trench. The HDP layer and the amorphous aluminum oxide layer are subjected to CMP to expose the hard mask. The hard mask and portions of the amorphous aluminum oxide layer that are formed on the HDP layer are removed. The amorphous aluminum oxide layer is crystallized.
摘要翻译：半导体器件的隔离结构通过在具有活性和场区域的半导体衬底上形成硬掩模层以暴露场区而形成。通过使用硬掩模作为蚀刻掩模蚀刻半导体衬底的曝光场区来限定沟槽。 SOG层形成在部分填充沟槽的沟槽中。在包含SOG层的所得基板上形成无定形氧化铝层。在无定形氧化铝层上形成HDP层以完全填充沟槽。对HDP层和无定形氧化铝层进行CMP以暴露硬掩模。去除形成在HDP层上的硬掩模和无定形氧化铝层的部分。无定形氧化铝层结晶。

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