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1. 发明授权

US06656378B2 Piezoelectric ceramic composition reducing leakage current and piezoelectric device using the same 失效
标题翻译：压电陶瓷组合物减少泄漏电流和使用其的压电器件
公开(公告)号：US06656378B2
公开(公告)日：2003-12-02
申请号：US10067814
申请日：2002-02-08
申请人： Sang Koo Kwon , Kang Heon Hur , Jong Kuk Hong , Dong Hwan Seo
发明人： Sang Koo Kwon , Kang Heon Hur , Jong Kuk Hong , Dong Hwan Seo
IPC分类号： H01L41187
CPC分类号： C04B35/493 , C04B2235/3241 , C04B2235/3249 , C04B2235/3258 , C04B2235/3267 , C04B2235/3275 , C04B2235/3296 , H01L41/1876
摘要： Disclosed is a piezoelectric ceramic composition comprising a PZT piezoelectric composition, a B-site of which is substituted with a certain material, and chromium oxide, and a piezoelectric device using the piezoelectric ceramic composition. The piezoelectric ceramic composition has good heat resistance and frequency stability, and reduces a leakage current. There is provided the piezoelectric ceramic composition comprising a main component expressed by Pb[(Co1/2W1/2)xTi1−x−yZry]O3 (wherein, 0.001≦x≦0.04, and 0.35 ≦y≦0.55), Cr2O3 in an amount of 0.01 to 2 wt %, MnO2 in an amount of 0.1 to 0.5 wt %, and an additive in an amount of 0.01 to 2.0 wt %, based on the total weight of the piezoelectric ceramic composition, in which the additive is selected from the group consisting of CoO, MgO, ZnO, Al2O3, Fe2O3, Sb2O3, SnO2, CeO2, Nb2O5, V2O5 and WO3, and mixtures thereof. The piezoelectric ceramic composition satisfies piezoelectric properties such as kp and Qm needed for a piezoelectric material, and is 320° C. or higher in phase transition temperature, ±30 ppm/° C. in TCF, and 0.1% or less in oscillation frequency change after reflow; and the piezoelectric ceramic composition also has good piezoelectric properties such that the leakage current is reduced.
摘要翻译：本发明公开了一种压电陶瓷组合物和使用该压电陶瓷组合物的压电装置，其中PZT压电组合物的B部位用某种材料代替，氧化铬。压电陶瓷组合物具有良好的耐热性和频率稳定性，并且减小了漏电流。提供了包含由Pb [（Co1 / 2W1 / 2）xTi1-x-yZry] O3（其中0.001≤x≤0.04,0.35≤Y＆LE; 0.55）表示的主要成分的压电陶瓷组合物， 0.01〜2.0重量％的MnO 2，0.1〜0.5重量％的MnO 2，0.01〜2.0重量％的添加剂，相对于压电陶瓷组合物的总重量，添加剂为选自CoO，MgO，ZnO，Al2O3，Fe2O3，Sb2O3，SnO2，CeO2，Nb2O5，V2O5和WO3，以及它们的混合物。压电陶瓷组合物满足压电材料所需的压电特性如kp和Qm，在TCF中相变温度为320℃或更高，±30ppm /℃，振荡频率变化为0.1％以下回流后并且压电陶瓷组合物也具有良好的压电性能，使得泄漏电流降低。

2. 发明授权

US06683014B2 Piezoelectric ceramic composition and piezoelectric ceramic device using the same 失效
标题翻译：压电陶瓷组合物和使用其的压电陶瓷装置
公开(公告)号：US06683014B2
公开(公告)日：2004-01-27
申请号：US10206983
申请日：2002-07-30
申请人： Dong Hwan Seo , Kang Heon Hur , Jong Kuk Hong , Sang Koo Kwon
发明人： Dong Hwan Seo , Kang Heon Hur , Jong Kuk Hong , Sang Koo Kwon
IPC分类号： H01L4118
CPC分类号： C04B35/472 , C04B2235/3227 , C04B2235/3234 , C04B2235/3267 , C04B2235/3284 , C04B2235/3296 , C04B2235/5436 , C04B2235/5445 , H01L41/187
摘要： The present invention provides a piezoelectric ceramic composition having the formula: {[Pb(1−1.5x)±(0˜0.2)Lax][Ti(1−y−z)MnyCuz]O3} which meets the requirements: 0.02
摘要翻译：本发明提供一种具有以下结构的压电陶瓷组合物：符合要求的{[Pb（1-1.5×）±（0〜0.2）Lax] [Ti（1-yz）MnyCuz] O 3}：0.02

3. 发明申请

US20110097553A1 TRENCH SUBSTRATE AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译： TRENCH基板及其制造方法
公开(公告)号：US20110097553A1
公开(公告)日：2011-04-28
申请号：US12631624
申请日：2009-12-04
申请人： Jong Kuk Hong , Soon Jin Cho , Sun Uk Hwang
发明人： Jong Kuk Hong , Soon Jin Cho , Sun Uk Hwang
IPC分类号： H05K1/03 , B32B3/30 , H05K3/00
CPC分类号： H05K3/0032 , H05K1/036 , H05K1/0366 , H05K3/045 , H05K3/107 , H05K2201/0209 , H05K2201/029 , Y10T428/2462
摘要： Disclosed is a trench substrate, which includes a first insulating layer having trenches formed therein, a second insulating layer disposed on a lower surface of the first insulating layer and having laser processability inferior to that of the first insulating layer, and a negative pattern formed in the trenches, and in which the second insulating layer having laser processability inferior to that of the first insulating layer functions as a stopper, so that the trenches having the same shape are formed in the first insulating layer, thus enabling the formation of a fine and uniform circuit pattern. A method of fabricating the trench substrate is also provided.
摘要翻译：公开了一种沟槽衬底，其包括其中形成有沟槽的第一绝缘层，设置在第一绝缘层的下表面上并且具有劣于第一绝缘层的激光加工性的第二绝缘层，以及形成在沟槽，其中具有劣于第一绝缘层的激光加工性的第二绝缘层用作止动件，使得具有相同形状的沟槽形成在第一绝缘层中，从而能够形成微细的和均匀的电路图案。还提供了制造沟槽衬底的方法。

4. 发明授权

US07277005B2 Printed circuit board including embedded resistor and method of fabricating the same 有权
标题翻译：包含嵌入式电阻的印刷电路板及其制造方法
公开(公告)号：US07277005B2
公开(公告)日：2007-10-02
申请号：US11022074
申请日：2004-12-22
申请人： Myung Sam Kang , Chang Sup Ryu , Jong Kuk Hong
发明人： Myung Sam Kang , Chang Sup Ryu , Jong Kuk Hong
IPC分类号： H01C1/012
CPC分类号： H01C7/003 , H01C17/065 , H01C17/0652 , H01L2224/05001 , H01L2224/05023 , H01L2224/05568 , H01L2224/16 , H01L2924/01019 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H05K1/167 , H05K3/0047 , H05K3/005 , H05K3/4069 , H05K3/42 , H05K3/429 , H05K3/4652 , H05K2201/09509 , H05K2201/09645 , H05K2203/1476
摘要： Disclosed is a PCB including an embedded resistor and a method of fabricating the same. The PCB includes a plurality of circuit layers in which circuit patterns are formed. A plurality of insulating layers is each interposed between the circuit layers. The embedded resistor is made of a resistive material and received in a receiving hole formed in the plurality of circuit layers and the plurality of insulating layers such that walls defining the receiving hole extends from one of the circuit layers to another circuit layer. The receiving hole has a closed section, and a conductive material is plated on the opposite walls of the walls defining the receiving hole.
摘要翻译：公开了一种包括嵌入式电阻器的PCB及其制造方法。 PCB包括形成电路图案的多个电路层。在电路层之间分别插入多个绝缘层。嵌入式电阻器由电阻材料制成并且被容纳在形成在多个电路层和多个绝缘层中的接收孔中，使得限定接收孔的壁从电路层之一延伸到另一个电路层。接收孔具有闭合部分，并且导电材料被电镀在限定接收孔的壁的相对壁上。

5. 发明申请

US20100096177A1 Coreless substrate having filled via pad and method of manufacturing the same 失效
标题翻译：具有填充通孔垫的无芯衬底及其制造方法
公开(公告)号：US20100096177A1
公开(公告)日：2010-04-22
申请号：US12320284
申请日：2009-01-22
申请人： Seok Kyu Lee , Soon OH Jung , Jong Kuk Hong , Soon Jin Cho
发明人： Seok Kyu Lee , Soon OH Jung , Jong Kuk Hong , Soon Jin Cho
IPC分类号： H05K1/11 , H05K3/42
CPC分类号： H05K3/00 , H05K1/113 , H05K3/0052 , H05K3/007 , H05K3/4007 , H05K3/426 , H05K3/4682 , H05K2201/0367 , H05K2201/09563 , H05K2201/096 , H05K2203/0156 , H05K2203/054 , H05K2203/1572
摘要： Disclosed herein is a coreless substrate having filled via pads and a method of manufacturing the same. Insulating layers are formed on both sides of a build-up layer, and via-pads are embedded in the insulating layers such that the via-pads are flush with the insulating layers. The via pads are not separated from a substrate, and thus reliability of the pads is increased. Flatness of bumps is increased, and thus bonding of flip chips becomes easy.
摘要翻译：本文公开了具有填充通孔焊盘的无芯基板及其制造方法。绝缘层形成在堆积层的两侧，并且通孔焊盘嵌入在绝缘层中，使得通孔焊盘与绝缘层齐平。通孔焊盘不与衬底分离，因此焊盘的可靠性增加。凸起的平坦度增加，因此倒装芯片的结合变得容易。

6. 发明申请

US20080110669A1 Printed circuit board having embedded resistors and method of manufacturing the same 审中-公开
标题翻译：具有嵌入式电阻器的印刷电路板及其制造方法
公开(公告)号：US20080110669A1
公开(公告)日：2008-05-15
申请号：US11976760
申请日：2007-10-26
申请人： Hwa Sun Park , Tae Eui Kim , Jong Kuk Hong , Sang Jin Baek , Hong Won Kim , Jin Soo Jeong
发明人： Hwa Sun Park , Tae Eui Kim , Jong Kuk Hong , Sang Jin Baek , Hong Won Kim , Jin Soo Jeong
IPC分类号： H05K1/16 , H05K3/30
CPC分类号： H05K1/167 , H05K1/095 , H05K3/4069 , H05K3/4644 , H05K2201/09481 , Y10T29/435 , Y10T29/49128 , Y10T29/4913 , Y10T29/49155 , Y10T29/49156 , Y10T29/49165
摘要： Disclosed herein is a Printed Circuit Board (PCB) having embedded resistors and a method of manufacturing the same, in which contact pads are formed by filling via holes formed on electrode pads with oxidation-resistant conductive material, and resistors are formed on the contact pads. Accordingly, erosion that occurs between the electrode pads and the resistors can be prevented using the contact pads made of oxidation-resistant conductive material, and connections between circuits also can be realized. Furthermore, resistors are formed on a flat plane without any difference in height, attributable to the electrode pads, and thus differences between the resistance values of the built-in resistors can be greatly reduced.
摘要翻译：本文公开了具有嵌入式电阻器的印刷电路板（PCB）及其制造方法，其中通过在电极焊盘上形成的具有抗氧化导电材料的孔填充形成接触焊盘，并且在接触焊盘上形成电阻器。因此，可以使用由抗氧化导电材料制成的接触垫来防止在电极焊盘和电阻器之间发生的侵蚀，并且还可以实现电路之间的连接。此外，电阻器形成在平面上，由于电极焊盘而在高度上没有任何差异，因此可以大大降低内置电阻器的电阻值之间的差异。

7. 发明授权

US08445790B2 Coreless substrate having filled via pad and method of manufacturing the same 失效
标题翻译：具有填充通孔垫的无芯衬底及其制造方法
公开(公告)号：US08445790B2
公开(公告)日：2013-05-21
申请号：US12320284
申请日：2009-01-22
申请人： Seok Kyu Lee , Soon Oh Jung , Jong Kuk Hong , Soon Jin Cho
发明人： Seok Kyu Lee , Soon Oh Jung , Jong Kuk Hong , Soon Jin Cho
IPC分类号： H05K1/11
CPC分类号： H05K3/00 , H05K1/113 , H05K3/0052 , H05K3/007 , H05K3/4007 , H05K3/426 , H05K3/4682 , H05K2201/0367 , H05K2201/09563 , H05K2201/096 , H05K2203/0156 , H05K2203/054 , H05K2203/1572
摘要： Disclosed herein is a coreless substrate having filled via pads and a method of manufacturing the same. Insulating layers are formed on both sides of a build-up layer, and via-pads are embedded in the insulating layers such that the via-pads are flush with the insulating layers. The via pads are not separated from a substrate, and thus reliability of the pads is increased. Flatness of bumps is increased, and thus bonding of flip chips becomes easy.
摘要翻译：本文公开了具有填充通孔焊盘的无芯基板及其制造方法。绝缘层形成在堆积层的两侧，并且通孔焊盘嵌入在绝缘层中，使得通孔焊盘与绝缘层齐平。通孔焊盘不与衬底分离，因此焊盘的可靠性增加。凸起的平坦度增加，因此倒装芯片的结合变得容易。

8. 发明申请

US20130119540A1 SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体封装及其制造方法
公开(公告)号：US20130119540A1
公开(公告)日：2013-05-16
申请号：US13362048
申请日：2012-01-31
申请人： Jong Kuk Hong , Keung Jin Sohn , Jung Hwan Park
发明人： Jong Kuk Hong , Keung Jin Sohn , Jung Hwan Park
IPC分类号： H01L23/498 , H01L21/50 , H01L23/48
CPC分类号： H01L21/50 , H01L23/3121 , H01L23/48 , H01L23/498 , H01L23/49816 , H01L23/562 , H01L24/16 , H01L24/73 , H01L24/81 , H01L25/0657 , H01L2224/16237 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48228 , H01L2224/73204 , H01L2224/73265 , H01L2224/81815 , H01L2225/0651 , H01L2225/06568 , H01L2924/15311 , H01L2924/3511 , H01L2924/00014 , H01L2224/16225 , H01L2924/00 , H01L2924/00012
摘要： Disclosed herein are a semiconductor package and a method for manufacturing the same. The method includes preparing a substrate having one surface and the other surface; mounting a semiconductor device mounted on one surface of the substrate; forming external connection terminals on the other surface of the substrate; forming a warpage preventing layer formed on one surface of the substrate or the other surface of the substrate; and performing a reflow process on the substrate.
摘要翻译：本文公开了一种半导体封装及其制造方法。该方法包括制备具有一个表面和另一个表面的基底; 安装安装在所述基板的一个表面上的半导体器件; 在所述基板的另一个表面上形成外部连接端子; 形成在所述基板或所述基板的另一表面的一个表面上形成的翘曲防止层; 并在衬底上进行回流处理。

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