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1. 发明授权

US6157590A Solid state memory having a latch circuit 有权
标题翻译：具有锁存电路的固态存储器
公开(公告)号：US6157590A
公开(公告)日：2000-12-05
申请号：US404143
申请日：1999-09-27
申请人： Sang Hoan Chang
发明人： Sang Hoan Chang
IPC分类号： G11C16/06 , G11C5/06 , G11C8/00
CPC分类号： G11C8/00 , G11C5/066
摘要： A solid state memory according to the present invention comprises a plurality of memory chips; a confirmation circuit to confirm an input address by comparing said input address to each address latched to a latch circuit; a common serial bus for transmitting commands, addresses and data between the memory chips and the confirmation circuit; and a printed circuit board on which the memory chips and the confirmation circuit are mounted.
摘要翻译：根据本发明的固态存储器包括多个存储器芯片; 确认电路，用于通过将所述输入地址与锁存到锁存电路的每个地址进行比较来确认输入地址; 用于在存储器芯片和确认电路之间发送命令，地址和数据的公共串行总线; 以及安装有存储芯片和确认电路的印刷电路板。

2. 发明申请

US20120087183A1 METHODS OF OPERATING PRAMS USING INITIAL PROGRAMMED RESISTANCES AND PRAMS USING THE SAME 有权
标题翻译：使用初始编程电阻和PRAMS操作的方法
公开(公告)号：US20120087183A1
公开(公告)日：2012-04-12
申请号：US13168553
申请日：2011-06-24
申请人： Sang Hoan Chang
发明人： Sang Hoan Chang
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C7/04 , G11C13/0007 , G11C13/0033
摘要： A method of operating a PRAM device can be provided by reading a PRAM reference cell to determine an initial programmed resistance of the PRAM reference cell and determining whether the initial programmed resistance has been reduced to below a predetermined reference threshold resistance.
摘要翻译：可以通过读取PRAM参考单元来确定PRAM参考单元的初始编程电阻并确定初始编程电阻是否已经降低到低于预定参考阈值电阻，来提供操作PRAM器件的方法。

3. 发明授权

US06391665B1 Method of monitoring a source contact in a flash memory 有权
标题翻译：监视闪存中的源触点的方法
公开(公告)号：US06391665B1
公开(公告)日：2002-05-21
申请号：US09722112
申请日：2000-11-27
申请人： Sang Hoan Chang , Ki Seog Kim , Jin Shin , Keun Woo Lee
发明人： Sang Hoan Chang , Ki Seog Kim , Jin Shin , Keun Woo Lee
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , G11C16/04 , G11C29/50 , G11C29/50008 , G11C2029/5006 , H01L21/76895 , H01L27/115
摘要： There is disclosed a method of monitoring a source contact in a flash memory by which whether a source contact having a narrow contact area contacts or not can be easily monitored using over-erase cell characteristic in a flash cell, in a flash memory device in which a source line is formed by a local interconnection method. In the present invention, in order to monitor a contact state at source contacts, the same voltage to the erase condition of a cell is applied to respective terminals (VG terminal, VD terminal, VS terminal and VSS terminal) wherein all the electrons existing at a floating gate in all the cells connected to the VS terminal and VSS terminal become turned on so that they can be over-erased. On the other hands, as electrons existing at the floating gate in two cells shared by any source contacts having a defect contact are not erased, the cells remain turn-off. In this state, if test voltages (VG=0V, VD
摘要翻译：公开了一种监视闪速存储器中的源极触点的方法，通过该闪光存储器中的源极触点可以容易地利用闪存单元中的过擦除单元特性来容易地监视具有窄接触区域的源极触点的触点，源线由本地互连方式形成。在本发明中，为了监测源极触点的接触状态，将与电池的擦除状态相同的电压施加到各个端子（VG端子，VD端子，VS端子和VSS端子），其中所有电子存在于连接到VS端子和VSS端子的所有单元中的浮动栅极变为导通，使得它们可能被过擦除。另一方面，由于存在于由具有缺陷接触的任何源极触点共享的两个电池中的浮动栅极处的电子不被擦除，所以电池保持关断。在这种状态下，如果施加了测试电压（VG = 0V，VD <5V，VS =浮动，VSS =接地），则在具有接触缺陷的部分中，从VD端子到VSS端子的电流断开，从而允许要监控的源触点的接触状态。

4. 发明授权

US06316313B1 Method of manufacturing a flash memory device 失效
标题翻译：制造闪存装置的方法
公开(公告)号：US06316313B1
公开(公告)日：2001-11-13
申请号：US09717002
申请日：2000-11-22
申请人： Sung Kee Park , Ki Seog Kim , Sang Hoan Chang , Keun Woo Lee
发明人： Sung Kee Park , Ki Seog Kim , Sang Hoan Chang , Keun Woo Lee
IPC分类号： H01L218247
CPC分类号： H01L27/112
摘要： There is disclosed a method of manufacturing a flash memory device. In order to solve the problems that a well resistance and a parasitic capacitance are great and the erase speed of a device is slow in case of the conventional flash memory device, the present invention forms a well region of a sector unit by use of a metal silicide layer and defines an unit cell by use of a ploysilicon layer. Thus, it can reduce the well resistance and the parasitic capacitance. Also, it can improve the operating speed of the device and can reduce the manufacturing cost by allowing the erase operation of a cell unit.
摘要翻译：公开了一种制造闪速存储器件的方法。为了解决现有的闪速存储器件的情况下阱电阻和寄生电容大的问题以及器件的擦除速度较慢的问题，本发明通过使用金属形成扇区单元的阱区硅化物层并且通过使用合金层来限定晶胞。因此，它可以降低阱电阻和寄生电容。此外，它可以提高装置的操作速度，并且可以通过允许单元单元的擦除操作来降低制造成本。

5. 发明授权

US09087220B2 Nonvolatile memory cell with authentication key storage 有权
标题翻译：具有认证密钥存储的非易失性存储单元
公开(公告)号：US09087220B2
公开(公告)日：2015-07-21
申请号：US13450578
申请日：2012-04-19
申请人： Sang Hoan Chang , Kwang Jin Lee
发明人： Sang Hoan Chang , Kwang Jin Lee
IPC分类号： G06F21/79
CPC分类号： G06F21/79 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2924/00014
摘要： A nonvolatile memory device includes a memory cell array configured to store an authentication key and authentication key configuration information in first and second pluralities of nonvolatile memory cells, along with data whose security is to be protected, and a control circuit controlling an operation of the memory cell array.
摘要翻译：非易失性存储器件包括：存储单元阵列，被配置为将第一和第二多个非易失性存储器单元中的认证密钥和认证密钥配置信息与安全性要保护的数据一起存储;以及控制电路，用于控制存储器的操作单元格阵列。

6. 发明授权

US08830724B2 Methods of operating PRAMS using initial programmed resistances and PRAMS using the same 有权
标题翻译：使用初始编程电阻运行PRAMS的方法和使用其的PRAMS
公开(公告)号：US08830724B2
公开(公告)日：2014-09-09
申请号：US13168553
申请日：2011-06-24
申请人： Sang Hoan Chang
发明人： Sang Hoan Chang
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C7/04 , G11C13/0007 , G11C13/0033
摘要： A method of operating a PRAM device includes reading a PRAM reference cell to determine an initial programmed resistance of the PRAM reference cell and determining whether the initial programmed resistance has been reduced to below a predetermined reference threshold resistance.
摘要翻译：一种操作PRAM设备的方法包括读取PRAM参考单元以确定PRAM参考单元的初始编程电阻并确定初始编程电阻是否已经降低到低于预定参考阈值电阻。

7. 发明申请

US20130014269A1 NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME 有权
标题翻译：非易失性存储器件和包括其的存储器系统
公开(公告)号：US20130014269A1
公开(公告)日：2013-01-10
申请号：US13450578
申请日：2012-04-19
申请人： Sang Hoan Chang , Kwang Jin Lee
发明人： Sang Hoan Chang , Kwang Jin Lee
IPC分类号： G06F21/00
CPC分类号： G06F21/79 , H01L2224/48091 , H01L2224/48227 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2924/00014
摘要： A nonvolatile memory device includes a memory cell array configured to store an authentication key and authentication key configuration information in first and second pluralities of nonvolatile memory cells, along with data whose security is to be protected, and a control circuit controlling an operation of the memory cell array.
摘要翻译：非易失性存储器件包括：存储单元阵列，被配置为将第一和第二多个非易失性存储器单元中的认证密钥和认证密钥配置信息与安全性要保护的数据一起存储;以及控制电路，用于控制存储器的操作单元格阵列。

8. 发明授权

US06304484B1 Multi-bit flash memory cell and programming method using the same 失效
标题翻译：多位闪存单元和编程方法使用相同
公开(公告)号：US06304484B1
公开(公告)日：2001-10-16
申请号：US09722111
申请日：2000-11-27
申请人： Jin Shin , Sang Hoan Chang , Seoung Ouk Choi , Keon Soo Shim
发明人： Jin Shin , Sang Hoan Chang , Seoung Ouk Choi , Keon Soo Shim
IPC分类号： G11C1604
CPC分类号： G11C16/0475 , G11C11/5621 , G11C11/5628 , G11C11/5671 , G11C16/0458 , G11C2211/5612 , H01L29/7887
摘要： There is disclosed a multi-bit flash memory cell and programming method using the same. In order to solve the problems that the size of a cell per unit is increased, reliability of a device is degraded due to a high operating voltage and a circuit necessary for driving the cell becomes complicated, the multi-bit flash memory cell and programming method using the same according to the present invention stores information of various states, by interchangeably programs a drain and a source in a cell array of virtual ground type, in a structure in which that two types of cells look like connected serially by doping a floating gate in a flash memory cell with two regions of a N type and a P to type.
摘要翻译：公开了一种使用其的多位闪存单元和编程方法。为了解决每单元的单元尺寸增加的问题，由于高工作电压，器件的可靠性降低，并且驱动单元所需的电路变得复杂，多位闪存单元和编程方法根据本发明，使用它们的信息通过可互换地编程虚拟接地型单元阵列中的漏极和源极的信息来存储各种状态的信息，其中两种类型的单元看起来通过掺杂浮置栅极串联连接在具有N型和P型的两个区域的闪存单元中。

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