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    • 4. 发明授权
    • Multi-tanh doublets using emitter resistors
    • 使用发射极电阻的多重双峰
    • US6087883A
    • 2000-07-11
    • US212089
    • 1998-12-15
    • Barrie Gilbert
    • Barrie Gilbert
    • G06F7/44
    • H03F3/45183H03F1/3211H03F3/211H03F3/45596H03F2203/45324H03F2203/45352H03F2203/45354H03F2203/45362H03F2203/45371H03F2203/45374
    • Multi-tanh cells constructed in accordance with the present invention provide improved input voltage range by utilizing resistors connected between the emitters of the transistors and the corresponding bias current sources. The resistor values and emitter area ratios are chosen to achieve substantially distortion-free transconductance functions over wide input voltage ranges. This improved input voltage range results in a corresponding improvement in dynamic range because the emitter resistances do not increase the noise significantly at low input voltage levels. In one embodiment, a separate resistor is connected in series with the emitter of each of the four doublet transistors. Another embodiment utilizes only a single bias current source and two emitter resistors to achieve better linearity and lower noise. To achieve higher effective emitter area ratios, an emitter follower scheme can be used to synthesize all or a portion of the area ratio. A series-connected version provides even wider input voltage range.
    • 根据本发明构造的多tanh电池通过利用连接在晶体管的发射极和相应的偏置电流源之间的电阻来提供改进的输入电压范围。 选择电阻值和发射极面积比以在宽输入电压范围内实现基本无畸变的跨导功能。 这种改进的输入电压范围导致动态范围的相应改善,因为在低输入电压电平下,发射极电阻不会显着增加噪声。 在一个实施例中,单独的电阻器与四个双晶体管中的每一个的发射极串联连接。 另一个实施例仅使用单个偏置电流源和两个发射极电阻来实现更好的线性度和更低的噪声。 为了实现更高的有效发射极面积比,可以使用射极跟随器方案来合成面积比的全部或一部分。 串联型号提供更宽的输入电压范围。
    • 9. 发明授权
    • Apparatus and method for correction of error caused by reverse saturation current mismatch
    • 用于校正由反饱和电流失配引起的误差的装置和方法
    • US07224227B1
    • 2007-05-29
    • US11035156
    • 2005-01-12
    • Ajay Kumar
    • Ajay Kumar
    • H03F3/45
    • H03F3/3432H03F1/30H03F3/4508H03F3/45596H03F2200/462
    • A buffer circuit is arranged for offset cancellation between an input voltage and a buffered voltage. The buffer circuit includes two bias current sources, two p-type transistors, and two n-type transistors. Further, the base-emitter voltages of the two p-type transistors and the two n-type transistors are arranged to form a translinear loop. The translinear loop is arranged to provide the buffered voltage from the input voltage. One of the bias sources is arranged to provide a bias current to one of the p-type transistors, and the other bias circuit is arranged to provide a bias current to one of the n-type transistors. One of the bias current circuits is arranged to actively sense the reverse saturation currents of the p-type transistors and the n-type transistors, and to provide its bias current so that the offset voltage between the input voltage and the buffered voltage is substantially cancelled.
    • 缓冲电路被布置用于输入电压和缓冲电压之间的偏移消除。 缓冲电路包括两个偏置电流源,两个p型晶体管和两个n型晶体管。 此外,两个p型晶体管和两个n型晶体管的基极 - 发射极电压被布置成形成跨线性环路。 跨导线圈被设置成从输入电压提供缓冲电压。 偏置源之一被布置成向p型晶体管之一提供偏置电流,并且另一偏置电路被布置为向n型晶体管中的一个提供偏置电流。 偏置电流电路之一被布置成主动地感测p型晶体管和n型晶体管的反向饱和电流,并提供其偏置电流,使得输入电压和缓冲电压之间的偏移电压被基本上取消 。