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1. 发明授权

US09576660B2 Low forming voltage non-volatile storage device 有权
标题翻译：低成型电压非易失性存储装置
公开(公告)号：US09576660B2
公开(公告)日：2017-02-21
申请号：US14996144
申请日：2016-01-14
申请人： SANDISK 3D LLC
发明人： Zhida Lan , Roy E. Scheuerlein , Tong Zhang , Kun Hou , Perumal Ratnam
IPC分类号： G11C13/00 , H01L45/00 , H01L27/24
CPC分类号： G11C13/0097 , G11C13/0002 , G11C13/0007 , G11C13/003 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0083 , G11C2213/32 , G11C2213/52 , G11C2213/71 , G11C2213/77 , H01L27/2454 , H01L27/249 , H01L45/08 , H01L45/1226 , H01L45/1253 , H01L45/145 , H01L45/146
摘要： A three-dimensional array of memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The memory elements can be set to a low resistance state and reset to a high resistance state during standard operation by biasing appropriate voltages on the word lines and bit lines. Prior to standard operation, the memory elements undergo a forming operation, during which current through the bit lines is limited. A forming voltage is applied to the memory elements during forming with a polarity such that a higher voltage is applied to anodes and a lower voltage to cathodes.
摘要翻译：存储元件的三维阵列，其响应于在其上施加的电压差而可逆地改变电导水平。存储器元件可以被设置为低电阻状态，并且在标准操作期间通过偏置字线和位线上的适当电压而复位到高电阻状态。在标准操作之前，存储元件进行成形操作，在此期间，通过位线的电流被限制。在成形期间，将形成电压施加到存储元件，其极性使得较高的电压被施加到阳极，而较低的电压施加到阴极。

2. 发明授权

US09054308B1 Plasma reduction method for modifying metal oxide stoichiometry in ReRAM 有权
标题翻译：用于修改ReRAM中金属氧化物化学计量的等离子体还原法
公开(公告)号：US09054308B1
公开(公告)日：2015-06-09
申请号：US14196647
申请日：2014-03-04
申请人： SanDisk 3D LLC
发明人： Tong Zhang , Timothy James Minvielle , Chu-Chen Fu , Wipul Jayasekara
IPC分类号： H01L21/00 , H01L21/16 , H01L47/00 , H01L45/00
CPC分类号： H01L45/1641 , H01L27/249 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/1616
摘要： A fabrication process for a resistance-switching memory cell uses metal oxide as a resistance-switching material. A metal oxide film having an initial stoichiometry is deposited on an electrode using atomic layer deposition. A changed stoichiometry is provided for a portion of the metal oxide film using a plasma reduction process, separate from the atomic layer deposition, and another electrode is formed adjacent to the changed stoichiometry portion. The film deposition and the plasma reduction can be performed in separate chambers where conditions such as temperature are optimized. The metal oxide film may be deposited on a vertical sidewall in a vertical bit line 3d memory device. Optionally, the mean free path of hydrogen ions during the plasma reduction process is adjusted to increase the uniformity of the vertical metal oxide film. The adjustment can involve factors such as RF power, pressure and a bias of the wafer.
摘要翻译：电阻切换存储单元的制造工艺使用金属氧化物作为电阻切换材料。使用原子层沉积将具有初始化学计量的金属氧化物膜沉积在电极上。使用与原子层沉积分离的等离子体还原法，对于金属氧化物膜的一部分提供了改变的化学计量，并且与改变的化学计量部分相邻地形成另一电极。膜沉积和等离子体还原可以在诸如温度等条件优化的分离室中进行。金属氧化物膜可以沉积在垂直位线3d存储器件中的垂直侧壁上。可选地，调整等离子体还原过程期间氢离子的平均自由程，以增加垂直金属氧化物膜的均匀性。该调整可以涉及诸如RF功率，压力和晶片偏置的因素。

3. 发明申请

US20130234099A1 NON-VOLATILE STORAGE WITH METAL OXIDE SWITCHING ELEMENT AND METHODS FOR FABRICATING THE SAME 有权
标题翻译：具有金属氧化物切换元件的非挥发性储存及其制造方法
公开(公告)号：US20130234099A1
公开(公告)日：2013-09-12
申请号：US13848603
申请日：2013-03-21
申请人： SANDISK 3D LLC
发明人： Deepak C. Sekar , Franz Kreupl , Raghuveer S. Makala , Peter Rabkin , Chu-Chen Fu , Tong Zhang
IPC分类号： H01L45/00
CPC分类号： H01L45/146 , G11C13/0007 , G11C2213/35 , G11C2213/71 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/08 , H01L45/1233 , H01L45/145 , H01L45/1641 , H01L45/1675
摘要： Non-volatile storage elements having a reversible resistivity-switching element and techniques for fabricating the same are disclosed herein. The reversible resistivity-switching element may be formed by depositing an oxygen diffusion resistant material (e.g., heavily doped Si, W, WN) over the top electrode. A trap passivation material (e.g., fluorine, nitrogen, hydrogen, deuterium) may be incorporated into one or more of the bottom electrode, a metal oxide region, or the top electrode of the reversible resistivity-switching element. One embodiment includes a reversible resistivity-switching element having a bi-layer capping layer between the metal oxide and the top electrode. Fabricating the device may include depositing (un-reacted) titanium and depositing titanium oxide in situ without air break. One embodiment includes incorporating titanium into the metal oxide of the reversible resistivity-switching element. The titanium might be implanted into the metal oxide while depositing the metal oxide, or after deposition of the metal oxide.
摘要翻译：本文公开了具有可逆电阻率开关元件的非易失性存储元件及其制造技术。可逆电阻率开关元件可以通过在顶部电极上沉积防氧扩散材料（例如，重掺杂的Si，W，WN）来形成。可以将陷阱钝化材料（例如，氟，氮，氢，氘）并入到可逆电阻率切换元件的底部电极，金属氧化物区域或顶部电极中的一个或多个中。一个实施例包括在金属氧化物和顶部电极之间具有双层覆盖层的可逆电阻率开关元件。制造该器件可以包括沉积（未反应的）钛并原位沉积二氧化钛而没有空气破裂。一个实施例包括将钛结合到可逆电阻率开关元件的金属氧化物中。可以在沉积金属氧化物的同时或在沉积金属氧化物之后将钛注入金属氧化物中。

4. 发明申请

US20130170283A1 LOW FORMING VOLTAGE NON-VOLATILE STORAGE DEVICE 有权
标题翻译：低成型电压非易失存储器件
公开(公告)号：US20130170283A1
公开(公告)日：2013-07-04
申请号：US13709349
申请日：2012-12-10
申请人： Sandisk 3D LLC
发明人： Zhida Lan , Roy E. Scheuerlein , Tong Zhang , Kun Hou , Perumal Ratnam
IPC分类号： G11C13/00
CPC分类号： G11C13/0097 , G11C13/0002 , G11C13/0007 , G11C13/003 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0083 , G11C2213/32 , G11C2213/52 , G11C2213/71 , G11C2213/77 , H01L27/2454 , H01L27/249 , H01L45/08 , H01L45/1226 , H01L45/1253 , H01L45/145 , H01L45/146
摘要： A three-dimensional array of memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are provided across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. The memory elements can be set to a low resistance state and reset to a high resistance state during standard operation by biasing appropriate voltages on the word lines and bit lines. Prior to standard operation, the memory elements undergo a forming operation, during which current through the bit lines is limited. A forming voltage is applied to the memory elements during forming with a polarity such that the bit line acts as a cathode and the word line acts as an anode, with the cathode having a lower electron injection energy barrier to the switching material than the anode.
摘要翻译：存储元件的三维阵列，其响应于在其上施加的电压差而可逆地改变电导水平。存储元件设置在跨越半导体衬底的不同距离上的多个平面中。所有平面的存储元件所连接的位线从衬底垂直定向并穿过多个平面。存储器元件可以被设置为低电阻状态，并且在标准操作期间通过偏置字线和位线上的适当电压而复位到高电阻状态。在标准操作之前，存储元件进行成形操作，在此期间，通过位线的电流受到限制。在具有极性的成形期间，将形成电压施加到存储元件，使得位线用作阴极，并且字线用作阳极，阴极与开关材料相比具有较低的电子注入能量势垒。

5. 发明申请

US20160133325A1 LOW FORMING VOLTAGE NON-VOLATILE STORAGE DEVICE 有权
标题翻译：低成型电压非易失存储器件
公开(公告)号：US20160133325A1
公开(公告)日：2016-05-12
申请号：US14996144
申请日：2016-01-14
申请人： SANDISK 3D LLC
发明人： Zhida Lan , Roy E. Scheuerlein , Tong Zhang , Kun Hou , Perumal Ratnam
IPC分类号： G11C13/00
CPC分类号： G11C13/0097 , G11C13/0002 , G11C13/0007 , G11C13/003 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0083 , G11C2213/32 , G11C2213/52 , G11C2213/71 , G11C2213/77 , H01L27/2454 , H01L27/249 , H01L45/08 , H01L45/1226 , H01L45/1253 , H01L45/145 , H01L45/146
摘要： A three-dimensional array of memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The memory elements can be set to a low resistance state and reset to a high resistance state during standard operation by biasing appropriate voltages on the word lines and bit lines. Prior to standard operation, the memory elements undergo a forming operation, during which current through the bit lines is limited. A forming voltage is applied to the memory elements during forming with a polarity such that a higher voltage is applied to anodes and a lower voltage to cathodes.
摘要翻译：存储元件的三维阵列，其响应于在其上施加的电压差而可逆地改变电导水平。存储器元件可以被设置为低电阻状态，并且在标准操作期间通过偏置字线和位线上的适当电压而复位到高电阻状态。在标准操作之前，存储元件进行成形操作，在此期间，通过位线的电流受到限制。在成形期间，将形成电压施加到存储元件，其极性使得较高的电压被施加到阳极，而较低的电压施加到阴极。

6. 发明授权

US09269425B2 Low forming voltage non-volatile storage device 有权
标题翻译：低成型电压非易失性存储装置
公开(公告)号：US09269425B2
公开(公告)日：2016-02-23
申请号：US13709349
申请日：2012-12-10
申请人： SANDISK 3D LLC
发明人： Zhida Lan , Roy E. Scheuerlein , Tong Zhang , Kun Hou , Perumal Ratnam
IPC分类号： G11C13/00 , H01L45/00 , H01L27/24
CPC分类号： G11C13/0097 , G11C13/0002 , G11C13/0007 , G11C13/003 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C2013/0083 , G11C2213/32 , G11C2213/52 , G11C2213/71 , G11C2213/77 , H01L27/2454 , H01L27/249 , H01L45/08 , H01L45/1226 , H01L45/1253 , H01L45/145 , H01L45/146
摘要： A three-dimensional array of memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The memory elements can be set to a low resistance state and reset to a high resistance state during standard operation by biasing appropriate voltages on the word lines and bit lines. Prior to standard operation, the memory elements undergo a forming operation, during which current through the bit lines is limited. A forming voltage is applied to the memory elements during forming with a polarity such that a higher voltage is applied to anodes and a lower voltage to cathodes.
摘要翻译：存储元件的三维阵列，其响应于在其上施加的电压差而可逆地改变电导水平。存储器元件可以被设置为低电阻状态，并且在标准操作期间通过偏置字线和位线上的适当电压而复位到高电阻状态。在标准操作之前，存储元件进行成形操作，在此期间，通过位线的电流受到限制。在成形期间，将形成电压施加到存储元件，其极性使得较高的电压被施加到阳极，而较低的电压施加到阴极。

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