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1. 发明授权

US09281029B2 Non-volatile memory having 3D array architecture with bit line voltage control and methods thereof 有权
标题翻译：具有具有位线电压控制的3D阵列架构的非易失性存储器及其方法
公开(公告)号：US09281029B2
公开(公告)日：2016-03-08
申请号：US13794344
申请日：2013-03-11
申请人： SanDisk 3D LLC
发明人： Raul Adrian Cernea
IPC分类号： G11C7/12 , G11C8/08 , G11C11/4094 , G11C5/02 , G11C7/18 , G11C13/00
CPC分类号： G11C7/12 , G11C5/025 , G11C7/18 , G11C8/08 , G11C11/4094 , G11C13/0021 , G11C13/004
摘要： In a 3D memory with vertical local bit lines, each local bit line is switchably connected to a node on a global bit line having first and second ends, the local bit line voltage is maintained at a predetermined reference level in spite of being driven by a bit line driver from a first end of the global bit line that constitutes variable circuit path length and circuit serial resistance. This is accomplished by a feedback voltage regulator comprising a voltage clamp at the first end of the global bit line controlled by a bit line voltage comparator at the second end of the global bit line. The comparator compares the bit line voltage sensed from the second end with the predetermined reference level and outputs a control voltage to control the voltage clamp In this way the voltage at the local bit line is regulated at the reference voltage.
摘要翻译：在具有垂直局部位线的3D存储器中，每个局部位线可切换地连接到具有第一和第二端的全局位线上的节点，局部位线电压被维持在预定的参考电平，尽管由全局位线第一端的位线驱动器构成可变电路路径长度和电路串联电阻。这是通过一个反馈电压调节器实现的，该电压调节器包括在由全局位线的第二端的位线电压比较器控制的全局位线的第一端的电压钳位。比较器将从第二端检测的位线电压与预定参考电平进行比较，并输出控制电压以控制电压钳位。以这种方式，局部位线处的电压被调节在参考电压。

2. 发明申请

US20130339571A1 3D MEMORY WITH VERTICAL BIT LINES AND STAIRCASE WORD LINES AND VERTICAL SWITCHES AND METHODS THEREOF 有权
标题翻译：具有垂直位线和立柱字线和垂直开关的3D存储器及其方法
公开(公告)号：US20130339571A1
公开(公告)日：2013-12-19
申请号：US13835032
申请日：2013-03-15
申请人： SANDISK 3D LLC
发明人： Raul Adrian Cernea , Roy E. Scheuerlein
IPC分类号： G06F12/02
CPC分类号： H01L27/249 , G06F12/0238 , G11C5/025 , G11C5/06 , G11C7/18 , G11C13/0002 , G11C13/0007 , G11C13/0023 , G11C2213/71 , H01L21/76877 , H01L27/1052 , H01L27/2454 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/16 , H01L45/1608
摘要： A 3D memory with vertical local bit lines global bit lines has an in-line vertical switch in the form of a thin film transistor (TFT) formed as a vertical structure, to switch a local bit line to a global bit line. The TFT is implemented to switch a maximum of current carried by the local bit line by a strongly coupled select gate which must be fitted within the space around the local bit line. Maximum thickness of the select gate is implemented with the select gate exclusively occupying the space along the x-direction from both sides of the local bit line. The switches for odd and even bit lines of the row are staggered and offset in the z-direction so that the select gates of even and odd local bit lines are not coincident along the x-direction. The switching is further enhanced with a wrap-around select gate.
摘要翻译：具有垂直局部位线的3D存储器全局位线具有形成为垂直结构的薄膜晶体管（TFT）形式的在线垂直开关，以将局部位线切换到全局位线。 TFT被实现为通过强耦合的选择栅极来切换局部位线所承载的最大电流，该选择栅极必须装配在局部位线周围的空间内。选择栅极的最大厚度是通过选择栅极实现的，该选择栅极从局部位线的两侧专门占据x方向的空间。该行的奇数和偶数位线的开关在z方向上交错和偏移，使得偶数和奇数局部位线的选择栅极沿x方向不重合。通过环绕选择门进一步增强切换。

3. 发明申请

US20140254231A1 3D Non-Volatile Memory Having Low-Current Cells and Methods 有权
标题翻译：具有低电流电池的3D非易失性存储器和方法
公开(公告)号：US20140254231A1
公开(公告)日：2014-09-11
申请号：US14196956
申请日：2014-03-04
申请人： SanDisk 3D LLC
发明人： Raul Adrian Cernea , Yung-Tin Chen , George Samachisa
IPC分类号： G11C5/06 , G11C13/00 , H01L45/00
CPC分类号： G11C5/06 , G11C5/025 , G11C5/04 , G11C13/0002 , H01L27/2454 , H01L27/249 , H01L45/06 , H01L45/065 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/149
摘要： A 3D array of nonvolatile memory has each read/write element accessed at a crossing between a word line and a bit line. The read/write element forms a tubular electrode having an outside shell of R/W material enclosing an oxide core. In a rectangular form, one side of the electrode contacts the word line and another side contacts the bit line. The thickness of the shell rather than its surface areas in contact with the word line and bit line determines the conduction cross-section and therefore the resistance. By adjusting the thickness of the shell, independent of its contact area with either the word line or bit line, each read/write element can operate with a much increased resistance and therefore much reduced current. Processes to manufacture a 3D array with such tubular R/W elements 3D array are also described.
摘要翻译：非易失性存储器的3D阵列具有在字线和位线之间的交叉处访问的每个读/写元件。读/写元件形成具有包围氧化物核心的R / W材料的外壳的管状电极。在矩形形式中，电极的一侧接触字线，另一侧接触位线。壳体的厚度而不是与字线和位线接触的表面积决定了传导截面，因此决定了电阻。通过调整外壳的厚度，独立于与字线或位线的接触面积，每个读/写元件可以以大大增加的电阻工作，因此电流大大降低。还描述了使用这种管状R / W元件3D阵列来制造3D阵列的过程。

4. 发明申请

US20130336038A1 NON-VOLATILE MEMORY HAVING 3D ARRAY ARCHITECTURE WITH STAIRCASE WORD LINES AND VERTICAL BIT LINES AND METHODS THEREOF 有权
标题翻译：具有STAIRCASE WORD行和垂直位线的3D阵列架构的非易失性存储器及其方法
公开(公告)号：US20130336038A1
公开(公告)日：2013-12-19
申请号：US13840759
申请日：2013-03-15
申请人： SANDISK 3D LLC
发明人： Raul Adrian Cernea , George Samachisa
IPC分类号： G11C5/02 , G11C5/06
CPC分类号： H01L27/249 , G06F12/0238 , G11C5/025 , G11C5/06 , G11C7/18 , G11C13/0002 , G11C13/0007 , G11C13/0023 , G11C2213/71 , H01L21/76877 , H01L27/1052 , H01L27/2454 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/16 , H01L45/1608
摘要： In a 3D nonvolatile memory with memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes from a bottom plane to a top plane stacked in the z-direction over a semiconductor substrate; a plurality of local bit lines elongated in the z-direction through the plurality of layers and arranged in a two-dimensional rectangular array of bit line pillars having rows in the x-direction and columns in the y-direction; the 3D nonvolatile memory further having a plurality of staircase word lines spaced apart in the y-direction and between and separated from the plurality of bit line pillars at a plurality of crossings, individual staircase word lines each having a series of alternating steps and risers elongated respectively in the x-direction and z-direction traversing across the plurality of planes in the z-direction with a segment in each plane.
摘要翻译：在具有以由具有x，y和z方向的直角坐标定义的三维图案中布置的存储元件的3D非易失性存储器中，并且具有多个平行平面，从底平面到在z方向上堆叠的顶平面半导体衬底; 多个局部位线沿Z方向延伸穿过多个层并且布置在具有沿x方向和y方向的列的行的位线柱的二维矩形阵列中; 所述3D非易失性存储器还具有沿着y方向间隔开并且在多个位置处与所述多个位线柱之间和分离的多个阶梯字线，各个阶梯字线各自具有一系列交替的台阶和提升板分别在x方向和z方向上在z方向上跨越多个平面横跨每个平面中的段。

5. 发明授权

US08923050B2 3D memory with vertical bit lines and staircase word lines and vertical switches and methods thereof 有权
标题翻译：具有垂直位线和阶梯字线和垂直开关的3D存储器及其方法
公开(公告)号：US08923050B2
公开(公告)日：2014-12-30
申请号：US13835032
申请日：2013-03-15
申请人： SanDisk 3D LLC
发明人： Raul Adrian Cernea , Roy E. Scheuerlein
IPC分类号： G11C11/34 , G11C5/02 , G11C5/06 , H01L27/105 , H01L21/768 , G06F12/02 , G11C7/18 , G11C13/00 , H01L27/24 , H01L45/00
CPC分类号： H01L27/249 , G06F12/0238 , G11C5/025 , G11C5/06 , G11C7/18 , G11C13/0002 , G11C13/0007 , G11C13/0023 , G11C2213/71 , H01L21/76877 , H01L27/1052 , H01L27/2454 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/16 , H01L45/1608
摘要： A 3D memory with vertical local bit lines global bit lines has an in-line vertical switch in the form of a thin film transistor (TFT) formed as a vertical structure, to switch a local bit line to a global bit line. The TFT is implemented to switch a maximum of current carried by the local bit line by a strongly coupled select gate which must be fitted within the space around the local bit line. Maximum thickness of the select gate is implemented with the select gate exclusively occupying the space along the x-direction from both sides of the local bit line. The switches for odd and even bit lines of the row are staggered and offset in the z-direction so that the select gates of even and odd local bit lines are not coincident along the x-direction. The switching is further enhanced with a wrap-around select gate.
摘要翻译：具有垂直局部位线的3D存储器全局位线具有形成为垂直结构的薄膜晶体管（TFT）形式的在线垂直开关，以将局部位线切换到全局位线。 TFT被实现为通过强耦合的选择栅极来切换局部位线所承载的最大电流，该选择栅极必须装配在局部位线周围的空间内。选择栅极的最大厚度是通过选择栅极实现的，该选择栅极从局部位线的两侧专门占据x方向的空间。该行的奇数和偶数位线的开关在z方向上交错和偏移，使得偶数和奇数局部位线的选择栅极沿x方向不重合。通过环绕选择门进一步增强切换。

6. 发明申请

US20130337646A1 METHOD FOR FORMING STAIRCASE WORD LINES IN A 3D NON-VOLATILE MEMORY HAVING VERTICAL BIT LINES 有权
标题翻译：在具有垂直位线的3D非易失性存储器中形成站点字线的方法
公开(公告)号：US20130337646A1
公开(公告)日：2013-12-19
申请号：US13840201
申请日：2013-03-15
申请人： SANDISK 3D LLC
发明人： Raul Adrian Cernea , Henry Chien
IPC分类号： H01L21/768
CPC分类号： H01L27/249 , G06F12/0238 , G11C5/025 , G11C5/06 , G11C7/18 , G11C13/0002 , G11C13/0007 , G11C13/0023 , G11C2213/71 , H01L21/76877 , H01L27/1052 , H01L27/2454 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/16 , H01L45/1608
摘要： A 3D nonvolatile memory has memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes stacked in the z-direction over a semiconductor substrate. It has vertical local bit lines and a plurality of staircase word lines. Each staircase word line has a series of alternating segments and risers elongated respectively in the x-direction and z-direction traversing across the plurality of planes in the z-direction with a segment in each plane. Methods of forming a slab of multi-plane memory with staircase word lines include processes with one masking and with two maskings for forming each plane.
摘要翻译： 3D非易失性存储器具有以由具有x，y和z方向的直角坐标限定的三维图案布置的存储元件，并且在半导体衬底上沿z方向堆叠多个平行平面。它具有垂直的局部位线和多个阶梯字线。每个阶梯字线具有在x方向和z方向上分别在z方向上穿过多个平面的每个平面中的段的一系列交替的段和提升板。用阶梯字线形成多平面存储器的平板的方法包括具有一个掩模和用于形成每个平面的两个掩模的处理。

7. 发明授权

US09123430B2 Differential current sense amplifier and method for non-volatile memory 有权
标题翻译：差分电流检测放大器和非易失性存储器的方法
公开(公告)号：US09123430B2
公开(公告)日：2015-09-01
申请号：US13918833
申请日：2013-06-14
申请人： SanDisk 3D LLC
发明人： Raul Adrian Cernea
IPC分类号： G11C16/06 , G11C16/28 , G11C7/06
CPC分类号： G11C16/28 , G11C7/062 , G11C2207/063
摘要： The selected bit line in a non-volatile memory carries a cell conduction current to be measured and also a leakage current or noise due to weak coupling with neighboring array structures. In a first phase, a sense amplifier senses the bit line current by discharging a capacitor with the combined current (cell conduction current plus the leakage current) over a predetermined time. In a second phase, the cell conduction current is minimized and significantly the leakage current in the selected bit line is used to recharge in tandem the capacitor in a time same as the predetermined time, effectively subtracting the component of the leakage current measured in the first sensing phase. The resultant voltage drop on the capacitor over the two sensing phases provides a measure of the cell conduction current alone, thereby avoiding reading errors due to the leakage current present in the selected bit line.
摘要翻译：非易失性存储器中所选择的位线携带要测量的单元传导电流，以及由于与相邻阵列结构的弱耦合而引起的漏电流或噪声。在第一阶段，读出放大器通过在预定时间内以组合电流（单元传导电流加上泄漏电流）放电电容器来感测位线电流。在第二阶段，电池导通电流被最小化，并且显着地，使用所选位线中的漏电流在与预定时间相同的时间内串联电容器，从而有效地减去第一检测阶段。两个感测相位上的电容器上产生的电压降提供了单独的电池导通电流的量度，从而避免了由于存在于所选位线中的泄漏电流而导致的读取误差。

8. 发明申请

US20130336037A1 3D MEMORY HAVING VERTICAL SWITCHES WITH SURROUND GATES AND METHOD THEREOF 审中-公开
标题翻译：具有环形门的垂直开关的3D存储器及其方法
公开(公告)号：US20130336037A1
公开(公告)日：2013-12-19
申请号：US13838782
申请日：2013-03-15
申请人： SANDISK 3D LLC
发明人： Yung-Tin Chen , Steven J. Radigan , Roy E. Scheuerlein , Raul Adrian Cernea
IPC分类号： G11C5/06 , H01L27/105
CPC分类号： H01L27/249 , G06F12/0238 , G11C5/025 , G11C5/06 , G11C7/18 , G11C13/0002 , G11C13/0007 , G11C13/0023 , G11C2213/71 , H01L21/76877 , H01L27/1052 , H01L27/2454 , H01L45/04 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/16 , H01L45/1608
摘要： A vertical switching layer of a 3D memory device serves to switch a set of vertical local bit lines to a corresponding set of global bit lines, the vertical switching layer being a 2D array of TFT channels of vertical thin-film transistors (TFTs) aligned to connect to an array of local bit lines, each TFT switching a local bit line to a corresponding global bit line. The TFTs in the array have a separation of lengths Lx and Ly along the x- and y-axis respectively such that a gate material layer forms a surround gate around each TFT in an x-y plane and has a thickness that merges to form a row select line along the x-axis while maintaining a separation of length Ls between individual row select lines. The surround gate improves the switching capacity of the TFTs.
摘要翻译： 3D存储器件的垂直切换层用于将一组垂直局部位线切换到相应的全局位线集合，垂直切换层是垂直薄膜晶体管（TFT）的TFT通道的2D阵列，其与连接到本地位线阵列，每个TFT将局部位线切换到相应的全局位线。阵列中的TFT分别具有沿着x轴和y轴的长度Lx和Ly的间隔，使得栅极材料层在xy平面内围绕每个TFT形成环绕栅，并且具有合并以形成行选择的厚度沿x轴线，同时保持单独行选择线之间的长度Ls的间隔。环绕栅极提高了TFT的开关容量。

9. 发明申请

US20130336036A1 NON-VOLATILE MEMORY HAVING 3D ARRAY ARCHITECTURE WITH BIT LINE VOLTAGE CONTROL AND METHODS THEREOF 有权
标题翻译：具有位线电压控制的三维阵列结构的非易失性存储器及其方法
公开(公告)号：US20130336036A1
公开(公告)日：2013-12-19
申请号：US13794344
申请日：2013-03-11
申请人： SANDISK 3D LLC
发明人： Raul Adrian Cernea
IPC分类号： G11C7/12 , G11C5/02
CPC分类号： G11C7/12 , G11C5/025 , G11C7/18 , G11C8/08 , G11C11/4094 , G11C13/0021 , G11C13/004
摘要： In a 3D memory with vertical local bit lines, each local bit line is switchably connected to a node on a global bit line having first and second ends, the local bit line voltage is maintained at a predetermined reference level in spite of being driven by a bit line driver from a first end of the global bit line that constitutes variable circuit path length and circuit serial resistance. This is accomplished by a feedback voltage regulator comprising a voltage clamp at the first end of the global bit line controlled by a bit line voltage comparator at the second end of the global bit line. The comparator compares the bit line voltage sensed from the second end with the predetermined reference level and outputs a control voltage to control the voltage clamp In this way the voltage at the local bit line is regulated at the reference voltage.
摘要翻译：在具有垂直局部位线的3D存储器中，每个局部位线可切换地连接到具有第一和第二端的全局位线上的节点，局部位线电压被维持在预定的参考电平，尽管由全局位线第一端的位线驱动器构成可变电路路径长度和电路串联电阻。这是通过一个反馈电压调节器实现的，该电压调节器包括在由全局位线的第二端的位线电压比较器控制的全局位线的第一端的电压钳位。比较器将从第二端检测的位线电压与预定参考电平进行比较，并输出控制电压以控制电压钳位。以这种方式，局部位线处的电压被调节在参考电压。

10. 发明授权

US09147439B2 Non-volatile memory having 3D array architecture with staircase word lines and vertical bit lines and methods thereof 有权
标题翻译：具有具有阶梯字线和垂直位线的3D阵列架构的非易失性存储器及其方法
公开(公告)号：US09147439B2
公开(公告)日：2015-09-29
申请号：US13840759
申请日：2013-03-15
申请人： SanDisk 3D LLC
发明人： Raul Adrian Cernea , George Samachisa
IPC分类号： G11C5/02 , G11C5/06 , H01L27/105 , H01L21/768 , G06F12/02 , G11C7/18 , G11C13/00 , H01L27/24 , H01L45/00
CPC分类号： H01L27/249 , G06F12/0238 , G11C5/025 , G11C5/06 , G11C7/18 , G11C13/0002 , G11C13/0007 , G11C13/0023 , G11C2213/71 , H01L21/76877 , H01L27/1052 , H01L27/2454 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/16 , H01L45/1608
摘要： In a 3D nonvolatile memory with memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes from a bottom plane to a top plane stacked in the z-direction over a semiconductor substrate; a plurality of local bit lines elongated in the z-direction through the plurality of layers and arranged in a two-dimensional rectangular array of bit line pillars having rows in the x-direction and columns in the y-direction; the 3D nonvolatile memory further having a plurality of staircase word lines spaced apart in the y-direction and between and separated from the plurality of bit line pillars at a plurality of crossings, individual staircase word lines each having a series of alternating steps and risers elongated respectively in the x-direction and z-direction traversing across the plurality of planes in the z-direction with a segment in each plane.
摘要翻译：在具有以由具有x，y和z方向的直角坐标定义的三维图案中布置的存储元件的3D非易失性存储器中，并且具有多个平行平面，从底平面到在z方向上堆叠的顶平面半导体衬底; 多个局部位线沿Z方向延伸穿过多个层并且布置在具有沿x方向和y方向的行的位线柱的二维矩形阵列中; 所述3D非易失性存储器还具有沿着y方向间隔开并且在多个位置处与所述多个位线柱之间和分离的多个阶梯字线，各个阶梯字线各自具有一系列交替的台阶和提升板分别在x方向和z方向上在z方向上跨越多个平面横跨每个平面中的段。

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