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1. 发明授权

US11276580B2 Connecting structure of a conductive layer 有权
公开(公告)号：US11276580B2
公开(公告)日：2022-03-15
申请号：US16296646
申请日：2019-03-08
申请人： SAMSUNG DISPLAY CO., LTD.
发明人： Su Bin Bae , Yu-Gwang Jeong , Shin Il Choi , Sang Gab Kim , Joon Geol Lee
IPC分类号： H01L29/41 , H01L21/311 , H01L21/027 , H01L21/768 , H01L21/763
摘要： A connecting structure of a conductive layer includes a first conductive layer, a first insulating layer disposed on the first conductive layer and including a first opening overlapping the first conductive layer, a connecting conductor disposed on the first insulating layer and connected to the first conductive layer through the first opening, an insulator island disposed on the connecting conductor, a second insulating layer disposed on the first insulating layer and including a second opening overlapping the connecting conductor and the insulator island, and a second conductive layer disposed on the second insulating layer and connected to a connecting electrode through the second opening. A sum of a thickness of the first insulating layer and a thickness of the second insulating layer is greater than or equal to 1 μm, and each of the thicknesses of the first and second insulating layers is less than 1 μm.

2. 发明授权

US11127807B2 Display device and manufacturing method thereof 有权
公开(公告)号：US11127807B2
公开(公告)日：2021-09-21
申请号：US16521394
申请日：2019-07-24
申请人： Samsung Display Co., Ltd. , POSTECH ACADEMY-INDUSTRY FOUNDATION
发明人： Sang Gab Kim , Hyun Min Cho , Tae Sung Kim , Yu-Gwang Jeong , Su Bin Bae , Jin Seock Kim , Sang Gyun Kim , Hyo Min Ko , Kil Won Cho , Hansol Lee
IPC分类号： H01L27/32 , H01L51/56
摘要： An manufacturing method of a display device may include the following steps: forming a transistor on a substrate; forming an insulating layer on the transistor; forming a conductive layer including silver on the insulating layer; forming a photosensitive member on the conductive layer; forming an electrode of a light-emitting element by etching the conductive layer; performing plasma treatment on a structure that comprises the electrode, the plasma treatment using a gas including a halogen; and removing a product that is resulted from the plasma treatment.

3. 发明授权

US10741589B2 Transistor array panel and manufacturing method thereof 有权
公开(公告)号：US10741589B2
公开(公告)日：2020-08-11
申请号：US16215520
申请日：2018-12-10
申请人： Samsung Display Co., Ltd.
发明人： Yu-Gwang Jeong , Hyun Min Cho , Su Bin Bae , Shin Il Choi , Sang Gab Kim
IPC分类号： H01L27/12 , H01L21/311 , H01L29/417 , H01L29/786 , G02F1/1368 , H01L27/32
摘要： A transistor array panel is manufactured by a method that reduces or obviates the need for highly selective etching agents or complex processes requiring multiple photomasks to create contact holes. The panel includes: a substrate; a buffer layer positioned on the substrate; a semiconductor layer positioned on the buffer layer; an intermediate insulating layer positioned on the semiconductor layer; and an upper conductive layer positioned on the intermediate insulating layer, wherein the semiconductor layer includes a first contact hole, the intermediate insulating layer includes a second contact hole positioned in an overlapping relationship with the first contact hole, and the upper conductive layer is in contact with a side surface of the semiconductor layer in the first contact hole.

4. 发明授权

US09830033B2 Touch sensor and method of manufacturing the same 有权
公开(公告)号：US09830033B2
公开(公告)日：2017-11-28
申请号：US14925439
申请日：2015-10-28
申请人： Samsung Display Co., Ltd.
发明人： Jung Ha Son , Jae Neung Kim , Yong-Hwan Ryu , Yun Jong Yeo , Joo Hyung Lee , Yu-Gwang Jeong
IPC分类号： G06F3/044 , G06F3/041
CPC分类号： G06F3/044 , G06F3/0416 , G06F2203/04102 , G06F2203/04103
摘要： A touch sensor includes a touch substrate including a touch sensing area and a non-sensing area outside the touch sensing area, touch electrodes disposed in the touch sensing area and configured to sense a touch, and touch wiring connected to the touch electrodes in the non-sensing area, in which the touch wiring includes a first wiring conductive layer, a second wiring conductive layer disposed on the first wiring conductive layer, and transparent layers disposed at first and second sides of the second wiring conductive layer and on the first wiring conductive layer.

5. 发明授权

US09768309B2 Thin film transistor and thin film transistor array panel including the same 有权
公开(公告)号：US09768309B2
公开(公告)日：2017-09-19
申请号：US15194841
申请日：2016-06-28
申请人： SAMSUNG DISPLAY CO., LTD.
发明人： Yong Su Lee , Yoon Ho Khang , Dong Jo Kim , Hyun Jae Na , Sang Ho Park , Se Hwan Yu , Chong Sup Chang , Dae Ho Kim , Jae Neung Kim , Myoung Geun Cha , Sang Gab Kim , Yu-Gwang Jeong
IPC分类号： H01L27/00 , H01L29/00 , H01L29/786 , H01L27/12 , H01L29/66 , H01L29/417 , H01L27/32
CPC分类号： H01L29/78633 , H01L27/1225 , H01L27/124 , H01L27/1288 , H01L27/3262 , H01L29/41733 , H01L29/66969 , H01L29/78618 , H01L29/7869 , H01L29/78696
摘要： A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

6. 发明授权

US09406630B2 Contact portion of wire and manufacturing method thereof 有权
公开(公告)号：US09406630B2
公开(公告)日：2016-08-02
申请号：US14579542
申请日：2014-12-22
申请人： SAMSUNG DISPLAY CO., LTD.
发明人： Joo-Han Kim , Ki-Yong Song , Dong-Ju Yang , Hee-Joon Kim , Yeo-Geon Yoon , Sung-Hen Cho , Chang-Hoon Kim , Jae-Hong Kim , Yu-Gwang Jeong , Ki-Yeup Lee , Sang-Gab Kim , Yun-Jong Yeo , Shin-Il Choi , Ji-Young Park
IPC分类号： H01L23/00 , G02F1/1362 , H01L27/12
CPC分类号： H01L24/05 , G02F1/136227 , H01L27/12 , H01L27/1214 , H01L27/124 , H01L2224/04042 , H01L2924/14 , H01L2924/1426 , H01L2924/00
摘要： A contact portion of wiring and a method of manufacturing the same are disclosed. A contact portion of wiring according to an embodiment includes: a substrate; a conductive layer disposed on the substrate; an interlayer insulating layer disposed on the conductive layer and having a contact hole; a metal layer disposed on the conductive layer and filling the contact hole; and a transparent electrode disposed on the interlayer insulating layer and connected to the metal layer, wherein the interlayer insulating layer includes a lower insulating layer and an upper insulating layer disposed on the lower insulating layer, the lower insulating layer is undercut at the contact hole, and the metal layer fills in the portion where the lower insulating layer is undercut.

7. 发明授权

US09365933B2 Method of forming a fine pattern 有权
标题翻译：形成精细图案的方法
公开(公告)号：US09365933B2
公开(公告)日：2016-06-14
申请号：US14718127
申请日：2015-05-21
申请人： Samsung Display Co., Ltd.
发明人： Jung-Ha Son , Su-Bin Bae , Yu-Gwang Jeong , Lei Xie , Yun-Jong Yeo , Joo-Hyung Lee
IPC分类号： C23F1/02 , H01L21/033 , G03F7/00
CPC分类号： G03F7/0002 , C23F1/02 , G02F1/133536 , G02F2001/133548 , G02F2202/36 , H01L21/0337 , H01L21/32139
摘要： A method of forming a fine pattern includes providing a first metal layer on a base substrate, providing a first passivation layer on the first metal layer, providing a mask pattern on the first passivation layer, providing a partitioning wall pattern having a reverse taper shape by etching the first passivation layer, coating a composition having a block copolymer between the partitioning wall patterns adjacent each other, providing a self-aligned pattern by heating the composition, and providing a metal pattern by etching the first metal layer using the self-aligned pattern as a mask.
摘要翻译：形成精细图案的方法包括在基底基板上提供第一金属层，在第一金属层上提供第一钝化层，在第一钝化层上提供掩模图案，通过以下步骤提供具有倒锥形的分隔壁图案：蚀刻第一钝化层，在彼此相邻的分隔壁图案之间涂覆具有嵌段共聚物的组合物，通过加热组合物提供自对准图案，以及通过使用自对准图案蚀刻第一金属层来提供金属图案作为面具。

8. 发明申请

US20150070643A1 DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：显示装置及其制造方法
公开(公告)号：US20150070643A1
公开(公告)日：2015-03-12
申请号：US14195051
申请日：2014-03-03
申请人： Samsung Display Co., Ltd.
发明人： Jae-Neung Kim , Yu-Gwang Jeong , Sang-Gab Kim , Su-Bin Bae , Shin-Il Choi
IPC分类号： H01L27/12 , G02F1/1343
CPC分类号： H01L27/1225 , G02F1/134309 , G02F1/136213 , G02F2201/50 , H01L27/1248 , H01L27/1255 , H01L27/1259
摘要： A display apparatus includes: a substrate defining transistor and wiring areas; a thin film transistor in the transistor area and including a gate electrode, an active layer, and source and drain electrodes; an etch prevention layer in the transistor area, absent in the wiring area and covering the active layer, and first and second contact holes defined in the etch prevention layer and through which the active layer is electrically coupled to the source and drain electrodes; a first wiring layer in the wiring area; a first insulating layer which covers the gate electrode and the first wiring layer, and a third contact hole defined in the first insulating layer in the wiring area and exposing the first wiring layer; and a second wiring layer on the first insulating layer and in the wiring area, and electrically coupled to the first wiring layer via the third contact hole.
摘要翻译：显示装置包括：限定晶体管和布线区域的基板; 晶体管区域中的薄膜晶体管，并且包括栅电极，有源层以及源极和漏极; 晶体管区域中的防蚀层，在布线区域中不存在并覆盖有源层，以及限定在防蚀层中的第一和第二接触孔，有源层电耦合到源电极和漏电极; 布线区域中的第一布线层; 覆盖所述栅电极和所述第一布线层的第一绝缘层和限定在所述布线区域中的所述第一绝缘层中的第三接触孔，并暴露所述第一布线层; 以及在所述第一绝缘层和所述布线区域中的第二布线层，并且经由所述第三接触孔电耦合到所述第一布线层。

9. 发明授权

US08853703B2 Thin film transistor array panel 有权
标题翻译：薄膜晶体管阵列面板
公开(公告)号：US08853703B2
公开(公告)日：2014-10-07
申请号：US13830269
申请日：2013-03-14
申请人： Samsung Display Co., Ltd.
发明人： Ji-Young Park , Yu-Gwang Jeong , Sang Gab Kim , Joon Geol Lee
IPC分类号： H01L29/04 , H01L29/15 , H01L31/036 , H01L29/10 , H01L31/0376 , H01L31/20 , H01L31/062 , H01L31/113 , H01L29/786 , H01L29/66
CPC分类号： H01L27/1259 , G02F1/134363 , G02F1/136227 , H01L27/124 , H01L29/66765 , H01L29/78669 , H01L29/78678
摘要： A thin film transistor array panel includes a substrate, gate lines, each including a gate pad, a gate insulating layer, data lines, each including a data pad connected to a source and drain electrode, a first passivation layer disposed on the data lines and the drain electrode, a first electric field generating electrode, a second passivation layer disposed on the first electric field generating electrode, and a second electric field generating electrode. The gate insulating layer and the first and second passivation layers include a first contact hole exposing a part of the gate pad, the first and second passivation layers include a second contact hole exposing a part of the data pad, and at least one of the first and second contact holes have a positive taper structure having a wider area at an upper side than at a lower side.
摘要翻译：薄膜晶体管阵列面板包括基板，栅极线，每个栅极线包括栅极焊盘，栅极绝缘层，数据线，每条数据线包括连接到源极和漏极的数据焊盘，设置在数据线上的第一钝化层和漏电极，第一电场产生电极，设置在第一电场产生电极上的第二钝化层和第二电场产生电极。栅极绝缘层和第一和第二钝化层包括暴露栅极焊盘的一部分的第一接触孔，第一和第二钝化层包括暴露数据焊盘的一部分的第二接触孔，以及第一和第二钝化层中的至少一个并且第二接触孔具有在上侧具有比在下侧更宽的面积的正锥形结构。

10. 发明申请

US20140167040A1 THIN FILM TRANSISTOR, THIN FILM TRANSISTOR ARRAY PANEL INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：薄膜晶体管，包括其的薄膜晶体管阵列面板及其制造方法
公开(公告)号：US20140167040A1
公开(公告)日：2014-06-19
申请号：US14184361
申请日：2014-02-19
申请人： Samsung Display Co., Ltd.
发明人： Yong Su Lee , Yoon Ho Khang , Dong Jo Kim , Hyun Jae Na , Sang Ho Park , Se Hwan Yu , Chong Sup Chang , Dae Ho Kim , Jae Neung Kim , Myoung Geun Cha , Sang Gab Kim , Yu-Gwang Jeong
IPC分类号： H01L29/786 , H01L29/66
CPC分类号： H01L29/78633 , H01L27/1225 , H01L27/124 , H01L27/1288 , H01L27/3262 , H01L29/41733 , H01L29/66969 , H01L29/78618 , H01L29/7869 , H01L29/78696
摘要： A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.
摘要翻译：根据本发明的示例性实施例的薄膜晶体管包括氧化物半导体。源电极和漏电极彼此面对。源电极和漏电极分别位于氧化物半导体的两个相对侧。低导电区域位于源电极或漏电极与氧化物半导体之间。绝缘层位于氧化物半导体和低导电区域上。栅电极位于绝缘层上。绝缘层覆盖氧化物半导体和低导电区域。低导电区域的载流子浓度低于源电极或漏电极的载流子浓度。

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