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1. 发明申请

US20090115030A1 N2 BASED PLASMA TREATMENT FOR ENHANCED SIDEWALL SMOOTHING AND PORE SEALING OF POROUS LOW-K DIELECTRIC FILMS 有权
标题翻译： N2基等离子体处理，用于增强多孔低介电膜的增强型平板光滑和多孔密封
公开(公告)号：US20090115030A1
公开(公告)日：2009-05-07
申请号：US12330732
申请日：2008-12-09
申请人： Sameer Kumar Ajmera , Patricia Beauregard Smith , Changming Jin
发明人： Sameer Kumar Ajmera , Patricia Beauregard Smith , Changming Jin
IPC分类号： H01L29/06
CPC分类号： H01L21/02126 , H01L21/02332 , H01L21/0234 , H01L21/02362 , H01L21/31058 , H01L21/31695 , H01L21/76801
摘要： A method of forming a semiconductor device including forming a low-k dielectric material over a substrate, depositing a liner on a portion of the low-k dielectric material, and exposing the liner to a plasma. The method also includes depositing a layer over the liner.
摘要翻译：一种形成半导体器件的方法，包括在衬底上形成低k电介质材料，在低k电介质材料的一部分上沉积衬垫，以及将衬套暴露于等离子体。该方法还包括在衬垫上沉积层。

2. 发明授权

US07910936B2 N2 based plasma treatment for enhanced sidewall smoothing and pore sealing of porous low-k dielectric films 有权
标题翻译：基于N2的等离子体处理，用于增强多孔低k电介质膜的侧壁平滑和孔密封
公开(公告)号：US07910936B2
公开(公告)日：2011-03-22
申请号：US12330732
申请日：2008-12-09
申请人： Sameer Kumar Ajmera , Patricia Beauregard Smith , Changming Jin
发明人： Sameer Kumar Ajmera , Patricia Beauregard Smith , Changming Jin
IPC分类号： H01L27/15 , H01L31/12 , H01L33/00
CPC分类号： H01L21/02126 , H01L21/02332 , H01L21/0234 , H01L21/02362 , H01L21/31058 , H01L21/31695 , H01L21/76801
摘要： A method of forming a semiconductor device including forming a low-k dielectric material over a substrate, depositing a liner on a portion of the low-k dielectric material, and exposing the liner to a plasma. The method also includes depositing a layer over the liner.
摘要翻译：一种形成半导体器件的方法，包括在衬底上形成低k电介质材料，在低k电介质材料的一部分上沉积衬垫，以及将衬套暴露于等离子体。该方法还包括在衬垫上沉积层。

3. 发明授权

US07476602B2 N2 based plasma treatment for enhanced sidewall smoothing and pore sealing porous low-k dielectric films 有权
标题翻译： N2基等离子体处理，用于增强侧壁平滑和孔隙密封多孔低k介电膜
公开(公告)号：US07476602B2
公开(公告)日：2009-01-13
申请号：US11046230
申请日：2005-01-31
申请人： Sameer Kumar Ajmera , Patricia Beauregard Smith , Changming Jin
发明人： Sameer Kumar Ajmera , Patricia Beauregard Smith , Changming Jin
IPC分类号： H01L21/26 , H01L21/42
CPC分类号： H01L21/02126 , H01L21/02332 , H01L21/0234 , H01L21/02362 , H01L21/31058 , H01L21/31695 , H01L21/76801
摘要： A method of forming a semiconductor device including forming a low-k dielectric material over a substrate, depositing a liner on a portion of the low-k dielectric material, and exposing the liner to a plasma. The method also includes depositing a layer over the liner.
摘要翻译：一种形成半导体器件的方法，包括在衬底上形成低k电介质材料，在低k电介质材料的一部分上沉积衬垫，以及将衬套暴露于等离子体。该方法还包括在衬垫上沉积层。

4. 发明授权

US07781884B2 Method of fabrication of on-chip heat pipes and ancillary heat transfer components 有权
标题翻译：片上热管和辅助传热部件的制造方法
公开(公告)号：US07781884B2
公开(公告)日：2010-08-24
申请号：US11863477
申请日：2007-09-28
申请人： Sameer Kumar Ajmera , Phillip D. Matz , Stephan Grunow , Satyavolu Srinivas Papa Rao
发明人： Sameer Kumar Ajmera , Phillip D. Matz , Stephan Grunow , Satyavolu Srinivas Papa Rao
IPC分类号： H01L23/34
CPC分类号： H01L23/427 , H01L2924/0002 , H01L2924/00
摘要： The density of components in integrated circuits (ICs) is increasing with time. The density of heat generated by the components is similarly increasing. Maintaining the temperature of the components at reliable operating levels requires increased thermal transfer rates from the components to the IC package exterior. Dielectric materials used in interconnect regions have lower thermal conductivity than silicon dioxide. This invention comprises a heat pipe located in the interconnect region of an IC to transfer heat generated by components in the IC substrate to metal plugs located on the top surface of the IC, where the heat is easily conducted to the exterior of the IC package. Refinements such as a wicking liner or reticulated inner surface will increase the thermal transfer efficiency of the heat pipe. Strengthening elements in the interior of the heat pipe will provide robustness to mechanical stress during IC manufacture.
摘要翻译：集成电路（IC）中组件的密度随时间而增加。组件产生的热密度同样增加。将组件的温度保持在可靠的操作水平，需要增加从组件到IC封装外部的热传递速率。互连区域中使用的介电材料的热导率低于二氧化硅。本发明包括位于IC的互连区域中的热管，用于将IC基板中的部件产生的热量转移到位于IC顶表面上的金属插头，其中热量易于传导到IC封装的外部。诸如芯吸衬垫或网状内表面的改进将增加热管的热传递效率。热管内部加强元件将为IC制造过程中的机械应力提供坚固耐用性。

5. 发明授权

US07115467B2 Metal insulator metal (MIM) capacitor fabrication with sidewall barrier removal aspect 有权
公开(公告)号：US07115467B2
公开(公告)日：2006-10-03
申请号：US10903712
申请日：2004-07-30
申请人： Sameer Kumar Ajmera , Darius L. Crenshaw , Stephan Grunow , Satyavolu S. Papa Rao , Phillip D. Matz
发明人： Sameer Kumar Ajmera , Darius L. Crenshaw , Stephan Grunow , Satyavolu S. Papa Rao , Phillip D. Matz
IPC分类号： H01L21/8242
CPC分类号： H01L28/75
摘要： A method (10) of forming a MIM (metal insulator metal) capacitor is disclosed whereby adverse affects associated with copper diffusion are mitigated even as the capacitor is scaled down. A layer of bottom electrode/copper diffusion barrier material (136) is formed (16) within an aperture (128) wherein the capacitor (100) is to be defined. The bottom electrode layer (136) is formed via a directional process so that a horizontal aspect (138) of the layer (136) is formed over a metal (110) at a bottom of the aperture (128) to a thickness (142) that is greater than a thickness (144) of a sidewall aspect (148) of the layer (136) formed upon sidewalls (132) of the aperture (128). Accordingly, the thinner sidewall aspects (148) are removed during an etching act (18) while some of the thicker horizontal aspect (138) remains. A layer of capacitor dielectric material (150) is then conformally formed (20) into the aperture 128 and over the horizontal aspect (138). A layer of top electrode material (152) is then conformally formed (22) over the layer of capacitor dielectric material (150) to complete the capacitor stack (154).

6. 发明申请

US20090085197A1 Method of Fabrication of On-Chip Heat Pipes and Ancillary Heat Transfer Components 有权
标题翻译：片上热管和辅助传热部件的制造方法
公开(公告)号：US20090085197A1
公开(公告)日：2009-04-02
申请号：US11863477
申请日：2007-09-28
申请人： Sameer Kumar Ajmera , Phillip D. Matz , Stephan Grunow , Satyavolu Srinivas Papa Rao
发明人： Sameer Kumar Ajmera , Phillip D. Matz , Stephan Grunow , Satyavolu Srinivas Papa Rao
IPC分类号： H01L23/34
CPC分类号： H01L23/427 , H01L2924/0002 , H01L2924/00
摘要： The density of components in integrated circuits (ICs) is increasing with time. The density of heat generated by the components is similarly increasing. Maintaining the temperature of the components at reliable operating levels requires increased thermal transfer rates from the components to the IC package exterior. Dielectric materials used in interconnect regions have lower thermal conductivity than silicon dioxide. This invention comprises a heat pipe located in the interconnect region of an IC to transfer heat generated by components in the IC substrate to metal plugs located on the top surface of the IC, where the heat is easily conducted to the exterior of the IC package. Refinements such as a wicking liner or reticulated inner surface will increase the thermal transfer efficiency of the heat pipe. Strengthening elements in the interior of the heat pipe will provide robustness to mechanical stress during IC manufacture.
摘要翻译：集成电路（IC）中组件的密度随时间而增加。组件产生的热密度同样增加。将组件的温度保持在可靠的操作水平，需要增加从组件到IC封装外部的热传递速率。互连区域中使用的介电材料的热导率低于二氧化硅。本发明包括位于IC的互连区域中的热管，用于将IC基板中的部件产生的热量转移到位于IC顶表面上的金属插头，其中热量易于传导到IC封装的外部。诸如芯吸衬垫或网状内表面的改进将增加热管的热传递效率。热管内部加强元件将为IC制造过程中的机械应力提供坚固耐用性。

7. 发明授权

US07338893B2 Integration of pore sealing liner into dual-damascene methods and devices 有权
标题翻译：将密封衬垫整合到双镶嵌方法和装置中
公开(公告)号：US07338893B2
公开(公告)日：2008-03-04
申请号：US11286877
申请日：2005-11-23
申请人： Edward Raymond Engbrecht , Satyavolu Srinivas Papa Rao , Sameer Kumar Ajmera , Stephan Grunow
发明人： Edward Raymond Engbrecht , Satyavolu Srinivas Papa Rao , Sameer Kumar Ajmera , Stephan Grunow
IPC分类号： H01L21/4763
CPC分类号： H01L21/76831 , H01L21/76844
摘要： A device employs damascene layers with a pore sealing liner and includes a semiconductor body. A metal interconnect layer comprising a metal interconnect is formed over the semiconductor body. A dielectric layer is formed over the metal interconnect layer. A conductive trench feature and a conductive via feature are formed in the dielectric layer. A pore sealing liner is formed only along sidewall of the conductive via feature and along sidewalls and bottom surfaces of the conductive trench feature. The pore sealing liner is not substantially present along a bottom surface of the conductive via feature.
摘要翻译：装置采用具有孔密封衬垫的镶嵌层，并且包括半导体本体。包括金属互连的金属互连层形成在半导体本体上。介电层形成在金属互连层上。导电沟槽特征和导电通孔特征形成在电介质层中。孔密封衬垫仅沿着导电通孔特征的侧壁并且沿着导电沟槽特征的侧壁和底表面形成。孔密封衬垫基本上不存在于导电通孔特征的底表面上。

8. 发明授权

US07189615B2 Single mask MIM capacitor and resistor with in trench copper drift barrier 有权
标题翻译：单掩模MIM电容器和电阻器具有沟槽铜漂移屏障
公开(公告)号：US07189615B2
公开(公告)日：2007-03-13
申请号：US11037530
申请日：2005-01-18
申请人： Satyavolu Srinivas Papa Rao , Darius Lammont Crenshaw , Stephan Grunow , Kenneth D. Brennan , Somit Joshi , Montray Leavy , Phillip D. Matz , Sameer Kumar Ajmera , Yuri E. Solomentsev
发明人： Satyavolu Srinivas Papa Rao , Darius Lammont Crenshaw , Stephan Grunow , Kenneth D. Brennan , Somit Joshi , Montray Leavy , Phillip D. Matz , Sameer Kumar Ajmera , Yuri E. Solomentsev
IPC分类号： H01L21/8242
CPC分类号： H01L21/76834 , H01L21/288 , H01L21/76816 , H01L21/76849 , H01L23/5223 , H01L28/20 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： The formation of a MIM (metal insulator metal) capacitor (164) and concurrent formation of a resistor (166) is disclosed. A copper diffusion barrier (124) is formed over a copper deposition (110) that serves as a bottom electrode (170) of the capacitor (164). The copper diffusion barrier (124) mitigates unwanted diffusion of copper from the copper deposition (110), and is formed via electro-less deposition such that little to none of the barrier material is deposited at locations other than over a top surface (125) of the deposition of copper/bottom electrode. Subsequently, layers of dielectric (150) and conductive (152) materials are applied to form a dielectric (172) and top electrode (174) of the MIM capacitor (164), respectively, where the layer of conductive top electrode material (152) also functions to concurrently develop the resistor (166) on the same chip as the capacitor (164).
摘要翻译：公开了MIM（金属绝缘金属）电容器（164）的形成和电阻器（166）的同时形成。在用作电容器（164）的底部电极（170）的铜沉积（110）上形成铜扩散阻挡层（124）。铜扩散阻挡层（124）减轻了铜从铜沉积物（110）的不期望的扩散，并且通过无电沉积形成，使得在除了顶部表面（125）之外的位置处几乎不会沉积阻挡材料，的铜/底电极的沉积。随后，分别施加介电层（150）和导电（152）材料层以形成MIM电容器（164）的电介质（172）和顶电极（174），其中导电顶电极材料层（152）还用于同时开发与电容器（164）相同的芯片上的电阻器（166）。

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