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    • 1. 发明授权
    • Planarization of metal container structures
    • 金属容器结构的平面化
    • US06524912B1
    • 2003-02-25
    • US09653280
    • 2000-08-31
    • Sam YangJohn M. Drynan
    • Sam YangJohn M. Drynan
    • H01L218242
    • H01L21/76843H01L21/3212H01L21/7684H01L27/10852H01L27/10855H01L28/90H01L28/91H01L2924/0002H01L2924/00
    • A conductive material is provided in an opening formed in an insulative material. The process involves first forming a conductive material over at least a portion of the opening and over at least a portion of the insulative material which is outside of the opening. Next, a metal-containing fill material is formed over at least a portion of the conductive material which is inside the opening and which is also over the insulative material outside of the opening. The metal-containing material at least partially fills the opening. At least a portion of both the metal-containing fill material and the conductive material outside of the opening is then removed. Thereafter, at least a portion of the metal-containing fill material which is inside the opening is then removed.
    • 导电材料设置在形成于绝缘材料的开口中。 该方法包括首先在该开口的至少一部分上方和在该开口外部的至少一部分绝缘材料上形成导电材料。 接下来,在开口内部的导电材料的至少一部分上形成含金属填充材料,并且还在开口外部的绝缘材料上方。 含金属的材料至少部分地填充开口。 然后除去开口内部的含金属填充材料和导电材料的至少一部分。 此后,除去开口内部的含金属填充材料的至少一部分。
    • 5. 发明授权
    • Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers
    • 含有钌和钨的层的形成方法和集成电路结构
    • US07253076B1
    • 2007-08-07
    • US09590795
    • 2000-06-08
    • Vishnu K. AgarwalGaro DerderianGurtej S. SandhuWeimin M. LiMark VisokayCem BasceriSam Yang
    • Vishnu K. AgarwalGaro DerderianGurtej S. SandhuWeimin M. LiMark VisokayCem BasceriSam Yang
    • H01L21/20
    • H01L28/84H01L21/31637H01L28/55H01L28/65
    • Capacitors having increased capacitance include an enhanced-surface-area (rough-surfaced) electrically conductive layer or other layers that are compatible with the high-dielectric constant materials. In one approach, an enhanced-surface-area electrically conductive layer for such capacitors is formed by processing a ruthenium oxide layer at high temperature at or above 500° C. and low pressure 75 torr or below, most desirably 5 torr or below, to produce a roughened ruthenium layer having a textured surface with a mean feature size of at least about 100 Angstroms. The initial ruthenium oxide layer may be provided by chemical vapor deposition techniques or sputtering techniques or the like. The layer may be formed over an underlying electrically conductive layer. The processing may be performed in an inert ambient or in a reducing ambient. A nitrogen-supplying ambient or nitrogen-supplying reducing ambient may be used during the processing or afterwards to passivate the ruthenium for improved compatibility with high-dielectric-constant dielectric materials. Processing in an oxidizing ambient may also be performed to passivate the roughened layer. The roughened layer of ruthenium may be used to form an enhanced-surface-area electrically conductive layer. The resulting enhanced-surface-area electrically conductive layer may form a plate of a storage capacitor in an integrated circuit, such as in a memory cell of a DRAM or the like. In another approach, a tungsten nitride layer is provided as an first electrode of such a capacitor. The capacitor, or at least the tungsten nitride layer, is annealed to increase the capacitance of the capacitor.
    • 具有增加的电容的电容器包括增强的表面积(粗糙表面)导电层或与高介电常数材料相容的其它层。 在一种方法中,用于这种电容器的增强表面积导电层是通过在高温或高于500℃,低压75托或更低,最理想的5托或更低的高温下处理氧化钌层形成的, 产生具有至少约100埃的平均特征尺寸的纹理表面的粗糙钌层。 初始氧化钌层可以通过化学气相沉积技术或溅射技术等来提供。 该层可以形成在下面的导电层上。 处理可以在惰性环境或还原环境中进行。 可以在处理期间或之后使用供氮环境或供氮还原环境以钝化钌以改善与高介电常数电介质材料的相容性。 氧化环境中的处理也可以进行以钝化粗糙层。 可以使用粗糙化的钌层来形成增强表面积的导电层。 所形成的增强表面积导电层可以在诸如DRAM等的存储单元中的集成电路中形成存储电容器的板。 在另一种方法中,提供氮化钨层作为这种电容器的第一电极。 电容器或至少氮化钨层被退火以增加电容器的电容。