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1. 发明授权

US07648803B2 Diagonal corner-to-corner sub-resolution assist features for photolithography 有权
标题翻译：对角线角对角分辨率辅助光刻技术
公开(公告)号：US07648803B2
公开(公告)日：2010-01-19
申请号：US11390779
申请日：2006-03-27
申请人： Sam Sivakumar , Charles H. Wallace , Shannon E. Daviess
发明人： Sam Sivakumar , Charles H. Wallace , Shannon E. Daviess
IPC分类号： G03F1/00 , G06F17/50
CPC分类号： G03F1/36
摘要： Diagonal corner-to-corner sub-resolution assist features for use in photolithography are described. The diagonal features may be applied to one or a group of main features. Such features may be developed starting by synthesizing a photolithography mask having a first feature aligned along a linear axis and having a corner and a second feature aligned along a linear axis and having a corner, the corners of first and second features being separated from each other by a gap. The features may be developed by determining at least one diagonal line between the corners of the features to bridge the gap between the corners, applying a sub-resolution assist feature along the determined line, and modifying the synthesized photolithography mask to include the sub-resolution assist feature.
摘要翻译：描述了用于光刻的对角角对角分辨率辅助功能。对角线特征可以应用于一个或一组主要特征。可以通过合成具有沿线性轴线对准的第一特征并且具有沿直线轴线对准的角部和第二特征并具有拐角的光刻掩模开始形成这些特征，第一和第二特征的角部彼此分离有差距。特征可以通过确定特征的拐角之间的至少一个对角线来桥接角部之间的间隙，沿着确定的线施加子分辨率辅助特征，以及修改合成的光刻掩模以包括子分辨率辅助功能。

2. 发明授权

US06774037B2 Method integrating polymeric interlayer dielectric in integrated circuits 有权
标题翻译：在集成电路中集成聚合物层间电介质的方法
公开(公告)号：US06774037B2
公开(公告)日：2004-08-10
申请号：US10150617
申请日：2002-05-17
申请人： Makarem A. Hussein , Ruth Brain , Robert Turklot , Sam Sivakumar
发明人： Makarem A. Hussein , Ruth Brain , Robert Turklot , Sam Sivakumar
IPC分类号： H01L2144
CPC分类号： H01L21/76808 , H01L21/76814
摘要： A method of integrating a polymeric interlayer dielectric. The method comprises forming a dielectric layer comprising a polymer on a conductive layer formed on a substrate. A sacrificial hard mask is then formed on the dielectric layer. A first photoresist layer is then patterned on the sacrificial hard mask to define a first etched region, which is formed through the dielectric layer while substantially all of the first photoresist layer is removed. A sacrificial fill layer then covers the sacrificial hard mask and fills the first etched region. A second photoresist layer is patterned over the sacrificial fill layer to define a second etched region which is formed through the sacrificial fill layer and the dielectric layer while substantially all of the second photoresist layer and the sacrificial fill layer are simultaneously removed.
摘要翻译：一种整合聚合物层间电介质的方法。该方法包括在形成在基底上的导电层上形成包含聚合物的介电层。然后在电介质层上形成牺牲性硬掩模。然后在牺牲硬掩模上将第一光致抗蚀剂层图案化，以限定通过电介质层形成的第一蚀刻区域，同时基本上所有的第一光致抗蚀剂层被去除。牺牲填充层然后覆盖牺牲硬掩模并填充第一蚀刻区域。在牺牲填充层上图案化第二光致抗蚀剂层以限定通过牺牲填充层和介电层形成的第二蚀刻区域，同时基本上全部第二光致抗蚀剂层和牺牲填充层被去除。

3. 发明授权

US06329118B1 Method for patterning dual damascene interconnects using a sacrificial light absorbing material 有权
标题翻译：使用牺牲光吸收材料图案化双镶嵌互连的方法
公开(公告)号：US06329118B1
公开(公告)日：2001-12-11
申请号：US09422821
申请日：1999-10-21
申请人： Makarem A. Hussein , Sam Sivakumar
发明人： Makarem A. Hussein , Sam Sivakumar
IPC分类号： G03F7004
CPC分类号： H01L21/76808 , G03F7/091
摘要： An improved method of forming an integrated circuit, which includes forming a conductive layer on a substrate, then forming a dielectric layer on the conductive layer. After forming the dielectric layer, a layer of photoresist is patterned to define a region to be etched. A first etched region is then formed by removing a first portion of the dielectric layer. That first etched region is filled with a preferably light absorbing sacrificial material having dry etch properties similar to those of the dielectric layer. A second etched region is then formed by removing the sacrificial material and a second portion of the dielectric layer. This improved method may be used to make an integrated circuit that includes a dual damascene interconnect.
摘要翻译：一种形成集成电路的改进方法，其包括在衬底上形成导电层，然后在导电层上形成电介质层。在形成介电层之后，将一层光致抗蚀剂图案化以限定待蚀刻的区域。然后通过去除电介质层的第一部分来形成第一蚀刻区域。该第一蚀刻区域填充有具有与介电层类似的干蚀刻性质的优选光吸收牺牲材料。然后通过去除牺牲材料和介电层的第二部分来形成第二蚀刻区域。这种改进的方法可以用于制造包括双镶嵌互连的集成电路。

4. 发明授权

US07179570B2 Chromeless phase shift lithography (CPL) masks having features to pattern large area line/space geometries 失效
标题翻译：无色相移光刻（CPL）掩模，具有绘制大面积线/空间几何图形的特征
公开(公告)号：US07179570B2
公开(公告)日：2007-02-20
申请号：US11292885
申请日：2005-12-02
申请人： Sam Sivakumar , Paul Nyhus
发明人： Sam Sivakumar , Paul Nyhus
IPC分类号： G03F1/00
CPC分类号： G03F1/34
摘要： A chromeless phase shift lithography (CPL) mask is described herein. The CPL mask includes a reticle having a phase-shifting feature pattern to produce a projected aerial image for patterning one or more large resist areas on a semiconductor substrate. The phase-shifting feature pattern includes an inner pattern comprising a plurality of phase-shifting features interspersed with non-phase-shifting areas. The phase-shifting features and the non-phase-shifting areas are arranged in a substantially alternating two-dimensional pattern surrounded by a substantially-filled phase-shifting peripheral area having a perimeter forming a pattern outline that is similar to an outline of the one or more large resist areas. Light that passes through the phase-shifting features and the phase-shifting peripheral area is phase-shifted by approximately 180 degrees from light passing through the non-phase-shifting areas of the CPL mask.
摘要翻译：本文描述了无色相移光刻（CPL）掩模。 CPL掩模包括具有相移特征图案的掩模版，以产生用于对半导体衬底上的一个或多个较大抗蚀剂区域进行构图的投射空间图像。相移特征图案包括包括散布有非相移区域的多个相移特征的内部图案。相移特征和非相移区域布置成基本上交替的二维图案，其被具有周边的基本上填充的相移周边区域包围，该周边形成图案轮廓，该图案轮廓类似于该轮廓的轮廓或更大的抗蚀剂区域。通过相移特征和相移周边区域的光从通过CPL掩模的非相移区域的光相移大约180度。

5. 发明授权

US07056645B2 Use of chromeless phase shift features to pattern large area line/space geometries 失效
标题翻译：使用无色相移特征来绘制大面积线/空间几何图形
公开(公告)号：US07056645B2
公开(公告)日：2006-06-06
申请号：US10305921
申请日：2002-11-27
申请人： Sam Sivakumar , Paul Nyhus
发明人： Sam Sivakumar , Paul Nyhus
IPC分类号： G03F7/20 , G03F7/16 , H01L21/027 , H01L21/441
CPC分类号： G03F1/34
摘要： Method for using chromeless phase shift lithography (CPL) masks to pattern large line/space geometries. The method comprises using light at a wavelength of one of 248 nm, 193 nm, or 157 nm to illumimate a CPL mask comprising a reticle having a plurality of phase-shifting features interspersed with non-phase-shifting areas arranged in a substantially alternating two-dimensional pattern. When light passes through the phase-shifting features it is phase-shifted relative to light passing through the non-phase-shifting areas of the CPL mask. The phase-shifted light and non-phase-shifted light passing through the reticle are then projected onto a resist layer applied over a semiconductor substrate. The resultant composite aerial image intensity distribution is such that an area of the resist having a shape defined by a periphery of a corresponding pattern of phase-shifting features is sufficiently exposed to pattern a large area feature in the resist. Subsequent semiconductor processing operations may then be performed to pattern a corresponding feature on the semiconductor substrate.
摘要翻译：使用无色相移光刻（CPL）掩模来绘制大线/空间几何的方法。该方法包括使用波长为248nm，193nm或157nm波长的光照亮包括具有多个相移特征的掩模版的CPL掩模，所述相移特征散布有以基本上交替的两个布置的非相移区域维度模式。当光通过相移特征时，它相对于穿过CPL掩模的非相移区域的光相移。然后通过掩模版的相移光和非相移光被投影到施加在半导体衬底上的抗蚀剂层上。所得到的复合空间图像强度分布使得具有由相移的相移特征图案的周边限定的形状的抗蚀剂的面积充分暴露于抗蚀剂中的大面积特征图案。随后可以执行随后的半导体处理操作以对半导体衬底上的对应特征进行图案化。

6. 发明授权

US06350670B1 Method for making a semiconductor device having a carbon doped oxide insulating layer 有权
标题翻译：制造具有碳掺杂氧化物绝缘层的半导体器件的方法
公开(公告)号：US06350670B1
公开(公告)日：2002-02-26
申请号：US09465654
申请日：1999-12-17
申请人： Ebrahim Andideh , Sam Sivakumar , Larry Wong
发明人： Ebrahim Andideh , Sam Sivakumar , Larry Wong
IPC分类号： H01L214763
CPC分类号： H01L21/76802 , H01L21/02126 , H01L21/02274 , H01L21/02362 , H01L21/31633 , H01L21/76801 , H01L21/76807
摘要： An improved method of forming a semiconductor device that has a carbon doped oxide insulating layer. The method comprises forming a first insulating layer that includes a carbon doped oxide, then forming on the surface of the first insulating layer a second insulating layer that comprises silicon dioxide.
摘要翻译：一种形成具有碳掺杂氧化物绝缘层的半导体器件的改进方法。该方法包括形成包括碳掺杂氧化物的第一绝缘层，然后在第一绝缘层的表面上形成包含二氧化硅的第二绝缘层。

7. 发明授权

US07374865B2 Methods to pattern contacts using chromeless phase shift masks 有权
标题翻译：使用无色相位掩模对触点进行图案化的方法
公开(公告)号：US07374865B2
公开(公告)日：2008-05-20
申请号：US10304303
申请日：2002-11-25
申请人： Paul Nyhus , Sam Sivakumar
发明人： Paul Nyhus , Sam Sivakumar
IPC分类号： G03F7/20 , G03F7/40
CPC分类号： G03F1/34
摘要： Method for using chromeless phase shift lithography (CPL) masks to pattern contacts on semiconductor substrates and corresponding CPL masks for performing the method. The method for patterning contacts includes illuminating a CPL mask comprising a reticle having a plurality of phase-shifting features interspersed with non-phase-shifting areas using a short wavelength UV light source, wherein the phase-shifting features are configured in a pattern corresponding to a target pattern of the contacts on the semiconductor substrate. Phase-shifted and non-phase-shifted light passing through the reticle are projected as an aerial image onto a layer of a negative tone resist applied over the semiconductor substrate to pattern the contacts in the resist. The phase-shifting features are recesses which cause light passing therethrough to be phase-shifted by approximately 180° from light passing through non-phase-shifting areas of the mask. Each recess in the CPL mask is used to pattern a separate contact on the semiconductor substrate.
摘要翻译：使用无色相移光刻（CPL）掩模对半导体衬底上的触点进行图案化和用于执行该方法的相应CPL掩模的方法。用于图案化接触的方法包括使用短波长UV光源照射包括具有散布有非相移区域的多个相移特征的掩模版的CPL掩模，其中相移特征被配置为对应于半导体衬底上的触点的目标图案。将穿过光罩的相移和非相移光作为空间图像投影到施加在半导体衬底上的负色调抗蚀剂层上以对抗蚀剂中的触点进行图案化。相移特征是使通过其的光从通过掩模的非相移区域的光相移大约180°的凹部。 CPL掩模中的每个凹槽用于对半导体衬底上的单独接触进行图案化。

8. 发明授权

US06649515B2 Photoimageable material patterning techniques useful in fabricating conductive lines in circuit structures 有权
标题翻译：可用于制造电路结构中的导线的可光成像材料图案化技术
公开(公告)号：US06649515B2
公开(公告)日：2003-11-18
申请号：US09164508
申请日：1998-09-30
申请人： Peter K. Moon , Makarem A. Hussein , Alan Myers , Charles Recchia , Sam Sivakumar , Angelo Kandas
发明人： Peter K. Moon , Makarem A. Hussein , Alan Myers , Charles Recchia , Sam Sivakumar , Angelo Kandas
IPC分类号： H01L214763
CPC分类号： H01L21/76808 , H01L21/76834
摘要： A method of forming an interconnection including the steps of depositing a first masking material over a first conductive region of an integrated circuit substrate and depositing a dielectric material over the first masking material. The method also includes forming a via through the dielectric material to expose the first masking material and a second masking material is deposited in a portion of the via. A trench is formed in the dielectric material over a portion of the via and the second masking material is removed from the via. The via is then extended through the first masking material and a conductive material is deposited in the via.
摘要翻译：一种形成互连的方法，包括以下步骤：在集成电路基板的第一导电区域上沉积第一掩模材料，并在第一掩模材料上沉积电介质材料。该方法还包括通过介电材料形成通孔以暴露第一掩模材料，并且第二掩蔽材料沉积在通孔的一部分中。在通孔的一部分上的电介质材料中形成沟槽，并且从通孔去除第二掩模材料。然后将通孔延伸穿过第一掩模材料，并且导电材料沉积在通孔中。

9. 发明授权

US06365529B1 Method for patterning dual damascene interconnects using a sacrificial light absorbing material 有权
标题翻译：使用牺牲光吸收材料图案化双镶嵌互连的方法
公开(公告)号：US06365529B1
公开(公告)日：2002-04-02
申请号：US09501354
申请日：2000-02-09
申请人： Makarem A. Hussein , Sam Sivakumar
发明人： Makarem A. Hussein , Sam Sivakumar
IPC分类号： H01L2131
CPC分类号： H01L21/76808 , G03F7/091
摘要： An improved method of forming an integrated circuit, which includes forming a conductive layer on a substrate, then forming a dielectric layer on the conductive layer. After forming the dielectric layer, a layer of photoresist is patterned to define a region to be etched. A first etched region is then formed by removing a first portion of the dielectric layer. That first etched region is filled with a preferably light absorbing sacrificial material having dry etch properties similar to those of the dielectric layer. A second etched region is then formed by removing the sacrificial material and a second portion of the dielectric layer. This improved method may be used to make an integrated circuit that includes a dual damascene interconnect.
摘要翻译：一种形成集成电路的改进方法，其包括在衬底上形成导电层，然后在导电层上形成电介质层。在形成介电层之后，将一层光致抗蚀剂图案化以限定待蚀刻的区域。然后通过去除电介质层的第一部分来形成第一蚀刻区域。该第一蚀刻区域填充有具有与介电层类似的干蚀刻性质的优选光吸收牺牲材料。然后通过去除牺牲材料和介电层的第二部分来形成第二蚀刻区域。这种改进的方法可以用于制造包括双镶嵌互连的集成电路。

10. 发明授权

US6037255A Method for making integrated circuit having polymer interlayer dielectric 有权
标题翻译：制造具有聚合物层间电介质的集成电路的方法
公开(公告)号：US6037255A
公开(公告)日：2000-03-14
申请号：US310656
申请日：1999-05-12
申请人： Makarem A. Hussein , Sam Sivakumar , Rick Davis
发明人： Makarem A. Hussein , Sam Sivakumar , Rick Davis
IPC分类号： H01L21/312 , H01L21/768 , H01L21/283
CPC分类号： H01L21/76801 , H01L21/76807 , H01L21/312
摘要： An improved method for making an integrated circuit that includes forming a conductive layer on a substrate, then forming a dielectric layer comprising a polymer on the conductive layer. After forming the dielectric layer, a layer of photoresist is patterned to define a region to be etched. An etched region is then formed through the dielectric layer while simultaneously removing the layer of photoresist.
摘要翻译：一种用于制造集成电路的改进方法，包括在衬底上形成导电层，然后在导电层上形成包含聚合物的电介质层。在形成介电层之后，将一层光致抗蚀剂图案化以限定待蚀刻的区域。然后通过电介质层形成蚀刻区域，同时去除光致抗蚀剂层。

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