会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 3. 发明授权
    • Rapid sample exchange for miniaturized NMR spectrometer
    • 用于小型化NMR光谱仪的快速样品交换
    • US08754646B2
    • 2014-06-17
    • US13171230
    • 2011-06-28
    • John C. PriceCharles MillerErick Winston
    • John C. PriceCharles MillerErick Winston
    • G01V3/00
    • G01R33/307G01R33/302G01R33/445
    • A method is provided for acquiring multiple NMR response signal data in rapid succession for averaging NMR spectral data from a sample. The fluid sample is placed in a capillary that extends through the magnetic field of the NMR spectrometer, including through the center of the magnetic field to place a segment of the sample in the magnetic center. After the sample fluid, initially magnetized by the magnetic field, is activated to emit an NMR pulse signal, the fluid in the capillary is advanced rapidly to put another pre-magnetized segment of the sample fluid in the fluid center, acquiring an NRM pulse signal, and continuing the cycle until a desired number of NMR response data signals from the sample have been acquired. Those response data from multiple acquisitions are then averaged.
    • 提供一种快速连续获取多个NMR响应信号数据的方法,用于对来自样品的NMR光谱数据进行平均。 将流体样品置于穿过NMR光谱仪的磁场的毛细管中,包括通过磁场的中心,将样品的一段放置在磁性中心。 在初始被磁场磁化的样品流体被激活以发射NMR脉冲信号之后,毛细管中的流体被快速前进,以将样品流体的另一个预先磁化的区段放在流体中心,获得NRM脉冲信号 并继续循环,直到获得了来自样品的所需数量的NMR响应数据信号。 然后对来自多次获取的响应数据进行平均。
    • 5. 发明申请
    • Method and apparatus for Terminating A Test Signal Applied To Multiple Semiconductor Loads Under Test
    • 用于终止被测试的多个半导体负载的测试信号的方法和装置
    • US20100253374A1
    • 2010-10-07
    • US12416375
    • 2009-04-01
    • Guang ChenCharles MillerDavid Pritzkau
    • Guang ChenCharles MillerDavid Pritzkau
    • G01R31/02G01R31/26
    • G01R31/31905
    • Apparatus for terminating a test signal applied to multiple semiconductor loads under test is described—for example apparatus for interfacing a test signal between a tester and a semiconductor device under test (DUT). In some examples, a probe card assembly may include at least one probe substrate each having test probes configured to contact test features of a DUT; a wiring substrate, coupled to the at least one probe substrate, having a connector configured for coupling with a source termination of a tester; a signal path formed on and/or in the wiring substrate and the at least one probe substrate, the signal path having a trace and trace stubs fanning out from the trace, an input of the trace being coupled to the connector and outputs of the trace stubs being coupled to the test probes; and a resistive termination coupled between the trace and at least one potential.
    • 描述了用于终止施加到被测试的多个半导体负载的测试信号的装置,例如用于在测试器和待测半导体器件(DUT)之间接合测试信号的装置。 在一些示例中,探针卡组件可以包括至少一个探针基板,每个探针基板具有被配置为接触DUT的测试特征的测试探针; 耦合到所述至少一个探针衬底的布线衬底,具有被配置为与测试器的源端接耦合的连接器; 形成在布线基板和至少一个探针基板上和/或布线基板和至少一个探针基板上的信号路径,该信号路径具有从迹线扇出的迹线和迹线短线,迹线的输入耦合到连接器和迹线的输出 桩被耦合到测试探针; 以及耦合在迹线和至少一个电位之间的电阻终端。
    • 7. 发明申请
    • TESTER CHANNEL TO MULTIPLE IC TERMINALS
    • TESTER通道到多个IC端子
    • US20080010814A1
    • 2008-01-17
    • US11779163
    • 2007-07-17
    • Charles Miller
    • Charles Miller
    • H01R43/00H01C17/00H05K3/30
    • G01R1/07378G01R3/00G01R31/2889G01R31/31723G01R31/318511G01R31/31905G01R31/31926Y10T29/49082Y10T29/49126Y10T29/4913
    • A probe card provides signal paths between integrated circuit (IC) tester channels and probes accessing input and output pads of ICs to be tested. When a single tester channel is to access multiple (N) IC pads, the probe card provides a branching path linking the channel to each of the N IC input pads. Each branch of the test signal distribution path includes a resistor for isolating the IC input pad accessed via that branch from all other branches of the path so that a fault on that IC pad does not substantially affect the voltage of signals appearing on any other IC pad. When a single tester channel is to monitor output signals produced at N IC pads, the resistance in each branch of the signal path linking the pads of the tester channel is uniquely sized to that the voltage of the input signal supplied to the tester channel is a function of the combination of logic states of the signals produced at the N IC pads. The tester channel measures the voltage of its input signal so that the logic state of the signals produced at each of the N IC output pads can be determined from the measured voltage.
    • 探针卡提供集成电路(IC)测试仪通道之间的信号路径,以及访问要测试的IC的输入和输出焊盘的探头。 当单个测试仪通道要访问多个(N)个IC焊盘时,探针卡提供将通道连接到每个N个IC输入焊盘的分支路径。 测试信号分配路径的每个分支包括用于隔离通过该分支从该路径的所有其他分支访问的IC输入焊盘的电阻器,使得该IC焊盘上的故障基本上不影响出现在任何其它IC焊盘上的信号的电压 。 当单个测试仪通道用于监视在N个IC焊盘处产生的输出信号时,连接测试仪通道的焊盘的信号路径的每个分支中的电阻的唯一尺寸是使提供给测试仪通道的输入信号的电压为 在N个IC焊盘上产生的信号的逻辑状态的组合的功能。 测试仪通道测量其输入信号的电压,使得可以根据测量的电压确定在每个N IC输出焊盘处产生的信号的逻辑状态。
    • 10. 发明申请
    • Isolation Buffers With Controlled Equal Time Delays
    • 具有受控相等时间延迟的隔离缓冲器
    • US20070103183A1
    • 2007-05-10
    • US11615976
    • 2006-12-24
    • Charles Miller
    • Charles Miller
    • G01R31/26
    • H03H11/265G01R31/2889G01R31/31917H03H11/126
    • A system is provided for controlling the delay in an isolation buffer. Multiple such isolation buffers are used to connect a single signal channel to multiple lines and controlled to provide an equal delay. Isolation buffer delay is controlled to be uniform by varying either power supply voltage or current. A single delay control circuit forming a delay-lock loop supplies the delay control signal to each buffer to assure the uniform delay. Since controlling delay can also vary the output voltage of each isolation buffer, in one embodiment buffers are made from two series inverters: one with a variable delay, and the second without a variable delay providing a fixed output voltage swing. To reduce circuitry needed, in one embodiment an isolation buffer with a variable power supply is provided in a channel prior to a branch, while buffers having a fixed delay are provided in each branch. A wafer test system can be configured using the isolation buffers having equal delays to enable concurrently connecting one tester channel to multiple wafer test probes.
    • 提供了一种用于控制隔离缓冲器中的延迟的系统。 多个这样的隔离缓冲器用于将单个信号信道连接到多个线路并被控制以提供相等的延迟。 通过改变电源电压或电流来将隔离缓冲器延迟控制为均匀。 形成延迟锁定环的单个延迟控制电路将延迟控制信号提供给每个缓冲器,以确保均匀延迟。 由于控制延迟也可以改变每个隔离缓冲器的输出电压,在一个实施例中,缓冲器由两个串联的反相器制成:一个具有可变延迟,第二个不具有可变延迟,提供固定的输出电压摆幅。 为了减少所需的电路,在一个实施例中,在分支之前的通道中提供具有可变电源的隔离缓冲器,而在每个分支中提供具有固定延迟的缓冲器。 可以使用具有相等延迟的隔离缓冲器来配置晶片测试系统,以使得能够将一个测试仪通道同时连接到多个晶片测试探针。