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1. 发明授权

US6073210A Synchronization of weakly ordered write combining operations using a fencing mechanism 失效
标题翻译：使用栅栏机制同步弱序写入组合操作
公开(公告)号：US6073210A
公开(公告)日：2000-06-06
申请号：US53377
申请日：1998-03-31
申请人： Salvador Palanca , Vladimir Pentkovski , Subramaniam Maiyuran , Lance Hacking , Roger A. Golliver , Shreekant S. Thakkar
发明人： Salvador Palanca , Vladimir Pentkovski , Subramaniam Maiyuran , Lance Hacking , Roger A. Golliver , Shreekant S. Thakkar
IPC分类号： G06F12/08 , G06F13/16 , G06F13/14 , G06F12/00
CPC分类号： G06F13/1631 , G06F12/0802
摘要： The present invention discloses a method and apparatus for synchronizing weakly ordered write combining operations. A memory controller has a buffer to service memory accesses. A store fence instruction is dispatched to the memory controller. If the buffer contains at least a data written by at least one of the weakly ordered write combining operations prior to the store fence instruction, then the store fence instruction is blocked until a block in the buffer containing the data is globally observed. If the buffer does not contain any data written by at least one of the write combining operations prior to the store fence instruction, then the store fence instruction is accepted by the memory controller.
摘要翻译：本发明公开了一种用于使弱顺序的写入组合操作同步的方法和装置。存储器控制器具有用于服务存储器访问的缓冲器。存储栏指令被发送到存储器控制器。如果缓冲区至少包含由存储栏指令之前的弱顺序写入组合操作中的至少一个写入的数据，则存储栅栏指令被阻止，直到包含数据的缓冲区中的块被全局观察到。如果在存储栏指令之前缓冲器不包含写入组合操作中的至少一个写入的任何数据，则存储器控制器接受存储栅栏指令。

2. 发明授权

US06801208B2 System and method for cache sharing 有权
标题翻译：用于缓存共享的系统和方法
公开(公告)号：US06801208B2
公开(公告)日：2004-10-05
申请号：US09750750
申请日：2000-12-27
申请人： Jagganath Keshava , Vladimir Pentkovski , Subramaniam Maiyuran , Salvador Palanca , Hsin-Chu Tsai
发明人： Jagganath Keshava , Vladimir Pentkovski , Subramaniam Maiyuran , Salvador Palanca , Hsin-Chu Tsai
IPC分类号： G09G536
CPC分类号： G06F3/14 , G06F12/084 , G09G5/001 , G09G5/393 , G09G2330/021 , G09G2350/00
摘要： A system and method for cache sharing. The system is a microprocessor comprising a processor core and a graphics engine, each coupled to a cache memory. The microprocessor also includes a driver to direct how the cache memory is shared by the processor core and the graphics engine. The method comprises receiving a memory request from a graphics application program and determining whether a cache memory that may be shared between a processor core and a cache memory is available to be shared. If the cache memory is available to be shared, a first portion of the cache memory is allocated to the processor core and a second portion of the cache memory is allocated to the graphics engine. The method and microprocessor may be included in a computing device.
摘要翻译：一种用于缓存共享的系统和方法。该系统是包括处理器核心和图形引擎的微处理器，每个耦合到高速缓冲存储器。微处理器还包括一个驱动程序，用于指示高速缓冲存储器如何由处理器核心和图形引擎共享。该方法包括从图形应用程序接收存储器请求并确定可以在处理器核心和高速缓冲存储器之间共享的高速缓存存储器是否可共享。如果高速缓冲存储器可用于共享，则高速缓冲存储器的第一部分被分配给处理器核心，高速缓冲存储器的第二部分被分配给图形引擎。方法和微处理器可以包括在计算设备中。

3. 发明授权

US06643745B1 Method and apparatus for prefetching data into cache 失效
标题翻译：将数据预取到高速缓存中的方法和装置
公开(公告)号：US06643745B1
公开(公告)日：2003-11-04
申请号：US09053383
申请日：1998-03-31
申请人： Salvador Palanca , Niranjan L. Cooray , Angad Narang , Vladimir Pentkovski , Steve Tsai , Subramaniam Maiyuran , Jagannath Keshava , Hsien-Hsin Lee , Steve Spangler , Suresh Kuttuva , Praveen Mosur
发明人： Salvador Palanca , Niranjan L. Cooray , Angad Narang , Vladimir Pentkovski , Steve Tsai , Subramaniam Maiyuran , Jagannath Keshava , Hsien-Hsin Lee , Steve Spangler , Suresh Kuttuva , Praveen Mosur
IPC分类号： G06F1200
CPC分类号： G06F9/383 , G06F9/3842 , G06F12/0862 , G06F12/0897 , G06F2212/6028
摘要： A computer system is disclosed. The computer system includes a higher level cache, a lower level cache, a decoder to decode instructions, and a circuit coupled to the decoder. In one embodiment, the circuit, in response to a single decoded instruction, retrieves data from external memory and bypasses the lower level cache upon a higher level cache miss. In another embodiment, the circuit, in response to a first decoded instruction, issues a request to retrieve data at an address from external memory to place said data only in the lower level cache, detects a second cacheable decoded instruction to said address, and places said data in the higher level cache.
摘要翻译：公开了一种计算机系统。计算机系统包括较高级别的缓存，较低级别的缓存，解码指令的解码器以及耦合到解码器的电路。在一个实施例中，电路响应于单个解码的指令，在较高级别的高速缓存未命中时从外部存储器检索数据并绕过下一级高速缓存。在另一个实施例中，电路响应于第一解码指令发出从外部存储器的地址检索数据的请求，以将所述数据仅放置在较低级别的高速缓存中，检测到所述地址的第二可缓存解码指令，表示高级缓存中的数据。

4. 发明授权

US6122715A Method and system for optimizing write combining performance in a shared buffer structure 失效
标题翻译：用于优化共享缓冲区结构中的写入组合性能的方法和系统
公开(公告)号：US6122715A
公开(公告)日：2000-09-19
申请号：US053384
申请日：1998-03-31
申请人： Salvador Palanca , Vladimir Pentkovski , Niranjan L. Cooray , Subramaniam Maiyuran , Angad Narang
发明人： Salvador Palanca , Vladimir Pentkovski , Niranjan L. Cooray , Subramaniam Maiyuran , Angad Narang
IPC分类号： G06F12/08 , G06F5/06
CPC分类号： G06F12/0804
摘要： An apparatus and method of optimizing write combining operations using write combining buffers. A plurality of control fields are assigned to each of the write combining buffers. Each of the control fields has a value corresponding to one of a plurality of write combining states. A first of the plurality of write combining states transitions to a second of the plurality of write combining states in response to a write combining operation.
摘要翻译：一种使用写入组合缓冲器优化写入组合操作的装置和方法。多个控制字段被分配给每个写合并缓冲器。每个控制字段具有对应于多个写合并状态之一的值。多个写入组合状态中的第一个响应写入组合操作转换到多个写入组合状态中的第二个。

5. 发明授权

US06205520B1 Method and apparatus for implementing non-temporal stores 失效
标题翻译：用于实施非时间存储的方法和装置
公开(公告)号：US06205520B1
公开(公告)日：2001-03-20
申请号：US09053387
申请日：1998-03-31
申请人： Salvador Palanca , Vladimir Pentkovski , Steve Tsai , Subramaniam Maiyuran
发明人： Salvador Palanca , Vladimir Pentkovski , Steve Tsai , Subramaniam Maiyuran
IPC分类号： G06F1200
CPC分类号： G06F9/3824 , G06F9/3842 , G06F12/0804 , G06F12/0888 , G06F12/0897
摘要： A processor is disclosed. The processor includes a decoder to decode instructions and a circuit, in response to a decoded instruction, detects an incoming write back or write through streaming store instruction that misses a cache and allocates a buffer in write combining mode. The circuit, in response to a second decoded instruction, detects either an uncacheable speculative write combining store instruction or a second write back streaming store or write through streaming store instruction that hits the buffer and merges the second decoded instruction with the buffer.
摘要翻译：公开了一种处理器。处理器包括解码器，用于对指令和电路进行解码，响应于解码的指令，通过错过高速缓冲存储器的流存储指令检测进入写回或写入，并以写入合并模式分配缓冲器。响应于第二解码指令，该电路检测不可缓存的推测写入组合存储指令或第二回写流存储器，或通过命中缓冲器的流存储指令进行写入，并将第二解码指令与缓冲器合并。

6. 发明授权

US06970994B2 Executing partial-width packed data instructions 有权
标题翻译：执行部分宽度打包的数据指令
公开(公告)号：US06970994B2
公开(公告)日：2005-11-29
申请号：US09852217
申请日：2001-05-08
申请人： Mohammad Abdallah , James Coke , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
发明人： Mohammad Abdallah , James Coke , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
IPC分类号： G06F9/30 , G06F9/302 , G06F9/318
CPC分类号： G06F9/3875 , G06F9/30014 , G06F9/30036 , G06F9/30112 , G06F9/3013 , G06F9/30134 , G06F9/30145 , G06F9/30167 , G06F9/3017 , G06F9/30181 , G06F9/30196 , G06F9/384 , G06F9/3885
摘要： A method and apparatus for executing partial-width packed data instructions are discussed. The processor may include a plurality of registers, a register renaming unit, a decoder, and a partial-width execution unit. The register renaming unit provides an architectural register file to store packed data operands each of which include a plurality of data elements. The decoder is to decode a first and second set of instructions that each specify one or more registers in the architectural register file. The first set of instructions specify operations to be performed on all of the data elements stored in the one or more specified registers. In contrast, the second set of instructions specify operations to be performed on only a subset of the data elements. The partial-width execution unit is to execute operations specified by either of the first or the second set of instructions.
摘要翻译：讨论了用于执行部分宽度打包数据指令的方法和装置。处理器可以包括多个寄存器，寄存器重命名单元，解码器和部分宽度执行单元。寄存器重命名单元提供架构寄存器文件以存储打包数据操作数，每个数据操作数包括多个数据元素。解码器是对第一和第二组指令进行解码，每组指令在架构寄存器文件中指定一个或多个寄存器。第一组指令指定要对存储在一个或多个指定寄存器中的所有数据元素执行的操作。相比之下，第二组指令指定仅对数据元素的子集执行的操作。部分宽度执行单元是执行由第一组或第二组指令指定的操作。

7. 发明授权

US5995122A Method and apparatus for parallel conversion of color values from a single precision floating point format to an integer format 失效
标题翻译：将颜色值从单精度浮点格式并行转换为整数格式的方法和装置
公开(公告)号：US5995122A
公开(公告)日：1999-11-30
申请号：US71468
申请日：1998-04-30
申请人： Hsien-Cheng E. Hsieh , Thomas R. Huff , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
发明人： Hsien-Cheng E. Hsieh , Thomas R. Huff , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
IPC分类号： H03M7/24 , G06F13/00 , G06F15/80
CPC分类号： H03M7/24
摘要： A method and apparatus for parallel processing of graphics data are described. A number of color components are stored in a floating point format in at least one register of a set of 128-bit registers in a packed format. The color components in the floating point format are converted to numbers in an integer format. The numbers in the integer format are placed in at least one register of a set of 64-bit registers in the packed format. Color components are assembled for image pixels from the numbers in the integer format.
摘要翻译：描述用于并行处理图形数据的方法和装置。多个颜色分量以压缩格式在一组128位寄存器的至少一个寄存器中以浮点格式存储。浮点格式的颜色分量将以整数格式转换为数字。整数格式的数字以打包格式放置在一组64位寄存器的至少一个寄存器中。从整数格式的数字组装图像像素的颜色分量。

8. 发明授权

US07467286B2 Executing partial-width packed data instructions 有权
标题翻译：执行部分宽度打包的数据指令
公开(公告)号：US07467286B2
公开(公告)日：2008-12-16
申请号：US11126049
申请日：2005-05-09
申请人： Mohammad Abdallah , James Coke , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
发明人： Mohammad Abdallah , James Coke , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
IPC分类号： H04Q3/00
CPC分类号： G06F9/3875 , G06F9/30014 , G06F9/30036 , G06F9/30112 , G06F9/3013 , G06F9/30134 , G06F9/30145 , G06F9/30167 , G06F9/3017 , G06F9/30181 , G06F9/30196 , G06F9/384 , G06F9/3885
摘要： A method and apparatus are provided for executing packed data instructions. According to one aspect of the invention, a processor includes registers, a register renaming unit coupled to the registers, a decoder coupled to the register renaming unit, and a partial-width execution unit coupled to the decoder. The register renaming unit provides an architectural register file to store packed data operands that include data elements. The decoder is to decode a first and second set of instructions that each specify one or more registers in the architectural register file. Each of the instructions in the first set specify operations to be performed on all of the data elements. In contrast, each of the instructions in the second set specify operations to be performed on only a subset of the data elements. The partial-width execution unit is to execute operations specified by either the first or second set of instructions.
摘要翻译：提供了一种用于执行打包数据指令的方法和装置。根据本发明的一个方面，处理器包括寄存器，耦合到寄存器的寄存器重命名单元，耦合到寄存器重命名单元的解码器以及耦合到解码器的部分宽度执行单元。寄存器重命名单元提供架构寄存器文件来存储包括数据元素的打包数据操作数。解码器是对第一和第二组指令进行解码，每组指令在架构寄存器文件中指定一个或多个寄存器。第一组中的每个指令指定要对所有数据元素执行的操作。相比之下，第二组中的每个指令指定仅对数据元素的子集执行的操作。部分宽度执行单元是执行由第一组或第二组指令指定的操作。

9. 发明授权

US06275904B1 Cache pollution avoidance instructions 失效
标题翻译：缓存污染回避说明
公开(公告)号：US06275904B1
公开(公告)日：2001-08-14
申请号：US09053385
申请日：1998-03-31
申请人： Srinivas Chennupaty , Shreekant S. Thakkar , Thomas Huff , Vladimir Pentkovski
发明人： Srinivas Chennupaty , Shreekant S. Thakkar , Thomas Huff , Vladimir Pentkovski
IPC分类号： G06F1208
CPC分类号： G06F12/0886 , G06F9/30018 , G06F9/30036 , G06F9/30047 , G06F12/0804 , G06F12/0888
摘要： A computer system and method for providing cache memory management. The computer system comprises a main memory having a plurality of main memory addresses each having a corresponding data entry, and a processor coupled to the main memory. At least one cache memory is coupled to the processor. The at least one cache memory has a cache directory with a plurality of addresses and a cache controller having a plurality of data entries corresponding to the plurality of addresses. The processor receives an instruction having an operand address and determines if the operand address matches one of the plurality of addresses in the cache directory. If so, the processor updates a data entry in the cache controller corresponding to the matched address. Otherwise, a data entry corresponding to the operand address in the main memory is updated.
摘要翻译：一种用于提供高速缓存存储器管理的计算机系统和方法。计算机系统包括具有多个主存储器地址的主存储器，每个主存储器地址都具有对应的数据条目，以及耦合到主存储器的处理器。至少一个高速缓存存储器耦合到处理器。所述至少一个高速缓冲存储器具有具有多个地址的高速缓存目录和具有对应于所述多个地址的多个数据条目的高速缓存控制器。处理器接收具有操作数地址的指令，并确定操作数地址是否匹配高速缓存目录中的多个地址之一。如果是这样，则处理器更新对应于匹配地址的高速缓存控制器中的数据条目。否则，更新与主存储器中的操作数地址相对应的数据条目。

10. 发明授权

US06266769B1 Conversion between packed floating point data and packed 32-bit integer data in different architectural registers 失效
公开(公告)号：US06266769B1
公开(公告)日：2001-07-24
申请号：US09070891
申请日：1998-04-30
申请人： Mohammad A. F. Abdallah , Hsien-Cheng E. Hsieh , Thomas R. Huff , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
发明人： Mohammad A. F. Abdallah , Hsien-Cheng E. Hsieh , Thomas R. Huff , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
IPC分类号： G06F900
CPC分类号： H03M7/24
摘要： A method and instruction for converting a number between a floating point format and an integer format are described. Numbers are stored in the integer format in a register of a first set of architectural registers in a packed format. At least one of the numbers in the integer format is converted to at least one number in the floating point format. The numbers in the floating point format are placed in a register of a second set of architectural registers in a packed format.

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