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1. 发明授权

US06838769B1 Dual damascene bond pad structure for lowering stress and allowing circuitry under pads 有权
标题翻译：双镶嵌结合垫结构，用于降低压力并允许垫下的电路
公开(公告)号：US06838769B1
公开(公告)日：2005-01-04
申请号：US09465089
申请日：1999-12-16
申请人： Sailesh Chittipeddi , William Thomas Cochran , Yehuda Smooha
发明人： Sailesh Chittipeddi , William Thomas Cochran , Yehuda Smooha
IPC分类号： H01L21/60 , H01L21/768 , H01L23/485 , H01L23/532 , H01L29/40 , H01L23/52
CPC分类号： H01L24/48 , H01L21/76807 , H01L23/53209 , H01L24/05 , H01L24/11 , H01L2224/0401 , H01L2224/04042 , H01L2224/05093 , H01L2224/05096 , H01L2224/05166 , H01L2224/05187 , H01L2224/05546 , H01L2224/05554 , H01L2224/05556 , H01L2224/05624 , H01L2224/05647 , H01L2224/05684 , H01L2224/13099 , H01L2224/48463 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01082 , H01L2924/04941 , H01L2924/04953 , H01L2924/10253 , H01L2924/14 , H01L2224/45099 , H01L2924/00
摘要： A bond pad is located over active circuitry formed within an integrated circuit device. A barrier film forms the bottom surface of the upper portion of a bond pad opening which also includes vias extending through the bottom surface to form a dual damascene structure. The bond pad is resistant to stress effects such as cracking, which can be produced when bonding an external wire to the bond pad, and therefore prevents leakage currents between the bond pads and the underlying circuitry.
摘要翻译：接合焊盘位于集成电路器件内形成的有源电路上。阻挡膜形成接合焊盘开口的上部的底表面，其还包括延伸穿过底表面的通孔以形成双镶嵌结构。接合焊盘抵抗诸如开裂的应力作用，当将外部导线接合到接合焊盘时可以产生裂纹，因此防止接合焊盘和下面的电路之间的漏电流。

2. 发明授权

US06417087B1 Process for forming a dual damascene bond pad structure over active circuitry 有权
标题翻译：用于在有源电路上形成双镶嵌键合焊盘结构的工艺
公开(公告)号：US06417087B1
公开(公告)日：2002-07-09
申请号：US09465075
申请日：1999-12-16
申请人： Sailesh Chittipeddi , William Thomas Cochran , Yehuda Smooha
发明人： Sailesh Chittipeddi , William Thomas Cochran , Yehuda Smooha
IPC分类号： H01L2144
CPC分类号： H01L24/48 , H01L21/76807 , H01L23/53209 , H01L24/05 , H01L24/11 , H01L2221/1036 , H01L2224/0401 , H01L2224/04042 , H01L2224/05073 , H01L2224/05093 , H01L2224/05166 , H01L2224/05181 , H01L2224/05187 , H01L2224/05546 , H01L2224/05624 , H01L2224/05647 , H01L2224/05684 , H01L2224/13099 , H01L2224/48463 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/04941 , H01L2924/04953 , H01L2924/10253 , H01L2924/14 , H01L2224/45099 , H01L2924/00
摘要： A process for forming a dual damascene bond pad within an integrated circuit produces a bond pad which is resistant to stress effects and which therefore allows for the bond pad to be formed over active circuitry. The process includes forming a dual damascene structure by forming a bond pad opening having a barrier layer film on the bottom surface of the upper portion of the opening, and forming vias which extend downwardly through the bottom surface. The process produces a bond pad which is resistant to stress effects such as cracking which can be produced when bonding an external wire to the bond pad. Leakage currents between the bond pad and the underlying circuitry are prevented.
摘要翻译：用于在集成电路内形成双镶嵌键合焊盘的工艺产生接合焊盘，其抵抗应力作用并因此允许在有源电路上形成接合焊盘。该方法包括通过在开口的上部的底部表面上形成具有阻挡层膜的接合焊盘开口形成双镶嵌结构，以及形成向下延伸通过底表面的通孔。该工艺产生接合焊盘，其抵抗诸如当将外部电线接合到接合焊盘时可产生的应力作用的破坏。防止接合焊盘和底层电路之间的泄漏电流。

3. 发明授权

US06556409B1 Integrated circuit including ESD circuits for a multi-chip module and a method therefor 有权
标题翻译：包括用于多芯片模块的ESD电路的集成电路及其方法
公开(公告)号：US06556409B1
公开(公告)日：2003-04-29
申请号：US09652571
申请日：2000-08-31
申请人： Sailesh Chittipeddi , William Thomas Cochran , Yehuda Smooha
发明人： Sailesh Chittipeddi , William Thomas Cochran , Yehuda Smooha
IPC分类号： H02H322
CPC分类号： H01L23/60 , H01L27/0248 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit that includes I/O circuitry that may or may not be protected from ESD damage. The protection from ESD damage may be selectively deactivated or activated or may not be present at all in one or more of the I/O circuits. In use, the integrated circuit may be coupled to another integrated circuit to form a multi-chip module where the ESD protection for the I/O circuitry between the modules is deactivated or not present. This is advantageous because the likelihood of ESD damage to this I/O circuitry is reduced once the multi-chip module is formed. It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.
摘要翻译：一个集成电路，其中包含I / O电路，可以或可能不受ESD保护。可以选择性地禁用或激活对ESD损坏的保护，或者可以在一个或多个I / O电路中完全不存在。在使用中，集成电路可以耦合到另一个集成电路以形成多芯片模块，其中模块之间的I / O电路的ESD保护被去激活或不存在。这是有利的，因为一旦形成多芯片模块就可以减少对该I / O电路的ESD损坏的可能性。应当理解，上述一般描述和以下详细描述都是本发明的示例性的，但不是限制性的。

4. 发明授权

US5751065A Integrated circuit with active devices under bond pads 失效
标题翻译：集成电路与有源器件在接合焊盘下
公开(公告)号：US5751065A
公开(公告)日：1998-05-12
申请号：US549990
申请日：1995-10-30
申请人： Sailesh Chittipeddi , William Thomas Cochran , Yehuda Smooha
发明人： Sailesh Chittipeddi , William Thomas Cochran , Yehuda Smooha
IPC分类号： H01L27/04 , H01L21/3205 , H01L21/60 , H01L21/822 , H01L23/485 , H01L23/52 , H01L23/544 , H01L29/78 , H01L23/48
CPC分类号： H01L24/05 , H01L22/34 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05093 , H01L2224/05556 , H01L2224/05599 , H01L2224/05624 , H01L2224/48463 , H01L2924/00014 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01033 , H01L2924/01082 , H01L2924/1306 , H01L2924/14 , H01L2924/19041 , H01L2924/30105 , H01L2924/3025 , H01L2924/351
摘要： Active circuitry is placed under the bond pads in an integrated circuit having at least three metal levels. The metal level adjacent the bond pad level acts as a buffer and provides stress relief and prevents leakage currents between the bond pad and underlying circuitry.
摘要翻译：有源电路放置在具有至少三个金属电平的集成电路中的接合焊盘下方。接合焊盘级附近的金属级作为缓冲器，并提供应力消除，并防止接合焊盘和下层电路之间的漏电流。

5. 发明授权

US06503793B1 Method for concurrently forming an ESD protection device and a shallow trench isolation region 有权
标题翻译：同时形成ESD保护器件和浅沟槽隔离区域的方法
公开(公告)号：US06503793B1
公开(公告)日：2003-01-07
申请号：US09927752
申请日：2001-08-10
申请人： Sailesh Chittipeddi , Yehuda Smooha
发明人： Sailesh Chittipeddi , Yehuda Smooha
IPC分类号： H01L218242
CPC分类号： H01L29/66181 , H01L21/76229 , H01L21/763 , H01L27/0251 , H01L29/945
摘要： The present invention provides a method of forming a trench capacitor in an input/output region and a trench isolation structure in an active device region and a method of manufacturing an integrated circuit using the aforementioned method of forming. The invention comprises concurrently forming an isolation trench in an active region and a capacitive trench in an input/output region, concurrently forming a dielectric layer over the walls of the isolation trench and the capacitive trench, and forming a conductive material in the capacitive trench.
摘要翻译：本发明提供一种在有源器件区域中的输入/输出区域和沟槽隔离结构中形成沟槽电容器的方法和使用上述形成方法制造集成电路的方法。本发明包括在输入/输出区域中的有源区域和电容沟槽中同时形成隔离沟槽，同时在隔离沟槽和电容沟槽的壁上形成电介质层，并在电容沟槽中形成导电材料。

6. 发明授权

US5965903A Device and method of manufacture for an integrated circuit having a BIST circuit and bond pads incorporated therein 失效
标题翻译：具有BIST电路和其中结合的接合焊盘的集成电路的装置和制造方法
公开(公告)号：US5965903A
公开(公告)日：1999-10-12
申请号：US22733
申请日：1998-02-12
申请人： Sailesh Chittipeddi , William T. Cochran , Yehuda Smooha
发明人： Sailesh Chittipeddi , William T. Cochran , Yehuda Smooha
IPC分类号： H01L23/485 , H01L23/544 , H01L23/48
CPC分类号： H01L24/05 , H01L22/34 , H01L24/03 , H01L24/06 , H01L24/48 , H01L2224/02126 , H01L2224/02166 , H01L2224/04042 , H01L2224/05093 , H01L2224/05556 , H01L2224/05624 , H01L2224/48463 , H01L2224/85424 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01033 , H01L2924/01075 , H01L2924/1306 , H01L2924/14 , H01L2924/19041
摘要： The present invention provides, in one embodiment, an integrated circuit having a substrate and active devices formed on the surface of the substrate. Other embodiments of the integrated circuit provide for having at least either three or four metal layers. In a particular embodiment of the present invention, the integrated circuit comprises a bond pad formed over a portion of the active devices. The bond pad has a footprint. As used therein the word footprint means the area covered by the device to which the word refers. The integrated circuit further incudes a patterned metal layer having a metal layer footprint that is located between the bond pad and the substrate and a built-in self-test (BIST) circuit that has a BIST footprint, which is located between the substrate and the bond pad. In this particular embodiment, the bond pad footprint overlays at least a portion of the metal layer footprint and the BIST footprint. However, in a more advantageous embodiment, the bond pad footprint overlays a substantial portion of the metal layer footprint and the BIST footprint.
摘要翻译：本发明在一个实施例中提供了一种集成电路，该集成电路具有形成在衬底表面上的衬底和有源器件。集成电路的其它实施例提供具有至少三个或四个金属层。在本发明的特定实施例中，集成电路包括形成在有源器件的一部分上的接合焊盘。接合垫有足迹。如其中使用的字足迹是指该词所涉及的设备所覆盖的区域。集成电路还包括具有位于接合焊盘和衬底之间的金属层覆盖区的图案化金属层和具有BIST占空比的内置自检（BIST）电路，该BIST封装位于衬底和衬底之间键盘在该特定实施例中，接合焊盘覆盖层覆盖金属层覆盖区和BIST覆盖区的至少一部分。然而，在更有利的实施例中，接合焊盘覆盖层覆盖金属层覆盖区和BIST覆盖区的大部分。

7. 发明授权

US06384452B1 Electrostatic discharge protection device with monolithically formed resistor-capacitor portion 有权
标题翻译：具有单片形成的电阻电容器部分的静电放电保护器件
公开(公告)号：US06384452B1
公开(公告)日：2002-05-07
申请号：US09617687
申请日：2000-07-17
申请人： Sailesh Chittipeddi , Yehuda Smooha
发明人： Sailesh Chittipeddi , Yehuda Smooha
IPC分类号： H01L2701
CPC分类号： H01L27/0288 , H01L21/76264 , H01L21/76286 , H01L27/0248 , H01L28/20 , H01L29/66181
摘要： A semiconductor device comprising a silicon-on-insulator (SOI) substrate including a base substrate, an insulator layer, and a silicon layer, a trench capacitor including at least one trench formed in the silicon-on-insulator substrate and extending through the silicon layer and the insulator layer to the base substrate, and a resistive element formed in the silicon-on-insulator substrate. The capacitor and resistor structure provide an R-C circuit which may be used in triggering an electrostatic discharge (ESD) protection device.
摘要翻译：一种包括绝缘体上硅（SOI）衬底的半导体器件，包括基底衬底，绝缘体层和硅层，沟槽电容器，其包括形成在绝缘体上硅衬底中的至少一个沟槽并延伸穿过硅层和绝缘体层到基底衬底，以及形成在绝缘体上硅衬底上的电阻元件。电容器和电阻结构提供可用于触发静电放电（ESD）保护装置的R-C电路。

8. 发明授权

US06136620A Method of manufacture for an integrated circuit having a BIST circuit and bond pads incorporated therein 有权
标题翻译：具有BIST电路的集成电路的制造方法和其中结合的接合焊盘
公开(公告)号：US06136620A
公开(公告)日：2000-10-24
申请号：US288746
申请日：1999-04-08
申请人： Sailesh Chittipeddi , William T. Cochran , Yehuda Smooha
发明人： Sailesh Chittipeddi , William T. Cochran , Yehuda Smooha
IPC分类号： H01L23/485 , H01L23/544 , H01L23/48 , G01R31/26
CPC分类号： H01L24/05 , H01L22/34 , H01L24/03 , H01L24/06 , H01L24/48 , H01L2224/02126 , H01L2224/02166 , H01L2224/04042 , H01L2224/05093 , H01L2224/05556 , H01L2224/05624 , H01L2224/48463 , H01L2224/85424 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01033 , H01L2924/01075 , H01L2924/1306 , H01L2924/14 , H01L2924/19041
摘要： In a method of incorporating BIST (built-in self test) circuitry in an integrated circuit, at least one metal layer is arranged to relieve stress in the substrate under bond pads from wire attachment to these pads. By providing at least one stress relieving metal layer, which can be incorporated into electrical paths of the bond pads and related circuitry, BIST circuitry can be provided, at least partly, in the conventionally non-active semiconductive portion of the substrate under the bond pad. The method allows BIST circuitry to occupy conventionally non-active areas under the bond pads wherein leakage current from stress cracks in dielectric layers under the bond pads can be redirected to a metal layer.
摘要翻译：在将BIST（内置自检）电路并入集成电路中的方法中，布置至少一个金属层以减轻接合焊盘处的衬底内的应力，从而将电线连接到这些焊盘。通过提供可以结合到接合焊盘和相关电路的电气路径中的至少一个应力消除金属层，BIST电路可以至少部分地提供在基板的传统非活性半导体部分的接合焊盘。该方法允许BIST电路占据接合焊盘下方的常规非有源区域，其中在接合焊盘下方的电介质层中的应力裂纹的泄漏电流可以被重定向到金属层。

9. 发明申请

US20100232078A1 Electrostatic Discharge Protection Circuit 有权
标题翻译：静电放电保护电路
公开(公告)号：US20100232078A1
公开(公告)日：2010-09-16
申请号：US12438460
申请日：2007-10-30
申请人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
发明人： Dipankar Bhattacharya , Makeshwar Kothandaraman , John C. Kriz , Bernard L. Morris , Yehuda Smooha
IPC分类号： H02H9/04
CPC分类号： H01L27/0266
摘要： An ESD protection circuit includes a first voltage clamp, connected between a first voltage supply node and a second voltage supply node of the circuit, and a second voltage clamp, connected between the second voltage supply node and a voltage return of the circuit. The first voltage supply node is adapted to receive a first voltage which is greater than a prescribed gate oxide reliability potential of the circuit. The second voltage supply node is operative to receive a second voltage which is less than the first voltage. The first voltage clamp is operative to clamp the first voltage on the first voltage supply node to a first value during an ESD event between the first and second voltage supply nodes, and the second voltage clamp is operative to clamp the second voltage on the second voltage supply node to a second value during an ESD event between the second voltage supply node and the voltage return.
摘要翻译： ESD保护电路包括连接在电路的第一电压供应节点和第二电压供应节点之间的第一电压钳位器，以及连接在第二电压供应节点和电路的电压回路之间的第二电压钳位。第一电压供应节点适于接收大于电路的预定栅极氧化物可靠性电位的第一电压。第二电压供应节点可操作以接收小于第一电压的第二电压。第一电压钳位器用于在第一和第二电压供应节点之间的ESD事件期间将第一电压供应节点上的第一电压钳位到第一值，并且第二电压钳位器用于将第二电压钳位在第二电压在第二电压供应节点和电压返回之间的ESD事件期间将供应节点提供给第二值。

10. 发明授权

US07495873B2 Electrostatic discharge protection in a semiconductor device 有权
标题翻译：半导体器件中的静电放电保护
公开(公告)号：US07495873B2
公开(公告)日：2009-02-24
申请号：US10977881
申请日：2004-10-29
申请人： Dipankar Bhattacharya , John C. Kriz , Bernard L. Morris , Yehuda Smooha
发明人： Dipankar Bhattacharya , John C. Kriz , Bernard L. Morris , Yehuda Smooha
IPC分类号： H02H9/00
CPC分类号： H01L27/0266
摘要： An ESD protection circuit for protecting a circuit from an ESD event occurring between a first voltage supply node and a second voltage supply node associated with the circuit to be protected includes an MOS device having a gate terminal, a first source/drain terminal and a second source/drain terminal. The first source/drain terminal is connected to the first voltage supply node and the second source/drain terminal is connected to the second voltage supply node. The ESD protection circuit further includes a trigger circuit coupled to the gate terminal of the MOS device. The trigger circuit is configured to generate a control signal at the gate terminal of the MOS device for activating the MOS device during the ESD event. At least a portion of the trigger circuit is formed in a floating well which becomes biased to a voltage that is substantially equal to a first voltage when the first voltage is supplied to the first voltage supply node or to a second voltage when the second voltage is applied to the second voltage supply node, whichever voltage is greater.
摘要翻译：一种ESD保护电路，用于保护电路免受在要被保护的电路的第一电压供应节点和第二电压供应节点之间发生的ESD事件的影响，包括具有栅极端子，第一源极/漏极端子和第二电压源的MOS器件源极/漏极端子。第一源极/漏极端子连接到第一电压供应节点，第二源极/漏极端子连接到第二电压供应节点。 ESD保护电路还包括耦合到MOS器件的栅极端子的触发电路。触发电路被配置为在MOS器件的栅极端产生控制信号，以在ESD事件期间激活MOS器件。触发电路的至少一部分形成在浮置阱中，当浮置第二电压为第二电压时，浮置阱被偏置到基本上等于第一电压的电压，或者当第一电压被提供给第一电压供应节点时，施加到第二电压供应节点，无论哪个电压较大。

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