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1. 发明授权

US06017787A Integrated circuit with twin tub 失效
标题翻译：集成电路与双缸
公开(公告)号：US06017787A
公开(公告)日：2000-01-25
申请号：US775490
申请日：1996-12-31
申请人： Sailesh Chittipeddi , William Thomas Cochran , Stephen Knight
发明人： Sailesh Chittipeddi , William Thomas Cochran , Stephen Knight
IPC分类号： H01L21/265 , H01L21/266 , H01L21/8238 , H01L27/092
CPC分类号： H01L21/266 , H01L21/823892
摘要： A twin tub integrated circuit and method for its formation are disclosed. A portion of the substrate is covered by photoresist while an n region is formed, illustratively, by ion implantation. Then the n region is covered with a protective material, illustratively a spin on glass or another photoresist. The previously-formed photoresist is removed and a p-type implant is performed to create an p region. When all the protective layers are removed, both regions have upper surfaces which are co-planar. The co-planar surfaces, a departure from previous practice, make submicron lithography easier. The regions are annealed to form twin tubs.
摘要翻译：公开了一种用于其形成的双桶集成电路及其方法。例如，通过离子注入形成n区，衬底的一部分被光致抗蚀剂覆盖。然后，n区域被保护材料覆盖，例如是在玻璃上或其他光致抗蚀剂上的旋涂。去除预先形成的光致抗蚀剂并执行p型注入以产生p区。当所有保护层被去除时，两个区域都具有共面的上表面。与以前的做法不同的共面表面使亚微米光刻更容易。这些区域进行退火以形成双盆。

2. 发明授权

US5773867A Programmable hex-ROM with isolation transistor structure 失效
标题翻译：具有隔离晶体管结构的可编程六进制ROM
公开(公告)号：US5773867A
公开(公告)日：1998-06-30
申请号：US827352
申请日：1997-03-26
申请人： Sailesh Chittipeddi , William Thomas Cochran , Kang Woo Lee
发明人： Sailesh Chittipeddi , William Thomas Cochran , Kang Woo Lee
IPC分类号： H01L27/10 , H01L21/765 , H01L27/112 , H01L29/78 , G11C17/00
CPC分类号： H01L27/112 , H01L21/765
摘要： A ROM (read only memory) is disclosed. For via-ROMs, an isolation transistor is used to isolate adjacent pairs of memory devices instead of the more conventional field oxide isolation. The gate of the isolation transistor is grounded, insuring that conduction does not take place. For a GASAD ROM, a field oxide isolation is used.
摘要翻译：公开了一种ROM（只读存储器）。对于通孔ROM，隔离晶体管用于隔离相邻的存储器件对，而不是更常规的场氧化物隔离。隔离晶体管的栅极接地，确保不会发生导通。对于GASAD ROM，使用场氧化物隔离。

3. 发明授权

US5751065A Integrated circuit with active devices under bond pads 失效
标题翻译：集成电路与有源器件在接合焊盘下
公开(公告)号：US5751065A
公开(公告)日：1998-05-12
申请号：US549990
申请日：1995-10-30
申请人： Sailesh Chittipeddi , William Thomas Cochran , Yehuda Smooha
发明人： Sailesh Chittipeddi , William Thomas Cochran , Yehuda Smooha
IPC分类号： H01L27/04 , H01L21/3205 , H01L21/60 , H01L21/822 , H01L23/485 , H01L23/52 , H01L23/544 , H01L29/78 , H01L23/48
CPC分类号： H01L24/05 , H01L22/34 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05093 , H01L2224/05556 , H01L2224/05599 , H01L2224/05624 , H01L2224/48463 , H01L2924/00014 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01033 , H01L2924/01082 , H01L2924/1306 , H01L2924/14 , H01L2924/19041 , H01L2924/30105 , H01L2924/3025 , H01L2924/351
摘要： Active circuitry is placed under the bond pads in an integrated circuit having at least three metal levels. The metal level adjacent the bond pad level acts as a buffer and provides stress relief and prevents leakage currents between the bond pad and underlying circuitry.
摘要翻译：有源电路放置在具有至少三个金属电平的集成电路中的接合焊盘下方。接合焊盘级附近的金属级作为缓冲器，并提供应力消除，并防止接合焊盘和下层电路之间的漏电流。

4. 发明授权

US06838769B1 Dual damascene bond pad structure for lowering stress and allowing circuitry under pads 有权
标题翻译：双镶嵌结合垫结构，用于降低压力并允许垫下的电路
公开(公告)号：US06838769B1
公开(公告)日：2005-01-04
申请号：US09465089
申请日：1999-12-16
申请人： Sailesh Chittipeddi , William Thomas Cochran , Yehuda Smooha
发明人： Sailesh Chittipeddi , William Thomas Cochran , Yehuda Smooha
IPC分类号： H01L21/60 , H01L21/768 , H01L23/485 , H01L23/532 , H01L29/40 , H01L23/52
CPC分类号： H01L24/48 , H01L21/76807 , H01L23/53209 , H01L24/05 , H01L24/11 , H01L2224/0401 , H01L2224/04042 , H01L2224/05093 , H01L2224/05096 , H01L2224/05166 , H01L2224/05187 , H01L2224/05546 , H01L2224/05554 , H01L2224/05556 , H01L2224/05624 , H01L2224/05647 , H01L2224/05684 , H01L2224/13099 , H01L2224/48463 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01082 , H01L2924/04941 , H01L2924/04953 , H01L2924/10253 , H01L2924/14 , H01L2224/45099 , H01L2924/00
摘要： A bond pad is located over active circuitry formed within an integrated circuit device. A barrier film forms the bottom surface of the upper portion of a bond pad opening which also includes vias extending through the bottom surface to form a dual damascene structure. The bond pad is resistant to stress effects such as cracking, which can be produced when bonding an external wire to the bond pad, and therefore prevents leakage currents between the bond pads and the underlying circuitry.
摘要翻译：接合焊盘位于集成电路器件内形成的有源电路上。阻挡膜形成接合焊盘开口的上部的底表面，其还包括延伸穿过底表面的通孔以形成双镶嵌结构。接合焊盘抵抗诸如开裂的应力作用，当将外部导线接合到接合焊盘时可以产生裂纹，因此防止接合焊盘和下面的电路之间的漏电流。

5. 发明授权

US06417087B1 Process for forming a dual damascene bond pad structure over active circuitry 有权
标题翻译：用于在有源电路上形成双镶嵌键合焊盘结构的工艺
公开(公告)号：US06417087B1
公开(公告)日：2002-07-09
申请号：US09465075
申请日：1999-12-16
申请人： Sailesh Chittipeddi , William Thomas Cochran , Yehuda Smooha
发明人： Sailesh Chittipeddi , William Thomas Cochran , Yehuda Smooha
IPC分类号： H01L2144
CPC分类号： H01L24/48 , H01L21/76807 , H01L23/53209 , H01L24/05 , H01L24/11 , H01L2221/1036 , H01L2224/0401 , H01L2224/04042 , H01L2224/05073 , H01L2224/05093 , H01L2224/05166 , H01L2224/05181 , H01L2224/05187 , H01L2224/05546 , H01L2224/05624 , H01L2224/05647 , H01L2224/05684 , H01L2224/13099 , H01L2224/48463 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/04941 , H01L2924/04953 , H01L2924/10253 , H01L2924/14 , H01L2224/45099 , H01L2924/00
摘要： A process for forming a dual damascene bond pad within an integrated circuit produces a bond pad which is resistant to stress effects and which therefore allows for the bond pad to be formed over active circuitry. The process includes forming a dual damascene structure by forming a bond pad opening having a barrier layer film on the bottom surface of the upper portion of the opening, and forming vias which extend downwardly through the bottom surface. The process produces a bond pad which is resistant to stress effects such as cracking which can be produced when bonding an external wire to the bond pad. Leakage currents between the bond pad and the underlying circuitry are prevented.
摘要翻译：用于在集成电路内形成双镶嵌键合焊盘的工艺产生接合焊盘，其抵抗应力作用并因此允许在有源电路上形成接合焊盘。该方法包括通过在开口的上部的底部表面上形成具有阻挡层膜的接合焊盘开口形成双镶嵌结构，以及形成向下延伸通过底表面的通孔。该工艺产生接合焊盘，其抵抗诸如当将外部电线接合到接合焊盘时可产生的应力作用的破坏。防止接合焊盘和底层电路之间的泄漏电流。

6. 发明授权

US06556409B1 Integrated circuit including ESD circuits for a multi-chip module and a method therefor 有权
标题翻译：包括用于多芯片模块的ESD电路的集成电路及其方法
公开(公告)号：US06556409B1
公开(公告)日：2003-04-29
申请号：US09652571
申请日：2000-08-31
申请人： Sailesh Chittipeddi , William Thomas Cochran , Yehuda Smooha
发明人： Sailesh Chittipeddi , William Thomas Cochran , Yehuda Smooha
IPC分类号： H02H322
CPC分类号： H01L23/60 , H01L27/0248 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit that includes I/O circuitry that may or may not be protected from ESD damage. The protection from ESD damage may be selectively deactivated or activated or may not be present at all in one or more of the I/O circuits. In use, the integrated circuit may be coupled to another integrated circuit to form a multi-chip module where the ESD protection for the I/O circuitry between the modules is deactivated or not present. This is advantageous because the likelihood of ESD damage to this I/O circuitry is reduced once the multi-chip module is formed. It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.
摘要翻译：一个集成电路，其中包含I / O电路，可以或可能不受ESD保护。可以选择性地禁用或激活对ESD损坏的保护，或者可以在一个或多个I / O电路中完全不存在。在使用中，集成电路可以耦合到另一个集成电路以形成多芯片模块，其中模块之间的I / O电路的ESD保护被去激活或不存在。这是有利的，因为一旦形成多芯片模块就可以减少对该I / O电路的ESD损坏的可能性。应当理解，上述一般描述和以下详细描述都是本发明的示例性的，但不是限制性的。

7. 发明授权

US06395611B1 Inductor or low loss interconnect and a method of manufacturing an inductor or low loss interconnect in an integrated circuit 有权
标题翻译：电感器或低损耗互连以及在集成电路中制造电感器或低损耗互连的方法
公开(公告)号：US06395611B1
公开(公告)日：2002-05-28
申请号：US09432725
申请日：1999-11-01
申请人： Nathan Belk , William Thomas Cochran , Michel Ranjit Frei , David Clayton Goldthorp , Shahriar Moinian , Kwok K. Ng , Mark Richard Pinto , Ya-Hong Xie
发明人： Nathan Belk , William Thomas Cochran , Michel Ranjit Frei , David Clayton Goldthorp , Shahriar Moinian , Kwok K. Ng , Mark Richard Pinto , Ya-Hong Xie
IPC分类号： H01L2120
CPC分类号： H01L28/10 , H01L23/5227 , H01L23/645 , H01L27/08 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit with a buried layer for increasing the Q of an inductor formed in the integrated circuit. The substrate includes a highly doped buried preserving device and latchup characteristics. The inductor may also include an increased thickness conductive layer in the inductor to further increase Q. The present invention is also directed to a low loss interconnect.
摘要翻译：一种具有埋层的集成电路，用于增加形成在集成电路中的电感器的Q。衬底包括高掺杂掩埋保存装置和闭锁特性。电感器还可以包括电感器中增加的厚度导电层以进一步增加Q.本发明还涉及一种低损耗互连。

8. 发明授权

US5963054A High voltage CMOS logic circuit using low voltage transistors 失效
标题翻译：高压CMOS逻辑电路采用低压晶体管
公开(公告)号：US5963054A
公开(公告)日：1999-10-05
申请号：US985709
申请日：1997-12-05
申请人： William Thomas Cochran , Scott Wayne McLellan
发明人： William Thomas Cochran , Scott Wayne McLellan
IPC分类号： H03K3/356 , H03K19/003 , H03K19/0175 , H03K19/094
CPC分类号： H03K19/00315 , H03K3/356113
摘要： A logic gate arrangement for switching voltages greater than the gate breakdown voltage of the transistors in the gate. Two transistors of different conductivity types, are disposed between the N and P transistors which perform the logic function of a conventional CMOS gate. The gates of the two transistors are connected to a first voltage that is less than the breakdown voltage of the transistors, with the entire logic gate being supplied with a voltage that is greater than the first voltage. Three outputs are provided, two with limited voltage swings that drive other like gates or conventional CMOS gates and the other output having a full voltage swing. Logic gates implementing various logic functions, such as NAND and NOR, are disclosed. Further, a cross-coupled logic gate is disclosed which can operate as a latch or as a logic voltage translator circuit.
摘要翻译：用于切换大于栅极中的晶体管的栅极击穿电压的电压的逻辑门装置。具有不同导电类型的两个晶体管设置在执行常规CMOS栅极的逻辑功能的N和P晶体管之间。两个晶体管的栅极连接到小于晶体管的击穿电压的第一电压，整个逻辑门被提供大于第一电压的电压。提供三个输出，其中两个具有有限的电压摆动，其驱动其它类似的栅极或常规CMOS栅极，另一个输出具有全电压摆幅。公开了实现各种逻辑功能的逻辑门，例如NAND和NOR。此外，公开了可以用作锁存器或逻辑电压转换器电路的交叉耦合逻辑门。

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