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    • 6. 发明授权
    • Radio frequency duplex filter for removing transmit signals from a receive path
    • 用于从接收路径去除发送信号的射频双工滤波器
    • US08005448B1
    • 2011-08-23
    • US11747032
    • 2007-05-10
    • Kelvin Kai Tuan YanDong-Jun Yang
    • Kelvin Kai Tuan YanDong-Jun Yang
    • H04B17/00
    • H03H7/465H03H7/0153
    • The present invention is an RF duplex filter that is used to remove transmit signals from the receive path of a full duplex transceiver. The RF duplex filter includes a notch filter for blocking signals at a transmit frequency and a bandpass filter for enhancing signals at a receive frequency. The notch filter is formed with series resonant elements and the bandpass filter is formed with parallel resonant elements. One embodiment of the present invention may include tunable resonant elements for tuning the notch filter to a transmit frequency, tuning the bandpass filter to a receive frequency, or both. Calibration circuitry may be included in the full duplex receiver for adjusting the tunable resonant elements. The present invention includes a method for calibrating the tunable resonant elements.
    • 本发明是用于从全双工收发器的接收路径去除发送信号的RF双工滤波器。 RF双工滤波器包括用于阻挡发射频率信号的陷波滤波器和用于增强接收频率处的信号的带通滤波器。 陷波滤波器由串联谐振元件形成,带通滤波器形成有并联谐振元件。 本发明的一个实施例可以包括用于将陷波滤波器调谐到发射频率的可调谐谐振元件,将带通滤波器调谐到接收频率,或者两者。 校准电路可以包括在全双工接收器中用于调节可调谐谐振元件。 本发明包括校准可调谐谐振元件的方法。
    • 7. 发明授权
    • High speed phase locked loop
    • 高速锁相环
    • US06940322B2
    • 2005-09-06
    • US10459910
    • 2003-06-12
    • Dong-Jun YangKenneth O
    • Dong-Jun YangKenneth O
    • H03K3/354H03K23/66H03L7/193H03L7/06
    • H03L7/193H03K3/354H03K23/667
    • A high speed CMOS phase locked loop (PLL) (10) includes a three-state phase detection circuit having a frequency phase detector (12) coupled to a charge pump (14) for monitoring the phase differences between a reference frequency signal and a divided output frequency signal. The PLL can further include a loop filter (16)coupled to the three-state phase detection circuit, a VCO (18) coupled to the output of the loop filter, a VCO buffer (22) coupled to the output of the VCO for providing an output frequency signal, and a dual modulus prescaler (28) having a synchronous counter (27 and 29) using feedback among D flip-flops (30 and 32) for generating the divided output frequency signal.
    • 高速CMOS锁相环(PLL)(10)包括具有耦合到电荷泵(14)的频率相位检测器(12)的三态相位检测电路,用于监视参考频率信号和分频信号之间的相位差 输出频率信号。 PLL还可以包括耦合到三态相位检测电路的环路滤波器(16),耦合到环路滤波器的输出的VCO(18),耦合到VCO的输出的VCO缓冲器(22),用于提供 输出频率信号和双模预分频器(28),其具有使用D触发器(30和32)之间的反馈产生分频输出频率信号的同步计数器(27和29)。