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1. 发明申请

US20070250284A1 Semiconductor integrated circuit and testing method for the same 审中-公开
公开(公告)号：US20070250284A1
公开(公告)日：2007-10-25
申请号：US11711644
申请日：2007-02-28
申请人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura , Takashi Ishimura
发明人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura , Takashi Ishimura
IPC分类号： G01R31/3187
CPC分类号： G11C29/12015 , G01R31/318552 , G01R31/31858 , G11C29/50012 , H03L7/00 , H03L7/06
摘要： A semiconductor integrated circuit of the present invention is provided with a clock control portion having a clock generation portion for generating a clock signal and an output command signal input portion for receiving a clock output command signal from the outside, and an internal circuit controlled by an output clock signal that is output from the clock control portion, and the clock control portion is configured so that it outputs the output clock signal to the internal circuit when a certain time period has passed from a time when the output command signal is received.

2. 发明授权

US07197725B2 Semiconductor integrated circuit and testing method for the same 有权
标题翻译：半导体集成电路和测试方法相同
公开(公告)号：US07197725B2
公开(公告)日：2007-03-27
申请号：US10187413
申请日：2002-07-02
申请人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura , Takashi Ishimura
发明人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura , Takashi Ishimura
IPC分类号： G06F17/50
CPC分类号： G11C29/12015 , G01R31/318552 , G01R31/31858 , G11C29/50012 , H03L7/00 , H03L7/06
摘要： A semiconductor integrated circuit of the present invention is provided with a clock control portion having a clock generation portion for generating a clock signal and an output command signal input portion for receiving a clock output command signal from the outside, and an internal circuit controlled by an output clock signal that is output from the clock control portion, and the clock control portion is configured so that it outputs the output clock signal to the internal circuit when a certain time period has passed from a time when the output command signal is received.
摘要翻译：本发明的半导体集成电路设置有时钟控制部分，其具有用于产生时钟信号的时钟产生部分和用于从外部接收时钟输出命令信号的输出命令信号输入部分和由外部控制的内部电路输出时钟信号，并且时钟控制部分被配置为使得当从接收到输出命令信号的时间过去一段时间时，它将输出时钟信号输出到内部电路。

3. 发明授权

US07348595B2 Semiconductor wiring substrate, semiconductor device, method for testing semiconductor device, and method for mounting semiconductor device 失效
标题翻译：半导体配线基板，半导体装置，半导体装置的测试方法以及半导体装置的安装方法
公开(公告)号：US07348595B2
公开(公告)日：2008-03-25
申请号：US10828492
申请日：2004-04-21
申请人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura
发明人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura
IPC分类号： G11C5/02
CPC分类号： G01R31/28 , G01R31/318505 , G01R31/318538 , G01R31/318558 , G06F17/50 , G11C5/02 , G11C5/025 , G11C29/48 , G11C2029/3202 , H01L23/12
摘要： A semiconductor device constructed by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, a method for testing the device and a method for mounting the chip IPs. A silicon wiring substrate on which chip IPs can be mounted is provided. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip flops. The flip flops are connected to wiring and are arranged to test connections in the wiring. The entire IP On Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.
摘要翻译：通过将多个芯片智能特性（IP）安装在公共半导体布线基板上构成的半导体器件，测试器件的方法和安装芯片IP的方法。提供了可以安装芯片IP的硅布线基板。通过连接触发器在硅布线基板上形成用于边界扫描测试的电路。触发器连接到布线并被布置成测试布线中的连接。整个IP On Super Sub（IPOS）设备或每个芯片IP可以被布置成便于在芯片IP的内部电路上进行扫描测试，内置自检（BIST）等。

4. 发明授权

US07032196B2 Semiconductor wiring substrate, semiconductor device, method for testing semiconductor device, and method for mounting semiconductor device 失效
公开(公告)号：US07032196B2
公开(公告)日：2006-04-18
申请号：US10828230
申请日：2004-04-21
申请人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura
发明人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura
IPC分类号： G06F17/50 , H01L23/58 , G01R31/28
CPC分类号： G01R31/28 , G01R31/318505 , G01R31/318538 , G01R31/318558 , G06F17/50 , G11C5/02 , G11C5/025 , G11C29/48 , G11C2029/3202 , H01L23/12
摘要： A semiconductor device constructed by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, a method for testing the device and a method for mounting the chip IPs. A silicon wiring substrate on which chip IPs can be mounted is provided. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip flops. The flip flops are connected to wiring and are arranged to test connections in the wiring. The entire IP On Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.

5. 发明授权

US06734549B2 Semiconductor device having a device for testing the semiconductor 失效
标题翻译：具有用于测试半导体的器件的半导体器件
公开(公告)号：US06734549B2
公开(公告)日：2004-05-11
申请号：US10187269
申请日：2002-07-02
申请人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura
发明人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura
IPC分类号： H01L2312
CPC分类号： G01R31/28 , G01R31/318505 , G01R31/318538 , G01R31/318558 , G06F17/50 , G11C5/02 , G11C5/025 , G11C29/48 , G11C2029/3202 , H01L23/12
摘要： A semiconductor device constructed by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, a method for testing the device and a method for mounting the chip IPs. A silicon wiring substrate on which chip IPs can be mounted is provided. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip flops. The flip flops are connected to wiring and are arranged to test connections in the wiring. The entire IP On Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.
摘要翻译：通过将多个芯片智能特性（IP）安装在公共半导体布线基板上构成的半导体器件，测试器件的方法和安装芯片IP的方法。提供了可以安装芯片IP的硅布线基板。通过连接触发器在硅布线基板上形成用于边界扫描测试的电路。触发器连接到布线并被布置成测试布线中的连接。整个IP On Super Sub（IPOS）设备或每个芯片IP可以被布置成便于在芯片IP的内部电路上进行扫描测试，内置自检（BIST）等。

6. 发明授权

US07171600B2 Semiconductor wiring substrate, semiconductor device, method for testing semiconductor device, and method for mounting semiconductor device 有权
标题翻译：半导体配线基板，半导体装置，半导体装置的测试方法以及半导体装置的安装方法
公开(公告)号：US07171600B2
公开(公告)日：2007-01-30
申请号：US10828263
申请日：2004-04-21
申请人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura
发明人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura
IPC分类号： G01R31/28
CPC分类号： G01R31/28 , G01R31/318505 , G01R31/318538 , G01R31/318558 , G06F17/50 , G11C5/02 , G11C5/025 , G11C29/48 , G11C2029/3202 , H01L23/12
摘要： An apparatus for testing a semiconductor device by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, including a silicon wiring substrate on which the chip IPs are mounted. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip-flops to wiring, which are arranged to test connections in the wiring. An IP on Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.
摘要翻译：一种用于通过在公共半导体布线基板上安装多个芯片智能特性（IP）来测试半导体器件的装置，包括安装有芯片IP的硅布线基板。通过将触发器连接到布线来测试布线中的连接，在硅布线基板上形成用于边界扫描测试的电路。可以安排IP超级（IPOS）设备上的IP或每个芯片IP，以便在芯片IP的内部电路上进行扫描测试，内置自检（BIST）等。

7. 发明授权

US06271677B1 Semiconductor integrated circuit and method for testing the semiconductor integrated circuit 失效
标题翻译：半导体集成电路和半导体集成电路测试方法
公开(公告)号：US06271677B1
公开(公告)日：2001-08-07
申请号：US09560126
申请日：2000-04-28
申请人： Mitsuyasu Ohta , Toshinori Hosokawa , Sadami Takeoka , Osamu Ichikawa
发明人： Mitsuyasu Ohta , Toshinori Hosokawa , Sadami Takeoka , Osamu Ichikawa
IPC分类号： H03K1900
CPC分类号： G01R31/318328
摘要： A semiconductor IC includes a test circuit comprising a logic circuit, a test timing generator, a first register serving as a test signal generation point, and second and third registers serving as test signal observation points. In this test circuit, a target signal transmission path to be tested is selected from a plurality of signal transmission paths in the logic circuit, and the test timing generator outputs a test clock having a cycle according to a delay time of the selected signal transmission path on design to the first to third registers, whereby the first register generates a test signal and the second and third registers observe the test signal. Therefore, the signal transmission paths connecting the test signal generation point and the test signal observation point are tested with high efficiency, whereby more signal transmission paths are tested for delay faults with less number of times the test is executed.
摘要翻译：半导体IC包括测试电路，其包括逻辑电路，测试定时发生器，用作测试信号生成点的第一寄存器，以及用作测试信号观测点的第二和第三寄存器。在该测试电路中，从逻辑电路中的多个信号传输路径选择要测试的目标信号传输路径，并且测试定时发生器输出具有根据所选信号传输路径的延迟时间的周期的测试时钟设计到第一至第三寄存器，由此第一寄存器产生测试信号，第二和第三寄存器观察测试信号。因此，连接测试信号生成点和测试信号观察点的信号传输路径被高效率地测试，由此对于执行测试次数较少的延迟故障来测试更多的信号传输路径。

8. 发明授权

US06615389B1 Database for designing integrated circuit device, and method for designing integrated circuit device 有权
标题翻译：集成电路器件设计数据库，集成电路器件设计方法
公开(公告)号：US06615389B1
公开(公告)日：2003-09-02
申请号：US09561342
申请日：2000-04-28
申请人： Mitsuyasu Ohta , Sadami Takeoka , Osamu Ichikawa
发明人： Mitsuyasu Ohta , Sadami Takeoka , Osamu Ichikawa
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： In response to a design request, fault detection strategy optimizing means selects RT-VCs and a fault detection method from a VCDB. The design request includes: requirements for a system LSI (e.g., area, number of pins, test time and information about the weights of prioritized constraints); and VC information. The fault detection strategy optimizing means performs computations for optimization in view of various parameters, thereby specifying a best fault detection strategy and a method of constructing a single-chip fault detection controller. On the VCDB, multiple VCs associated with the same function and mutually different test techniques are stored. By weighting the parameters affecting a test cost in accordance with a user defined priority order, a test technique of the type minimizing the total test cost can be selected from the VCDB.
摘要翻译：响应于设计请求，故障检测策略优化装置从VCDB中选择RT-VC和故障检测方法。设计请求包括：对系统LSI的要求（例如，区域，引脚数，测试时间和关于优先约束的权重的信息）; 和VC信息。故障检测策略优化装置根据各种参数进行优化计算，从而指定最佳故障检测策略和构建单片故障检测控制器的方法。在VCDB上，存储与相同功能和相互不同的测试技术相关联的多个VC。通过根据用户定义的优先顺序加权影响测试成本的参数，可以从VCDB中选择最小化总测试成本的类型的测试技术。

9. 发明授权

US07203913B2 Semiconductor integrated circuit device, method of testing the same, database for design of the same and method of designing the same 有权
公开(公告)号：US07203913B2
公开(公告)日：2007-04-10
申请号：US10281230
申请日：2002-10-28
申请人： Mitsuyasu Ohta , Sadami Takeoka
发明人： Mitsuyasu Ohta , Sadami Takeoka
IPC分类号： G06F17/50
CPC分类号： G01R31/318575 , G01R31/318502 , G01R31/318558 , G01R31/318591 , G01R31/318594 , G06F17/5036 , G06F17/5045 , G06F2217/78
摘要： Elements of a combinational circuit are divided into plural groups. The output from a terminal Q is fixed at shifted timing in flip-flop circuits belonging to each of groups X, Y and Z resulting from this grouping. With the outputs from the terminals Q of the flip-flop circuits thus fixed, an operation of a shift mode is carried out. When the operation of the shift mode is completed, a hold releasing operation and a capture operation are carried out with respect to each of the groups of the flip-flop circuits. For example, the hold releasing operation is carried out when one clock is at a high level with the capture operation carried out when the clock is at a low level, or the hold releasing operation is successively carried out with respect to each of the groups and then the capture operation for capturing a data signal is carried out with respect to each of the groups.

10. 发明授权

US06625784B1 Semiconductor integrated circuit device, method of testing the same, database for design of the same and method of designing the same 有权
标题翻译：半导体集成电路器件，测试方法，设计数据库及设计方法相同
公开(公告)号：US06625784B1
公开(公告)日：2003-09-23
申请号：US09637867
申请日：2000-08-15
申请人： Mitsuyasu Ohta , Sadami Takeoka
发明人： Mitsuyasu Ohta , Sadami Takeoka
IPC分类号： G06F1750
CPC分类号： G01R31/318575 , G01R31/318502 , G01R31/318558 , G01R31/318591 , G01R31/318594 , G06F17/5036 , G06F17/5045 , G06F2217/78
摘要： Elements of a combinational circuit are divided into plural groups. The output from a terminal Q is fixed at shifted timing in flip-flop circuits belonging to each of groups X, Y and Z resulting from this grouping. With the outputs from the terminals Q of the flip-flop circuits thus fixed, an operation of a shift mode is carried out. When the operation of the shift mode is completed, a hold releasing operation and a capture operation are carried out with respect to each of the groups of the flip-flop circuits. For example, the hold releasing operation is carried out when one clock is at a high level with the capture operation carried out when the clock is at a low level, or the hold releasing operation is successively carried out with respect to each of the groups and then the capture operation for capturing a data signal is carried out with respect to each of the groups.
摘要翻译：组合电路的元件分为多组。端子Q的输出在属于由该分组产生的组X，Y和Z中的每一个的触发器电路中以移位的定时被固定。利用如此固定的触发器电路的端子Q的输出，执行移位模式的操作。当移位模式的操作完成时，针对触发器电路的每个组执行保持释放操作和捕捉操作。例如，当一个时钟处于高电平时执行保持释放操作，当时钟处于低电平时执行捕捉操作，或者相对于每个组依次执行保持释放操作，以及则针对每个组执行用于捕获数据信号的捕获操作。

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