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1. 发明授权

US06907596B2 Mask data generating apparatus, a computer implemented method for generating mask data and a computer program for controlling the mask data generating apparatus 失效
标题翻译：掩模数据产生装置，用于产生掩模数据的计算机实现方法和用于控制掩模数据产生装置的计算机程序
公开(公告)号：US06907596B2
公开(公告)日：2005-06-14
申请号：US10385624
申请日：2003-03-12
申请人： Sachiko Kobayashi , Toshiya Kotani , Satoshi Tanaka , Susumu Watanabe
发明人： Sachiko Kobayashi , Toshiya Kotani , Satoshi Tanaka , Susumu Watanabe
IPC分类号： G03F1/36 , G03F1/68 , G03F1/70 , H01L21/027 , H01L21/82 , G06F17/50
CPC分类号： G03F1/36
摘要： A mask data generating apparatus comprising: a division module configured to extract a line segment and dividing the extracted line segment into a suitable length; a correction value calculation module configured to calculate correction value calculating points from each divided edge; a first calculated center point calculation module configured to set first calculated center points and a shape of a pattern; a first rectangular region preparation module configured to prepare first simulation regions and a plurality of first rectangular regions which overlap with each other; a second calculated center point calculation module configured to acquire second rectangular regions, and calculating second calculated center points based on the second rectangular regions; a second simulation region preparation module configured to acquire second simulation regions; a process simulation execution module configured to calculate a correction value; and a correction pattern preparation module configured to prepare the correction pattern.
摘要翻译：一种掩模数据生成装置，包括：分割模块，被配置为提取线段并将所提取的线段划分成合适的长度; 校正值计算模块，被配置为从每个分割边缘计算校正值计算点; 第一计算中心点计算模块，被配置为设置第一计算的中心点和图案的形状; 第一矩形区域准备模块，被配置为准备第一模拟区域和彼此重叠的多个第一矩形区域; 第二计算中心点计算模块，被配置为获取第二矩形区域，并且基于所述第二矩形区域计算第二计算的中心点; 配置成获取第二模拟区域的第二模拟区域准备模块; 被配置为计算校正值的过程模拟执行模块; 以及配置为准备校正图案的校正图案准备模块。

2. 发明授权

US07065739B2 Pattern correction method of semiconductor device 失效
标题翻译：半导体器件的图案校正方法
公开(公告)号：US07065739B2
公开(公告)日：2006-06-20
申请号：US10331005
申请日：2002-12-27
申请人： Sachiko Kobayashi , Toshiya Kotani , Satoshi Tanaka , Susumu Watanabe , Mitsuhiro Yano
发明人： Sachiko Kobayashi , Toshiya Kotani , Satoshi Tanaka , Susumu Watanabe , Mitsuhiro Yano
IPC分类号： G06F17/50 , G03F1/00
CPC分类号： G03F1/36 , G03F7/70441
摘要： A pattern correction method executed by a computer includes a first correction and a second correction. The first correction is executed by calculating a correction value, in consideration for an optical proximity effect, for edges (first edges) meeting a condition among the edges constituting a designed pattern. Subsequently, The second correction is executed for an edge (second edge) which does not meet the condition, by use of the correction value of any one of the edges (first edges) adjacent to the second edge among the first edges for which the first correction is executed, thus connecting the corrected first edge and the corrected second edge by a line segment. The pattern is corrected to a shape suitable for a mask drawing and a check with simple processing.
摘要翻译：由计算机执行的图案校正方法包括第一校正和第二校正。对于构成设计图案的边缘中满足条件的边缘（第一边缘），考虑光学邻近效应来计算校正值来执行第一校正。随后，对于不符合条件的边缘（第二边缘），通过使用与第一边缘相邻的边缘（第一边缘）中的任何一个边缘（第一边缘）的第一边缘的第一边缘执行校正，从而将校正的第一边缘和校正的第二边缘连接到线段。该图案被校正为适于掩模绘图和具有简单处理的检查的形状。

3. 发明申请

US20120198396A1 METHOD OF OPTIMIZING SEMICONDUCTOR DEVICE MANUFACTURING PROCESS, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND NON-TRANSITORY COMPUTER READABLE MEDIUM 审中-公开
标题翻译：优化半导体器件制造工艺的方法，制造半导体器件的方法和非电子计算机可读介质
公开(公告)号：US20120198396A1
公开(公告)日：2012-08-02
申请号：US13237854
申请日：2011-09-20
申请人： Masanari KAJIWARA , Sachiko Kobayashi , Satoshi Tanaka , Kazuhiro Takahata , Shigeki Nojima , Toshiya Kotani , Shimon Maeda
发明人： Masanari KAJIWARA , Sachiko Kobayashi , Satoshi Tanaka , Kazuhiro Takahata , Shigeki Nojima , Toshiya Kotani , Shimon Maeda
IPC分类号： G06F17/50
CPC分类号： H01L22/20 , H01L22/12 , H01L2924/0002 , H01L2924/00
摘要： A method of optimizing a semiconductor device manufacturing process according to an embodiment is a method of optimizing a semiconductor device manufacturing process in which a pattern based on circuit design is formed. The method of optimizing a semiconductor device manufacturing process according to the embodiment includes: at the time of calculation of a statistic amount based on a distribution of differences at a plurality of sites between a pattern formed by a first exposing apparatus in a first condition and a pattern formed by a second exposing apparatus in a second condition, calculating the statistic amount after applying weighting to the differences based on information on an electrical characteristic; and repeating the calculating with the second condition being changed, and selecting an condition in which the total sum becomes a minimum or equal to or less than a standard value as an optimized condition of the second exposing apparatus.
摘要翻译：根据实施例的优化半导体器件制造工艺的方法是优化其中形成基于电路设计的图案的半导体器件制造工艺的方法。根据实施例的半导体器件制造方法的优化方法包括：在基于在第一状态下由第一曝光装置形成的图案与第一状态之间的多个位置处的差异的分布的统计量的计算时，在第二状态下由第二曝光装置形成的图案，基于关于电特性的信息对所述差进行加权计算后的统计量; 并重复进行第二条件的计算，并且选择总和变为最小或等于或小于标准值的条件作为第二曝光装置的优化条件。

4. 发明授权

US06964031B2 Mask pattern generating method and manufacturing method of semiconductor apparatus 失效
标题翻译：半导体装置的掩模图案生成方法和制造方法
公开(公告)号：US06964031B2
公开(公告)日：2005-11-08
申请号：US10255832
申请日：2002-09-27
申请人： Toshiya Kotani , Satoshi Tanaka , Soichi Inoue , Sachiko Kobayashi , Hirotaka Ichiakwa
发明人： Toshiya Kotani , Satoshi Tanaka , Soichi Inoue , Sachiko Kobayashi , Hirotaka Ichiakwa
IPC分类号： H01L21/027 , G03F1/00 , G03F1/36 , G06F17/50 , H01L21/00
CPC分类号： G03F1/36
摘要： A mask pattern generation method of generating a mask pattern from a designed pattern, comprising preparing the designed pattern, preparing a correction parameter, preparing a first correction library in which a plurality of pairs of an edge coordinate group and a correction value group to correct the edge coordinate group is registered, acquiring edge coordinate groups of the designed patterns, generating a second correction library in which only the plurality of pairs of an edge coordinate group agreeing with the acquired edge coordinate group and the correction value group is registered in the first correction library and simulation using the correction parameter, and correcting the designed pattern using the second correction library.
摘要翻译：一种从设计图案生成掩模图案的掩模图案生成方法，包括准备设计图案，准备校正参数，准备第一校正库，其中多对边缘坐标组和校正值组校正第登记边缘坐标组，获取所设计图案的边缘坐标组，生成第二校正库，其中在所述第一校正中仅登记与获取的边缘坐标组和校正值组一致的边缘坐标组的多对对库和模拟，并使用第二校正库校正设计的模式。

5. 发明授权

US08142961B2 Mask pattern correcting method, mask pattern inspecting method, photo mask manufacturing method, and semiconductor device manufacturing method 有权
标题翻译：掩模图案校正方法，掩模图案检查方法，光掩模制造方法和半导体器件制造方法
公开(公告)号：US08142961B2
公开(公告)日：2012-03-27
申请号：US12717914
申请日：2010-03-04
申请人： Toshiya Kotani , Satoshi Tanaka , Shigeki Nojima , Koji Hashimoto , Soichi Inoue
发明人： Toshiya Kotani , Satoshi Tanaka , Shigeki Nojima , Koji Hashimoto , Soichi Inoue
IPC分类号： G03F1/00
CPC分类号： G06F17/5068 , G03F1/36
摘要： A pattern correcting method for correcting a design pattern to form a desired pattern on a wafer is disclosed, which comprises defining an allowable dimensional change quantity of each of design patterns, defining a pattern correction condition for the each design pattern based on the allowable dimensional change quantity defined for the each design pattern, and correcting the each design pattern based on the pattern correction condition defined for the each design pattern.
摘要翻译：公开了一种用于校正在晶片上形成期望图案的设计图案的图案校正方法，其包括限定每个设计图案的允许尺寸变化量，基于允许的尺寸变化来定义每个设计图案的图案校正条件并且基于为每个设计图案定义的图案校正条件来校正每个设计图案。

6. 再颁专利

USRE42302E1 Method for making a design layout and mask 有权
标题翻译：制作设计布局和面具的方法
公开(公告)号：USRE42302E1
公开(公告)日：2011-04-19
申请号：US11905862
申请日：2007-10-04
申请人： Toshiya Kotani , Satoshi Tanaka , Soichi Inoue
发明人： Toshiya Kotani , Satoshi Tanaka , Soichi Inoue
IPC分类号： G06F17/50 , G06F9/455 , G06F11/22
CPC分类号： G06F17/5081
摘要： A method for designing a semiconductor integrated circuit is provided which comprises compacting a design layout of a semiconductor integrated circuit on the basis of a given design rule to obtain a compacted pattern, predicting a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit on the basis of the compacted pattern, obtaining an evaluated value by comparing the predicted pattern with the compacted pattern, deciding whether the evaluated value satisfies a predetermined condition, and modifying the design rule when the evaluated value is decided as not satisfying the predetermined condition.
摘要翻译：提供了一种用于设计半导体集成电路的方法，其包括基于给定的设计规则压缩半导体集成电路的设计布局以获得压缩图案，预测在用于形成的晶片的表面区域形成的图案所述半导体集成电路基于所述压实图案，通过将所述预测图案与所述压实图案进行比较来获得评价值，判定所述评价值是否满足预定条件，以及当所述评价值被判定为不满足时修改所述设计规则预定条件。

7. 发明申请

US20100275174A1 Semiconductor device pattern creation method, pattern data processing method, pattern data processing program, and semiconductor device manufacturing method 审中-公开
标题翻译：半导体器件图案生成方法，图案数据处理方法，图案数据处理程序和半导体器件制造方法
公开(公告)号：US20100275174A1
公开(公告)日：2010-10-28
申请号：US12801895
申请日：2010-06-30
申请人： Ayako Nakano , Satoshi Tanaka , Toshiya Kotani
发明人： Ayako Nakano , Satoshi Tanaka , Toshiya Kotani
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G03F1/36
摘要： A correction target pattern having a size not more than a threshold value is extracted from first design data containing a pattern of a semiconductor integrated circuit. The first characteristic of the semiconductor integrated circuit is calculated on the basis of the first design data. Second design data is generated by correcting the correction target pattern contained in the first design data. The second characteristic of the semiconductor integrated circuit is calculated on the basis of the second design data. It is checked whether the characteristic difference between the first characteristic and the second characteristic falls within a tolerance. It is decided to use the second design data to manufacture the semiconductor integrated circuit when the characteristic difference falls within the tolerance.
摘要翻译：从包含半导体集成电路的图案的第一设计数据中提取尺寸不大于阈值的校正对象图案。基于第一设计数据计算半导体集成电路的第一特性。通过校正包含在第一设计数据中的校正目标图案来生成第二设计数据。基于第二设计数据计算半导体集成电路的第二特性。检查第一特性和第二特性之间的特性差是否落在公差之内。当特性差在公差范围内时，决定使用第二设计数据来制造半导体集成电路。

8. 发明授权

US07788626B2 Pattern data correction method, pattern checking method, pattern check program, photo mask producing method, and semiconductor device manufacturing method 有权
标题翻译：图案数据校正方法，图案检查方法，图案检查程序，光掩模制造方法和半导体器件制造方法
公开(公告)号：US07788626B2
公开(公告)日：2010-08-31
申请号：US11138407
申请日：2005-05-27
申请人： Shigeki Nojima , Satoshi Tanaka , Toshiya Kotani , Kyoko Izuha , Soichi Inoue
发明人： Shigeki Nojima , Satoshi Tanaka , Toshiya Kotani , Kyoko Izuha , Soichi Inoue
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A pattern data correction method is disclosed, which comprises preparing an integrated circuit pattern, setting a tolerance to the pattern that is allowable error range when the pattern is transferred on a substrate, creating a target pattern within the tolerance, and making correction for the target pattern to make a first correction pattern under a predetermined condition.
摘要翻译：公开了一种图案数据校正方法，其包括：准备集成电路图案，在图案在衬底上传送时设定容许误差范围的容许度，在公差内产生目标图案，并对目标进行校正模式以在预定条件下进行第一校正模式。

9. 发明申请

US20100159709A1 MASK PATTERN CORRECTING METHOD, MASK PATTERN INSPECTING METHOD, PHOTO MASK MANUFACTURING METHOD, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD 有权
标题翻译：掩模图像校正方法，掩模图案检查方法，照相胶片制造方法和半导体器件制造方法
公开(公告)号：US20100159709A1
公开(公告)日：2010-06-24
申请号：US12717914
申请日：2010-03-04
申请人： Toshiya KOTANI , Satoshi Tanaka , Shigeki Nojima , Koji Hashimoto , Soichi Inoue
发明人： Toshiya KOTANI , Satoshi Tanaka , Shigeki Nojima , Koji Hashimoto , Soichi Inoue
IPC分类号： H01L21/302 , G03F1/00
CPC分类号： G06F17/5068 , G03F1/36
摘要： A pattern correcting method for correcting a design pattern to form a desired pattern on a wafer is disclosed, which comprises defining an allowable dimensional change quantity of each of design patterns, defining a pattern correction condition for the each design pattern based on the allowable dimensional change quantity defined for the each design pattern, and correcting the each design pattern based on the pattern correction condition defined for the each design pattern.
摘要翻译：公开了一种用于校正在晶片上形成期望图案的设计图案的图案校正方法，其包括限定每个设计图案的允许尺寸变化量，基于允许的尺寸变化来定义每个设计图案的图案校正条件并且基于为每个设计图案定义的图案校正条件来校正每个设计图案。

10. 发明授权

US07120882B2 Method of setting process parameter and method of setting process parameter and/or design rule 有权
标题翻译：设置过程参数的方法和设置过程参数和/或设计规则的方法
公开(公告)号：US07120882B2
公开(公告)日：2006-10-10
申请号：US11105431
申请日：2005-04-14
申请人： Toshiya Kotani , Satoshi Tanaka , Koji Hashimoto , Soichi Inoue , Ichiro Mori
发明人： Toshiya Kotani , Satoshi Tanaka , Koji Hashimoto , Soichi Inoue , Ichiro Mori
IPC分类号： G06F17/50
CPC分类号： H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method of setting a process parameter for use in manufacturing a semiconductor integrated circuit, comprising correcting a first pattern by using process parameter information to obtain a second pattern, the first pattern being one which corresponds to a design layout of the semiconductor integrated circuit, predicting a third pattern by using the process parameter information, the third pattern being one which corresponds to the second pattern and which is to be formed on a semiconductor wafer in an etching process, obtaining an evaluation value by comparing the third pattern with the first pattern, determining whether the evaluation value satisfies a preset condition, and changing the process parameter information when the evaluation value is found not to satisfy the preset condition.
摘要翻译：公开了一种设置用于制造半导体集成电路的工艺参数的方法，包括通过使用工艺参数信息来校正第一图案以获得第二图案，第一图案是对应于半导体集成电路的设计布局的图案，通过使用处理参数信息来预测第三图案，在蚀刻工艺中，第三图案是对应于第二图案并且将形成在半导体晶片上的图案，通过将第三图案与第一图案进行比较来获得评估值判定评估值是否满足预设条件，以及当评估值不满足预设条件时，改变处理参数信息。

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