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热词
    • 3. 发明授权
    • Phase-locked loop circuit
    • 锁相环电路
    • US4929917A
    • 1990-05-29
    • US288575
    • 1988-12-22
    • Fumihiko YokogawaRyuichi Naito
    • Fumihiko YokogawaRyuichi Naito
    • G11B7/005G11B20/14H03L7/00H03L7/089H03L7/093H03L7/10H03L7/14
    • H03L7/089G11B20/1403H03L7/093G11B7/005
    • A phase-locked loop circuit (PLL) to which a phase-synchronization signal is intermittently supplied, both of the natural angular frequency of the PLL and the damping factor of the same are so determined as to prevent a phase difference produced at the next sampling point from exceeding the linear property range of a phase comparator even when the extraneous electrical disturbance enters the PLL. In addition, when the level of a clock control signal supplied to a variable frequency oscillator which varies the clock signal of the PLL in phase and frequency exceeds a predetermined value, the level of the clock control signal is limited to the predetermined value. As a result, it is possible to prevent the output signal of the phase difference from having any discontinuity.
    • 间歇地提供相位同步信号的锁相环电路(PLL)被确定为PLL的固有角频率和其阻尼因子,以防止在下一次采样时产生的相位差 即使当外部电气干扰进入PLL时,超出相位比较器的线性特性范围。 此外,当提供给变频PLL的时钟信号在相位和频率上变化的可变频率振荡器的时钟控制信号的电平超过预定值时,时钟控制信号的电平被限制为预定值。 结果,可以防止相位差的输出信号具有任何不连续性。