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1. 发明授权

US09837138B1 Semiconductor device 有权
公开(公告)号：US09837138B1
公开(公告)日：2017-12-05
申请号：US15438411
申请日：2017-02-21
申请人： SK hynix Inc.
发明人： Hong Ki Moon , Jeong Tae Hwang
IPC分类号： G11C7/00 , G11C11/406 , G11C11/4093
CPC分类号： G11C11/40615 , G11C11/4072 , G11C11/4093
摘要： A semiconductor device may be provided. The semiconductor device may include an input signal generator configured to enable an input signal although a reset signal is disabled after a clock enable signal is enabled. The semiconductor device may include a self-refresh enable signal generator configured to generate a self-refresh enable signal based on the input signal.

2. 发明授权

US12040801B2 Random pulse generator and memory 有权
公开(公告)号：US12040801B2
公开(公告)日：2024-07-16
申请号：US17976096
申请日：2022-10-28
申请人： SK hynix Inc.
发明人： Hong Ki Moon
IPC分类号： H03K3/84 , G01R31/30
CPC分类号： H03K3/84 , G01R31/30
摘要： A random pulse generator includes: a randomness test circuit suitable for testing randomness of a random pulse; a control circuit suitable for generating frequency control information and puke control information based on a test result of the randomness test circuit; a periodic wave generating circuit suitable for generating a periodic wave whose frequency is changed based on the frequency control information; and a pulse generating circuit suitable for generating the random pulse based on the periodic wave and the pulse control information.

3. 发明授权

US09570194B1 Device for detecting fuse test mode using a fuse and method therefor 有权
标题翻译：使用保险丝检测保险丝测试模式的装置及其方法
公开(公告)号：US09570194B1
公开(公告)日：2017-02-14
申请号：US14959101
申请日：2015-12-04
申请人： SK hynix Inc.
发明人： Hong Ki Moon
IPC分类号： G11C17/18 , G11C17/16 , G11C29/02 , G11C7/10 , G11C29/00 , G11C7/22
CPC分类号： G11C7/22 , G11C7/1018 , G11C29/027 , G11C29/46 , G11C29/787
摘要： A fuse test mode detection device is disclosed, which relates to a technology for improving detection efficiency of a fuse test mode. The fuse test mode detection device includes: a fuse unit configured to scan a plurality of fuses in a boot-up operation, and output fuse data; a counter configured to count the fuse data in response to a clock signal; a decoding unit configured to output a decoding signal for controlling a fuse test mode in response to an output signal of the counter; an encoder configured to encode the output signal of the decoding unit, and output a code signal; and a comparator configured to compare the fuse data with the code signal, and output a comparison signal.
摘要翻译：公开了一种用于提高保险丝测试模式的检测效率的技术的熔丝测试模式检测装置。熔丝测试模式检测装置包括：熔丝单元，被配置为在启动操作中扫描多个保险丝，并输出熔丝数据; 配置为响应于时钟信号对熔丝数据进行计数的计数器; 解码单元，被配置为响应于所述计数器的输出信号输出用于控制熔丝测试模式的解码信号; 编码器，被配置为对解码单元的输出信号进行编码，并输出代码信号; 以及比较器，被配置为将所述熔丝数据与所述代码信号进行比较，并输出比较信号。

4. 发明授权

US12124397B2 Data bus inversion circuit and semiconductor apparatus including the same 有权
公开(公告)号：US12124397B2
公开(公告)日：2024-10-22
申请号：US18173791
申请日：2023-02-24
申请人： SK hynix Inc.
发明人： Hong Ki Moon , Seok Bo Shim
IPC分类号： G06F13/42
CPC分类号： G06F13/4221
摘要： The present technology may include a first latch circuit configured to store, as first data, data that is transmitted through a first signal line, a second latch circuit configured to store, as a plurality of second data, the data that is transmitted through the first signal line by sorting the data by a plurality of second signal lines that are connected to the first signal line in common, and a data bus inversion engine configured to selectively perform a first mode in which the data bus inversion engine generates a data bus inversion flag by comparing the first data with current input data and a second mode in which the data bus inversion engine generates the data bus inversion flag by comparing the plurality of second data with the current input data.

5. 发明公开

US20230402999A1 RANDOM PULSE GENERATOR AND MEMORY 审中-公开
公开(公告)号：US20230402999A1
公开(公告)日：2023-12-14
申请号：US17976096
申请日：2022-10-28
申请人： SK hynix Inc.
发明人： Hong Ki Moon
IPC分类号： H03K3/84 , G01R31/30
CPC分类号： H03K3/84 , G01R31/30
摘要： A random pulse generator includes: a randomness test circuit suitable for testing randomness of a random pulse; a control circuit suitable for generating frequency control information and puke control information based on a test result of the randomness test circuit; a periodic wave generating circuit suitable for generating a periodic wave whose frequency is changed based on the frequency control information; and a pulse generating circuit suitable for generating the random pulse based on the periodic wave and the pulse control information.

6. 发明授权

US11651832B2 Memory device and test method thereof 有权
公开(公告)号：US11651832B2
公开(公告)日：2023-05-16
申请号：US17146958
申请日：2021-01-12
申请人： SK hynix Inc.
发明人： Hong Ki Moon , Seung Woo Lee , Dong Hee Han
IPC分类号： G11C29/42 , G11C29/44 , G11C8/18 , G11C29/12 , G11C7/10 , G11C29/46
CPC分类号： G11C29/42 , G11C7/106 , G11C8/18 , G11C29/12015 , G11C29/44 , G11C29/46
摘要： A memory device includes: a normal cell region suitable for storing write data and outputting read data; a parity cell region suitable for storing write parity bits and outputting read parity bits; a pattern generation circuit suitable for generating test data whose value is sequentially increased, and providing the test data as the write data, in a first test mode; an error correction circuit suitable for generating the write parity bits based on the write data, correcting an error of the read data based on the read parity bits, and outputting the error-corrected data; and an output circuit suitable for compressing the error-corrected data and outputting the compressed data, wherein the output circuit is further suitable for compressing the read parity bits output from the parity cell region to output the compressed data, in the first test mode.

7. 发明授权

US09653145B1 Semiconductor devices and semiconductor systems including the same 有权
公开(公告)号：US09653145B1
公开(公告)日：2017-05-16
申请号：US15218544
申请日：2016-07-25
申请人： SK hynix Inc.
发明人： Hong Ki Moon , Jeong Tae Hwang
IPC分类号： G11C11/40 , G01K13/00 , G11C11/406
CPC分类号： G11C11/40626 , G01K13/00 , G11C29/02 , G11C29/028 , G11C29/12015 , G11C29/46
摘要： A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs first to (M+1)th command/address signals (wherein, “M” denotes a natural number which is equal to or greater than two) and receives a detection signal to detect a normality/abnormality of a temperature sensor. The second semiconductor device enters a test mode in response to the (M+1)th command/address signal and compare first to Nth sensing codes (wherein, “N” denotes a natural number which is equal to or greater than two) generated by the temperature sensor with the first to Mth command/address signals to generate the detection signal. The second semiconductor device also executes a refresh operation in response to a refresh signal including a plurality of pulses whose cycle time is controlled by the first to Mth command/address signals.

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