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1. 发明申请

US20190294374A1 MEMORY SYSTEM INCLUDING MEMORY DEVICE AND MEMORY CONTROLLER, AND OPERATING METHOD THEREOF 审中-公开
公开(公告)号：US20190294374A1
公开(公告)日：2019-09-26
申请号：US16234768
申请日：2018-12-28
申请人： SK hynix Inc.
发明人： Hae-Rang CHOI
IPC分类号： G06F3/06 , G11C11/408 , G11C11/4091 , G11C11/4096 , G06F11/10 , G11C29/52 , G06F12/06
摘要： A memory system includes a memory device including a plurality of memory cells, and a memory controller suitable for generating a second address based on a first address indicating a defective memory cell, among the plurality of memory cells, and sequentially transmitting the first address and a first command corresponding to the first address, and the second address and a second command corresponding to the second address to the memory device, during write and read operations of the defective memory cell.

2. 发明申请

US20130294186A1 PHASE-LOCKED LOOP AND INTEGRATED CIRCUIT CHIP INCLUDING THE SAME, AND TEST SYSTEM INCLUDING THE INTEGRATED CIRCUIT CHIP 有权
标题翻译：相位锁定环路和集成电路芯片，包括集成电路芯片的测试系统
公开(公告)号：US20130294186A1
公开(公告)日：2013-11-07
申请号：US13714357
申请日：2012-12-13
申请人： SK HYNIX INC.
发明人： Hae-Rang CHOI , Joo-Hwan CHO , Kwang-Jin NA , Kwan-Dong KIM
IPC分类号： H03L7/08 , G11C29/08 , H03K21/00
CPC分类号： H03L7/08 , G11C29/023 , G11C29/028 , G11C29/08 , H03K21/00 , H03K21/023 , H03L7/099 , H03L7/16 , H03L7/18
摘要： A phase-locked loop includes a phase detection unit configured to compare the phase of a feedback clock with the phase of an input clock, a clock generation unit configured to adjust the frequency of a first clock based on a result of the comparison of the phase detection unit, a first division unit configured to generate an output clock by dividing the first clock at a first division ratio in test mode and generate the output clock by dividing the first clock at a second division ratio that is lower than the first division ratio in normal mode, and a second division unit configured to generate the feedback clock by dividing the output clock.
摘要翻译：锁相环包括相位检测单元，被配置为将反馈时钟的相位与输入时钟的相位进行比较;时钟生成单元，被配置为基于相位的比较结果来调整第一时钟的频率检测单元，第一分割单元，被配置为通过在测试模式中以第一分频比除以第一时钟而产生输出时钟，并且通过以低于第一分频比的第二分频比除以第一时钟而产生输出时钟以及第二分割单元，被配置为通过分割输出时钟来产生反馈时钟。

3. 发明申请

US20160164504A1 LATCH CIRCUIT 有权
标题翻译：锁定电路
公开(公告)号：US20160164504A1
公开(公告)日：2016-06-09
申请号：US14678704
申请日：2015-04-03
申请人： SK hynix Inc.
发明人： Hae-Rang CHOI , Mi-Hyun HWANG
IPC分类号： H03K3/356
CPC分类号： H03K3/356147 , H03K3/356104 , H03K3/356182
摘要： A latch circuit includes a first PMOS transistor suitable for pull-up driving a second node based on a voltage of a first node, a first NMOS transistor suitable for pull-down driving the second node based on a voltage of the first node, a second PMOS transistor suitable for pull-up driving the first node based on a voltage of the second node, a second NMOS transistor suitable for pull-down driving the first node based on a voltage of the second node, a first separation element suitable for electrically separating the first NMOS transistor from the second node when the first PMOS transistor is turned on, and a second separation element suitable for electrically separating the second NMOS transistor from the first node when the second PMOS transistor is turned on.
摘要翻译：锁存电路包括：第一PMOS晶体管，其适于基于第一节点的电压上拉驱动第二节点;第一NMOS晶体管，其适于基于第一节点的电压下拉驱动第二节点;第二NMOS晶体管， PMOS晶体管，其适于基于第二节点的电压上拉驱动第一节点;第二NMOS晶体管，适于基于第二节点的电压来下拉驱动第一节点;第一分离元件，适于电分离当第一PMOS晶体管导通时来自第二节点的第一NMOS晶体管，以及适于在第二PMOS晶体管导通时将第二NMOS晶体管与第一节点电分离的第二分离元件。

4. 发明申请

US20150200655A1 DUTY CYCLE CORRECTION CIRCUIT AND OPERATION METHOD THEREOF 审中-公开
公开(公告)号：US20150200655A1
公开(公告)日：2015-07-16
申请号：US14668488
申请日：2015-03-25
申请人： SK hynix Inc.
发明人： Shin-Deok KANG , Jae-Min JANG , Yong-Ju KIM , Hae-Rang CHOI
IPC分类号： H03K3/017
CPC分类号： H03K3/017 , H03K5/1565
摘要： A duty cycle correction circuit includes a clock adjustment unit configured to adjust a duty ratio of an input clock signal in response to a duty control signal and generate an output clock signal, a tracking type setting unit configured to generate an tracking type selection signal for setting a first or second tracking type based on a duty locking state of the output clock signal, and a control signal generation unit configured to generate the duty control signal, into which the first or second tracking type is incorporated, in response to the tracking type selection signal and the output clock signal.

5. 发明申请

US20140103981A1 COUNTING CIRCUIT OF SEMICONDUCTOR DEVICE AND DUTY CORRECTION CIRCUIT OF SEMICONDUCTOR DEVICE USING THE SAME 有权
标题翻译：使用其的半导体器件的半导体器件的计数电路和占空比校正电路
公开(公告)号：US20140103981A1
公开(公告)日：2014-04-17
申请号：US14133063
申请日：2013-12-18
申请人： SK hynix Inc.
发明人： Hae-Rang CHOI , Yong-Ju KIM
IPC分类号： H03K5/156
CPC分类号： H03K5/1565 , H03K21/38
摘要： A counting circuit of a semiconductor device includes a plurality of counting units configured to count respective bits of counting codes in response to a plurality of counting clocks, respectively, and to control in a counting direction in response to a counting control signal; a clock toggling control unit configured to control the number of counting clocks that toggle among the plurality of counting clocks in response to clock control signals; and a counting operation control unit configured to compare a value of target codes and a value of the counting codes, and to determine a value of the counting control signal according to a comparison result.
摘要翻译：半导体器件的计数电路包括多个计数单元，其被配置为分别响应于多个计数时钟对计数代码的各个位进行计数，并且响应于计数控制信号而在计数方向上进行控制; 时钟切换控制单元，被配置为响应于时钟控制信号来控制在多个计数时钟之间切换的计数时钟的数量; 以及计数操作控制单元，被配置为比较目标代码的值和计数代码的值，并且根据比较结果确定计数控制信号的值。

6. 发明申请

US20180358972A1 CLOCK GENERATION CIRCUIT 审中-公开
公开(公告)号：US20180358972A1
公开(公告)日：2018-12-13
申请号：US16106658
申请日：2018-08-21
申请人： SK hynix Inc.
发明人： Hae-Rang CHOI , Yong-Ju KIM , Dae-Han KWON , Shin-Deok KANG
IPC分类号： H03K23/66 , G06F1/04
CPC分类号： H03K23/662 , G06F1/04
摘要： A clock generation circuit includes a clock generation unit suitable for generating a first clock, a first inversion clock having an opposite phase to the first clock, a second clock having a different phase from the first clock, and a second inversion clock having an opposite phase to the second clock; and a reset control unit suitable for comparing the phases of the first and second clocks, and controlling the clock generation unit to disable for a time and then enable the second clock and the second inversion clock when the second clock leads the first clock.

7. 发明申请

US20180108400A1 MEMORY DEVICE AND OPERATING METHOD THEREOF 审中-公开
公开(公告)号：US20180108400A1
公开(公告)日：2018-04-19
申请号：US15641844
申请日：2017-07-05
申请人： SK hynix Inc.
发明人： Hae-Rang CHOI
IPC分类号： G11C11/4093 , G11C29/12 , G11C11/4091 , G11C11/406
CPC分类号： G11C11/4093 , G11C11/40611 , G11C11/4085 , G11C11/4091 , G11C11/4094 , G11C29/12005 , G11C29/1201 , G11C29/18 , G11C29/50012 , G11C29/50016 , G11C2029/1202 , G11C2029/1204 , G11C2029/5004
摘要： A memory device includes a plurality of word lines; a plurality of bit lines; a plurality of memory cells, each memory cell coupled to a corresponding word line among the plurality of word lines and a corresponding bit line among the plurality of bit lines; and a control block suitable for controlling at least two word lines among the plurality of word lines to be activated together, and determining whether or not a weak cell exists, based on a voltage of a bit line corresponding to the activated word lines.

8. 发明申请

US20150042387A1 DATA RECOVERY CIRCUIT AND OPERATING METHOD THEREOF 有权
标题翻译：数据恢复电路及其操作方法
公开(公告)号：US20150042387A1
公开(公告)日：2015-02-12
申请号：US14106817
申请日：2013-12-15
申请人： Industry-University Cooperation Foundation Hanyang University , SK hynix Inc.
发明人： Hae-Rang CHOI , Yong-Ju KIM , Oh-Kyong KWON , Kang-Sub KWAK , Jun-Yong SONG , Hyeon-Cheon SEOL
IPC分类号： H03L7/08
CPC分类号： H03L7/0807 , H04L7/0337 , H04L7/044
摘要： A data recovery circuit may include a data sampling unit suitable for sampling source data including an edge data using data clocks and an edge clock, a data extraction unit suitable for extracting the edge data from sampled data outputted from the data sampling unit, a control signal generation unit suitable for generating a phase control signal in response to the edge data, and a multi-clock control unit suitable for controlling phases of the data clocks and the edge clock in response to the phase control signal.
摘要翻译：数据恢复电路可以包括适于使用数据时钟和边沿时钟对包括边缘数据的源数据进行采样的数据采样单元，适合于从数据采样单元输出的采样数据中提取边缘数据的数据提取单元，控制信号适用于响应于边缘数据产生相位控制信号的多时钟单元，以及适于根据相位控制信号控制数据时钟和边沿时钟的相位的多时钟控制单元。

9. 发明申请

US20130222025A1 PHASE LOCKED LOOP 有权
标题翻译：相位锁定环
公开(公告)号：US20130222025A1
公开(公告)日：2013-08-29
申请号：US13844865
申请日：2013-03-16
申请人： SK HYNIX INC.
发明人： Hae-Rang CHOI , Yong-Ju KIM , Jae-Min JANG
IPC分类号： H03L7/14
CPC分类号： H03L7/14 , H03L7/113
摘要： A phase locked loop includes a phase detector configured to compare a phase of an input clock with a phase of a feedback clock to produce a phase comparison result, an initial frequency value provider configured to detect a frequency of the input clock and provide a frequency detection result, a controller configured to generate a frequency control signal based on the phase comparison result and the frequency detection result, and an oscillator configured to generate an output clock in response to the frequency control signal.
摘要翻译：锁相环包括相位检测器，被配置为将输入时钟的相位与反馈时钟的相位进行比较以产生相位比较结果，初始频率值提供器被配置为检测输入时钟的频率并提供频率检测结果，配置为基于相位比较结果和频率检测结果产生频率控制信号的控制器，以及响应于频率控制信号产生输出时钟的振荡器。

10. 发明申请

US20180151250A1 MEMORY DEVICE 审中-公开
公开(公告)号：US20180151250A1
公开(公告)日：2018-05-31
申请号：US15682685
申请日：2017-08-22
申请人： SK hynix Inc.
发明人： Hae-Rang CHOI , Sung-Soo CHI , Dong-Jae LEE
IPC分类号： G11C29/00 , G11C29/42
CPC分类号： G11C29/783 , G11C29/42 , G11C29/50016
摘要： A memory device may include: a plurality of memory cells; a weak cell information storage unit suitable for storing a weak address and parity information corresponding to one or more weak cells having a shorter data retention time than a reference time, among the plurality of memory cells; an ECC (Error Correction Code) circuit suitable for detecting and correcting an error bit of the one or more weak cells using the parity information; and a refresh control unit suitable for controlling the plurality of memory cells to be refreshed at a cycle equal to or more than the reference time.

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