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1. 发明申请

US20090096555A1 MOTHERBOARD 失效
标题翻译：母板
公开(公告)号：US20090096555A1
公开(公告)日：2009-04-16
申请号：US11942727
申请日：2007-11-20
申请人： SHOU-KUO HSU , CHIEN-HUNG LIU , CHENG-SHIEN LI
发明人： SHOU-KUO HSU , CHIEN-HUNG LIU , CHENG-SHIEN LI
IPC分类号： H01P5/12
CPC分类号： G06F13/409
摘要： A motherboard includes a signal control chip, a signal switch chip connected to the signal control chip via a plurality of first transmission lines, and a complex connector configured for connecting to a first type of transmission device or a second type of transmission device. The signal control chip is connected to the complex connector via the first transmission lines and a plurality of second transmission lines. The signal switch chip is electrically connected to the complex connector via a plurality of third transmission lines. Each second transmission line is connected in series with a first resistor. Each third transmission line is connected in series with a second resistor. When the first type of transmission device is mounted on the complex connector, the signal switch chip and the second resistors are removed. When the second type of transmission device is mounted on the complex connector, the first resistors are removed.
摘要翻译：主板包括信号控制芯片，通过多个第一传输线连接到信号控制芯片的信号开关芯片，以及被配置为连接到第一类型的传输设备或第二类型的传输设备的复合连接器。信号控制芯片通过第一传输线和多条第二传输线连接到复合连接器。信号开关芯片通过多条第三传输线与复合连接器电连接。每个第二传输线与第一电阻器串联连接。每个第三传输线与第二电阻器串联连接。当第一类型的传输装置安装在复合连接器上时，信号开关芯片和第二电阻器被去除。当第二类型的传输装置安装在复合连接器上时，第一电阻器被去除。

2. 发明申请

US20070129921A1 SYSTEM AND METHOD FOR GENERATING VARIOUS SIMULATION CONDITIONS FOR SIMULATION ANALYSIS 失效
标题翻译：用于生成各种模拟条件的系统和方法进行模拟分析
公开(公告)号：US20070129921A1
公开(公告)日：2007-06-07
申请号：US11309042
申请日：2006-06-13
申请人： SHOU-KUO HSU , CHENG-SHIEN LI
发明人： SHOU-KUO HSU , CHENG-SHIEN LI
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F17/5009 , G06F17/5036 , G06F2217/10
摘要： A system for generating various simulation conditions for simulation analysis is disclosed. The system includes: a signal generating module (301) for generating an N-bit binary sequence consisting of “1” and “0” according to signal source parameters; a application module (302) for applying the N-bit binary sequence to generate the various simulation conditions according to control parameters; a noise generating module (303) for generating N influence values of Gauss noises with N standard deviations to N signal bit-widths; and an addition module (304) for adding the Gauss noises to corresponding digital waveform positions of the generated simulation conditions. A related method is also disclosed.
摘要翻译：公开了一种用于生成用于模拟分析的各种模拟条件的系统。该系统包括：根据信号源参数产生由“1”和“0”组成的N位二进制序列的信号产生模块（301）应用模块（302），用于根据控制参数应用所述N位二进制序列以产生各种仿真条件; 噪声产生模块（303），用于产生具有N个标准偏差N个信号位宽的高斯噪声的N个影响值; 以及用于将高斯噪声加到所产生的模拟条件的相应数字波形位置的加法模块（304）。还公开了相关方法。

3. 发明申请

US20080010622A1 SYSTEM AND METHOD FOR ANALYZING RESPONSE VALUES SUM OF DIFFERENTIAL SIGNALS 有权
标题翻译：用于分析差分信号响应值的系统和方法
公开(公告)号：US20080010622A1
公开(公告)日：2008-01-10
申请号：US11615008
申请日：2006-12-22
申请人： SHOU-KUO HSU , CHENG-SHIEN LI
发明人： SHOU-KUO HSU , CHENG-SHIEN LI
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/504
摘要： A method for analyzing response values sum of differential signals includes: receiving configurations of simulation parameters; simulating differential signal paths with an analog transmission channel according to a design file; analyzing the analog transmission channel into different channel modes according to received configurations; simulating a plurality of pulse signals into the analog transmission channel according to the received configurations, and recording an impulse response of each of the channel modes; simulating differential signal transmissions of the differential signals according to the received configurations, and analyzing the differential signal transmissions into different signal modes corresponding to the different channel modes; transforming each signal mode and the impulse response of a corresponding channel mode to respectively generate a first value and a second value by utilizing Fast Fourier Transform Algorithm; multiplying the first value by the second value to generate a third value, and transforming the third value to a fourth value by utilizing an Inverse Fast Fourier Transform Algorithm; and summing all the fourth values corresponding to all of the channel modes to be the response values sum of the differential signals. A related system is also disclosed.
摘要翻译：用于分析差分信号的响应值和的方法包括：接收模拟参数的配置; 根据设计文件用模拟传输通道模拟差分信号路径; 根据接收的配置，将模拟传输信道分析成不同的信道模式; 根据接收到的配置将多个脉冲信号模拟成模拟传输信道，并记录每个信道模式的脉冲响应; 根据接收到的配置模拟差分信号的差分信号传输，并将差分信号传输分析成对应于不同信道模式的不同信号模式; 通过利用快速傅立叶变换算法来变换每个信号模式和相应信道模式的脉冲响应，分别产生第一值和第二值; 将第一值乘以第二值以产生第三值，并且通过利用快速傅里叶逆变换算法将第三值变换为第四值; 并将与所有信道模式相对应的所有第四值求和作为差分信号的响应值和。还公开了相关系统。

4. 发明申请

US20090086561A1 MOTHERBOARD FOR SUPPORTING DIFFERENT TYPES OF MEMORIES 有权
标题翻译：支持不同类型的记忆的主板
公开(公告)号：US20090086561A1
公开(公告)日：2009-04-02
申请号：US11952140
申请日：2007-12-07
申请人： SHOU-KUO HSU , DUEN-YI HO , CHENG-SHIEN LI
发明人： SHOU-KUO HSU , DUEN-YI HO , CHENG-SHIEN LI
IPC分类号： G11C5/14 , H05K1/11
CPC分类号： G06F1/26 , G11C5/04 , G11C5/147 , H05K1/0262 , H05K1/14 , H05K2201/044 , H05K2201/09954 , H05K2201/10159
摘要： An exemplary motherboard includes a driving module, a first slot module arranged for mounting a first type of memory and connected to the driving module via a first channel, a second slot module arranged for mounting a second type of memory and connected to the driving module via a second channel, and a voltage regulator electronically connected to the first slot module and the second slot module. The first memory and the second memory are alternatively mounted on the motherboard, the voltage regulator detects which type memory is currently mounted on the motherboard and outputs voltages suitable for the type of the memory mounted on the motherboard accordingly.
摘要翻译：示例性主板包括驱动模块，布置成用于安装第一类型存储器并经由第一通道连接到驱动模块的第一插槽模块，布置成用于安装第二类型存储器并连接到驱动模块的第二插槽模块，其经由第二通道和电连接到第一插槽模块和第二插槽模块的电压调节器。第一存储器和第二存储器替代地安装在母板上，电压调节器检测当前安装在母板上的哪种类型的存储器，并相应地输出适合安装在母板上的存储器类型的电压。

5. 发明申请

US20100289601A1 OVERDRIVE TOPOLOGY STRUCTURE FOR TRANSMISSION OF RGB SIGNAL 失效
标题翻译：用于传输RGB信号的扩展拓扑结构
公开(公告)号：US20100289601A1
公开(公告)日：2010-11-18
申请号：US12483260
申请日：2009-06-12
申请人： SHOU-KUO HSU , YU-CHANG PAI , CHENG-SHIEN LI , JIA-CHI CHEN
发明人： SHOU-KUO HSU , YU-CHANG PAI , CHENG-SHIEN LI , JIA-CHI CHEN
IPC分类号： H01P3/00
CPC分类号： H04L25/0278 , G09G5/04 , G09G2300/0426
摘要： An overdrive topology structure for transmission of a RGB signal includes a signal sending terminal, a signal receiving terminal, and a transmission line to transmit the RGB signal from the signal sending terminal to the signal receiving terminal. The transmission line is divided into a number of section transmission lines. A node is formed between every two section transmission lines. An impedance of a first section transmission line approaching to the signal sending terminal is less than an impedance of a second section transmission line approaching to the first section transmission line to overdrive the RGB signal at a first node between the first and second section transmission lines. At least one node except the first node is grounded via a resistor. An equivalent resistance of the resistor is equal to a resistance of the first resistor.
摘要翻译：用于传输RGB信号的过驱动拓扑结构包括信号发送端，信号接收端和传输线，以将RGB信号从信号发送端发送到信号接收端。传输线被分成多个部分传输线。在每两段传输线之间形成节点。接近信号发送端的第一部分传输线的阻抗小于接近第一部分传输线的第二部分传输线的阻抗，以在第一和第二部分传输线之间的第一节点处过驱动RGB信号。除第一个节点之外的至少一个节点通过电阻器接地。电阻器的等效电阻等于第一电阻器的电阻。

6. 发明申请

US20100007429A1 PRINTED CIRCUIT BOARD 失效
标题翻译：印刷电路板
公开(公告)号：US20100007429A1
公开(公告)日：2010-01-14
申请号：US12205146
申请日：2008-09-05
申请人： CHENG-SHIEN LI , YUNG-CHIEH CHEN , SHOU-KUO HSU
发明人： CHENG-SHIEN LI , YUNG-CHIEH CHEN , SHOU-KUO HSU
IPC分类号： H01P3/08
CPC分类号： H05K1/0245 , H05K1/0366 , H05K2201/029 , H05K2201/09236 , H05K2201/09263 , H05K2201/09272
摘要： A printed circuit board includes a plurality of differential pairs arranged thereon side-by-side. Each differential pair includes two transmission lines. Each transmission line includes a plurality of sections of equal length. Every two adjacent sections in each transmission line meet at an angle, and all angles are equal. The length of each section is determined by dividing the distance between two corresponding angles of the two transmission lines of each differential pair by the cosine of half of the angle.
摘要翻译：印刷电路板包括并排布置的多个差分对。每个差分对包括两条传输线。每个传输线包括多个相等长度的部分。每个传输线中的每两个相邻部分以一定角度相交，并且所有角度相等。每个部分的长度通过将每个差分对的两个传输线的两个对应角度之间的距离除以角度的一半的余弦来确定。

7. 发明申请

US20080059685A1 MOTHERBOARD 失效
标题翻译：母板
公开(公告)号：US20080059685A1
公开(公告)日：2008-03-06
申请号：US11759238
申请日：2007-06-07
申请人： SHOU-KUO HSU , CHENG-SHIEN LI
发明人： SHOU-KUO HSU , CHENG-SHIEN LI
IPC分类号： G06F13/36
CPC分类号： G06F13/4068 , G06F2213/0024 , H05K1/029 , H05K1/0295 , H05K2201/10363
摘要： A motherboard includes a chipset, a first connector pad suitable for receiving a first type of PCI connector, a second connector pad suitable for receiving a second type of PCI connector, a plurality of first transmission lines, a plurality of second transmission lines, and a plurality of areas for mounting switches. One end of each first transmission line is connected to the chipset, another end of each first transmission line is connected to an end of a corresponding area, one end of each second transmission line is connected to another end of the corresponding area, another end of each second transmission line is connected to the second connector pad, the first connector pad is connected to the plurality of first transmission lines, and the switches are selectively mounted on the plurality of areas.
摘要翻译：主板包括芯片组，适于接收第一类型的PCI连接器的第一连接器焊盘，适于接收第二类型的PCI连接器的第二连接器焊盘，多个第一传输线，多条第二传输线，以及多个安装开关的区域。每个第一传输线的一端连接到芯片组，每个第一传输线的另一端连接到相应区域的一端，每个第二传输线的一端连接到相应区域的另一端，另一端每个第二传输线连接到第二连接器焊盘，第一连接器焊盘连接到多个第一传输线，并且开关选择性地安装在多个区域上。

8. 发明申请

US20080041618A1 PRINTED CIRCUIT BOARD WITH REDUCED CROSSTALK EFFECT BETWEEN TRANSMISSION LINES THEREIN 有权
标题翻译：印刷电路板，其传输线之间具有降低的CROSSTALK效应
公开(公告)号：US20080041618A1
公开(公告)日：2008-02-21
申请号：US11759239
申请日：2007-06-07
申请人： SHOU-KUO HSU , YU-CHANG PAI , CHENG-SHIEN LI
发明人： SHOU-KUO HSU , YU-CHANG PAI , CHENG-SHIEN LI
IPC分类号： H05K1/16 , H05K1/02
CPC分类号： H05K1/0228 , H05K2201/09236 , H05K2201/10189
摘要： A printed circuit board includes a first signal layer, a second signal layer, a plurality of transmission lines respectively including first segments laid in parallel on the first signal layer and second segments laid in parallel on the second signal layer, and a plurality of vias, each via connecting the first segment with the second segment of a corresponding transmission line. One of the plurality of transmission lines has the first segment positioned in the middle of an array defined by the first segments of the plurality of transmission lines, and a second segment positioned in an outmost position of an array defined by the second segments of the plurality of transmission lines. The printed circuit board reduces the possibility of false action of electronic components coupled to transmission lines, which is caused by the crosstalk between transmission lines.
摘要翻译：印刷电路板包括第一信号层，第二信号层，分别包括在第一信号层上平行放置的第一段和在第二信号层上并联放置的第二段的多条传输线，以及多个通孔，每个通过将第一段连接到相应传输线的第二段。多个传输线中的一个具有位于由多个传输线的第一段限定的阵列的中间的第一段，以及位于由多个传输线中的第二段定义的阵列的最外部位置的第二段的传输线。印刷电路板减少了由传输线之间的串扰引起的耦合到传输线的电子部件的错误动作的可能性。

9. 发明申请

US20100012363A1 PRINTED CIRCUIT BOARD AND LAYOUT METHOD THEREOF 有权
标题翻译：印刷电路板及其布局方法
公开(公告)号：US20100012363A1
公开(公告)日：2010-01-21
申请号：US12329614
申请日：2008-12-07
申请人： YUNG-CHIEH CHEN , CHENG-SHIEN LI , SHOU-KUO HSU
发明人： YUNG-CHIEH CHEN , CHENG-SHIEN LI , SHOU-KUO HSU
IPC分类号： H05K1/18 , G06F17/50
CPC分类号： H05K1/0295 , H05K1/0231 , H05K1/0237 , H05K1/0243 , H05K1/113 , H05K2201/09236 , H05K2201/09954 , H05K2201/10545 , H05K2201/10636 , H05K2201/10689 , Y02P70/611 , Y10T29/49117 , Y10T29/4913
摘要： A printed circuit board coupling includes a first layout layer, a second layout layer, a pair of connecting portions, a first component and a second component. The first layout layer has a pair of first conducting portions which is disposed thereon to couple with a control chip. The second layout layer has a pair of second conducting portions, third conducting portions, and fourth conducting portions all of which are sequentially disposed thereon. The connecting portions are coupled with the first conducting portions and the third conducting portions. In a first coupling mode, an electronic device is coupled with the second conducting portions, and first and second components are coupled with the third and fourth conducting portions. In a second coupling mode, the electronic device is coupled with the fourth conducting portions, and the first and the second components are coupled with the second and third conducting portions.
摘要翻译：印刷电路板耦合包括第一布局层，第二布局层，一对连接部分，第一部件和第二部件。第一布局层具有一对第一导电部分，其布置在其上以与控制芯片耦合。第二布局层具有一对第二导电部分，第三导电部分和第四导电部分，所有这些都顺序地设置在其上。连接部分与第一导电部分和第三导电部分耦合。在第一耦合模式中，电子器件与第二导电部分耦合，并且第一和第二部件与第三和第四导电部分耦合。在第二耦合模式中，电子器件与第四导电部分耦合，并且第一和第二部件与第二和第三导电部分耦合。

10. 发明申请

US20090103385A1 MOTHERBOARD FOR SUPPORTING DIFFERENT TYPES OF MEMORIES 有权
标题翻译：支持不同类型的记忆的主板
公开(公告)号：US20090103385A1
公开(公告)日：2009-04-23
申请号：US11965753
申请日：2007-12-28
申请人： SHOU-KUO HSU , DUEN-YI HO , CHENG-SHIEN LI
发明人： SHOU-KUO HSU , DUEN-YI HO , CHENG-SHIEN LI
IPC分类号： G11C5/14 , H05K1/11
CPC分类号： G06F13/4072 , G06F13/4239 , H05K1/0262 , H05K1/14 , H05K2201/044 , H05K2201/09954 , H05K2201/10159
摘要： An exemplary motherboard includes a driving module, at least two first slots arranged for mounting two first type of memories, at least two second slots arranged for mounting two second type of memories, and a voltage regulator. The driving module is electronically connected to the at least two first slots, the at least two second slots, and the voltage regulator in turn via a channel. The first type of memories and the second type of memories are alternatively mounted on the motherboard, the voltage regulator detects which type memory is currently mounted on the motherboard and outputs voltages suitable for the type of memory mounted on the motherboard accordingly.
摘要翻译：示例性主板包括驱动模块，布置成用于安装两个第一类型存储器的至少两个第一槽，布置成安装两个第二类型存储器的至少两个第二槽和电压调节器。驱动模块通过通道电连接到至少两个第一插槽，至少两个第二插槽和电压调节器。第一类型的存储器和第二类型的存储器交替地安装在母板上，电压调节器检测当前安装在母板上的哪种类型的存储器，并相应地输出适合于安装在母板上的存储器类型的电压。

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