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1. 发明授权

US07668010B2 Flash memory having insulating liners between source/drain lines and channels 有权
标题翻译：闪存在源极/漏极线和通道之间具有绝缘衬垫
公开(公告)号：US07668010B2
公开(公告)日：2010-02-23
申请号：US12038612
申请日：2008-02-27
申请人： Shaw Hung Ku , Ten Hao Yeh , Shih Chin Lee , Shang Wei Lin , Chia Wei Wu , Tzung Ting Han , Ming Shang Chen , Wenpin Lu
发明人： Shaw Hung Ku , Ten Hao Yeh , Shih Chin Lee , Shang Wei Lin , Chia Wei Wu , Tzung Ting Han , Ming Shang Chen , Wenpin Lu
IPC分类号： G11C16/00
CPC分类号： H01L27/11568 , H01L2924/0002 , H01L2924/00
摘要： A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions.
摘要翻译：存储器阵列包括具有大致平行对准的多个沟槽的半导体本体。沟槽包含诸如掺杂非晶硅的半导体材料，并且用作存储器阵列的源极/漏极线。绝缘衬垫位于沟槽内的半导体材料和半导体本体之间。多个字线以交叉点的阵列覆盖半导体本体中的多个沟槽和沟道区域。电荷捕获结构位于字线和交叉点处的通道区之间，提供闪存单元阵列。电荷捕获结构包括适于编程和擦除以存储数据的介电电荷俘获结构。制造这种器件的方法包括在通道区域上形成电荷俘获结构之前，利用绝缘衬垫图案化和形成源极/漏极线。

2. 发明授权

US07889556B2 Flash memory having insulating liners between source/drain lines and channels 有权
标题翻译：闪存在源极/漏极线和通道之间具有绝缘衬垫
公开(公告)号：US07889556B2
公开(公告)日：2011-02-15
申请号：US12690582
申请日：2010-01-20
申请人： Shaw Hung Ku , Ten Hao Yeh , Shih Chin Lee , Shang Wei Lin , Chia Wei Wu , Tzung Ting Han , Ming Shang Chen , Wenpin Lu
发明人： Shaw Hung Ku , Ten Hao Yeh , Shih Chin Lee , Shang Wei Lin , Chia Wei Wu , Tzung Ting Han , Ming Shang Chen , Wenpin Lu
IPC分类号： G11C16/00
CPC分类号： H01L27/11568 , H01L2924/0002 , H01L2924/00
摘要： A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions.
摘要翻译：存储器阵列包括具有大致平行对准的多个沟槽的半导体本体。沟槽包含诸如掺杂非晶硅的半导体材料，并且用作存储器阵列的源极/漏极线。绝缘衬垫位于沟槽内的半导体材料和半导体本体之间。多个字线以交叉点的阵列覆盖半导体本体中的多个沟槽和沟道区域。电荷捕获结构位于字线和交叉点处的通道区之间，提供闪存单元阵列。电荷捕获结构包括适于编程和擦除以存储数据的介电电荷俘获结构。制造这种器件的方法包括在通道区域上形成电荷俘获结构之前，利用绝缘衬垫图案化和形成源极/漏极线。

3. 发明申请

US20100120210A1 FLASH MEMORY HAVING INSULATING LINERS BETWEEN SOURCE/DRAIN LINES AND CHANNELS 有权
标题翻译：在源/排水管线和通道之间具有绝缘衬套的闪存
公开(公告)号：US20100120210A1
公开(公告)日：2010-05-13
申请号：US12690582
申请日：2010-01-20
申请人： SHAW-HUNG KU , Ten Hao Yeh , Shih Chin Lee , Shang Wei Lin , Chia Wei Wu , Tzung Ting Han , Ming Shang Chen , Wenpin Lu
发明人： SHAW-HUNG KU , Ten Hao Yeh , Shih Chin Lee , Shang Wei Lin , Chia Wei Wu , Tzung Ting Han , Ming Shang Chen , Wenpin Lu
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L2924/0002 , H01L2924/00
摘要： A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions.
摘要翻译：存储器阵列包括具有大致平行对准的多个沟槽的半导体本体。沟槽包含诸如掺杂非晶硅的半导体材料，并且用作存储器阵列的源极/漏极线。绝缘衬垫位于沟槽内的半导体材料和半导体本体之间。多个字线以交叉点的阵列覆盖半导体本体中的多个沟槽和沟道区域。电荷捕获结构位于字线和交叉点处的通道区之间，提供闪存单元阵列。电荷捕获结构包括适于编程和擦除以存储数据的介电电荷俘获结构。制造这种器件的方法包括在通道区域上形成电荷俘获结构之前，利用绝缘衬垫图案化和形成源极/漏极线。

4. 发明申请

US20090213656A1 FLASH MEMORY HAVING INSULATING LINERS BETWEEN SOURCE/DRAIN LINES AND CHANNELS 有权
标题翻译：在源/排水管线和通道之间具有绝缘衬套的闪存
公开(公告)号：US20090213656A1
公开(公告)日：2009-08-27
申请号：US12038612
申请日：2008-02-27
申请人： Shaw Hung Ku , Teng Hao Yeh , Shih-Chin Lee , Shang-Wei Lin , Chia-Wei Wu , Tzung Ting Han , Ming Shang Chen , Wenpin Lu
发明人： Shaw Hung Ku , Teng Hao Yeh , Shih-Chin Lee , Shang-Wei Lin , Chia-Wei Wu , Tzung Ting Han , Ming Shang Chen , Wenpin Lu
IPC分类号： G11C11/34 , H01L21/8247
CPC分类号： H01L27/11568 , H01L2924/0002 , H01L2924/00
摘要： A memory array comprises a semiconductor body having a plurality of trenches aligned generally in parallel. The trenches contain semiconductor material, such as doped amorphous silicon, and act as source/drain lines for the memory array. Insulating liners lie between the semiconductor material within the trenches and the semiconductor body. A plurality of word lines overlie the plurality of trenches and channel regions in the semiconductor body in an array of cross points. Charge trapping structures lie between the word lines and the channel regions at the cross points, providing an array of flash memory cells. The charge trapping structures comprise dielectric charge trapping structures adapted to be programmed and erased to store data. A method for manufacturing such devices includes patterning and forming the sources/drain lines with insulating liners prior to formation of the charge trapping structure over the channel regions.
摘要翻译：存储器阵列包括具有大致平行对准的多个沟槽的半导体本体。沟槽包含诸如掺杂非晶硅的半导体材料，并且用作存储器阵列的源极/漏极线。绝缘衬垫位于沟槽内的半导体材料和半导体本体之间。多个字线以交叉点的阵列覆盖半导体本体中的多个沟槽和沟道区域。电荷捕获结构位于字线和交叉点处的通道区之间，提供闪存单元阵列。电荷捕获结构包括适于编程和擦除以存储数据的介电电荷俘获结构。制造这种器件的方法包括在通道区域上形成电荷俘获结构之前，利用绝缘衬垫图案化和形成源极/漏极线。

5. 发明授权

US07888272B2 Methods for manufacturing memory and logic devices using the same process without the need for additional masks 有权
标题翻译：使用相同过程制造存储器和逻辑器件而不需要额外掩模的方法
公开(公告)号：US07888272B2
公开(公告)日：2011-02-15
申请号：US11609747
申请日：2006-12-12
申请人： Kuan Fu Chen , Yin Jen Chen , Tzung Ting Han , Ming-Shang Chen , Shih Chin Lee
发明人： Kuan Fu Chen , Yin Jen Chen , Tzung Ting Han , Ming-Shang Chen , Shih Chin Lee
IPC分类号： H01L21/318
CPC分类号： H01L21/3144 , H01L21/02238 , H01L21/02255 , H01L21/28238 , H01L21/31662 , H01L29/42332 , H01L29/518 , H01L29/66825 , H01L29/78 , H01L29/7883 , H01L29/7885
摘要： A semiconductor fabrication process allows the fabrication of both logic and memory devices using a conventional CMOS process with a few additional steps. The additional steps, however, do not require additional masks. Accordingly, the process can be reduce the complexity, time, and cost for fabricating logic and memory devices on the same substrate, especially for embedded applications.
摘要翻译：半导体制造工艺允许使用常规CMOS工艺制造逻辑和存储器件，并且附加几个步骤。然而，额外的步骤不需要额外的掩模。因此，该过程可以降低在同一衬底上制造逻辑和存储器件的复杂性，时间和成本，特别是对于嵌入式应用。

6. 发明申请

US20080138998A1 METHODS FOR MANUFACTURING MEMORY AND LOGIC DEVICES USING THE SAME PROCESS WITHOUT THE NEED FOR ADDITIONAL MASKS 有权
标题翻译：使用相同工艺制造存储器和逻辑器件的方法，而不需要额外的掩码
公开(公告)号：US20080138998A1
公开(公告)日：2008-06-12
申请号：US11609747
申请日：2006-12-12
申请人： Kuan Fu Chen , Yin Jen Chen , Tzung Ting Han , Ming-Shang Chen , Shih Chin Lee
发明人： Kuan Fu Chen , Yin Jen Chen , Tzung Ting Han , Ming-Shang Chen , Shih Chin Lee
IPC分类号： H01L21/31
CPC分类号： H01L21/3144 , H01L21/02238 , H01L21/02255 , H01L21/28238 , H01L21/31662 , H01L29/42332 , H01L29/518 , H01L29/66825 , H01L29/78 , H01L29/7883 , H01L29/7885
摘要： A semiconductor fabrication process allows the fabrication of both logic and memory devices using a conventional CMOS process with a few additional steps. The additional steps, however, do not require additional masks. Accordingly, the process can be reduce the complexity, time, and cost for fabricating logic and memory devices on the same substrate, especially for embedded applications.
摘要翻译：半导体制造工艺允许使用常规CMOS工艺制造逻辑和存储器件，并且附加几个步骤。然而，额外的步骤不需要额外的掩模。因此，该过程可以降低在同一衬底上制造逻辑和存储器件的复杂性，时间和成本，特别是对于嵌入式应用。

7. 发明申请

US20080026561A1 METHODS OF TRENCH AND CONTACT FORMATION IN MEMORY CELLS 有权
标题翻译：记忆细胞中TRENCH和接触形成的方法
公开(公告)号：US20080026561A1
公开(公告)日：2008-01-31
申请号：US11459990
申请日：2006-07-26
申请人： Miao Chih Hsu , Tzung Ting Han , Ming Shang Chen
发明人： Miao Chih Hsu , Tzung Ting Han , Ming Shang Chen
IPC分类号： H01L21/4763
CPC分类号： H01L21/76838 , H01L27/105 , H01L27/11521 , H01L27/11568
摘要： Methods of contact formation and memory arrays formed using such methods, which methods include providing a memory array having a plurality of bit lines disposed below a surface of a semiconductor substrate and a plurality of word lines disposed above the surface of the substrate and transverse to the bit lines; forming a hard mask material layer over the plurality of word lines, wherein an area above at least one of the bit lines and between two consecutive word lines is exposed below an opening in the hard mask material layer; forming an insulating material layer above the hard mask material layer; forming a contiguous trench and via pattern in the insulating material layer above the area such that a portion of the at least one bit line is exposed below the pattern; and forming an interconnection comprising a conductive material disposed in the contiguous trench and via pattern wherein the interconnection is in conductive contact with the exposed portion of the at least one bit line.
摘要翻译：使用这种方法形成的接触形成方法和存储器阵列，该方法包括提供存储阵列，该存储阵列具有设置在半导体衬底的表面下方的多个位线，以及设置在衬底的表面上方且横向于衬底的多个字线位线在所述多个字线上形成硬掩模材料层，其中在所述硬掩模材料层中的开口下方暴露位于所述位线中的至少一个之上并且在两个连续字线之间的区域; 在硬掩模材料层上形成绝缘材料层; 在所述区域上方的绝缘材料层中形成连续的沟槽和通孔图案，使得所述至少一个位线的一部分暴露在所述图案下方; 以及形成互连，其包括设置在所述连续沟槽中的导电材料和通孔图案，其中所述互连与所述至少一个位线的所述暴露部分导电接触。

8. 发明授权

US08183106B2 Apparatus and associated method for making a floating gate memory device with buried diffusion dielectric structures and increased gate coupling ratio 有权
标题翻译：用于制造具有掩埋扩散电介质结构和增加的栅极耦合比的浮动栅极存储器件的装置和相关方法
公开(公告)号：US08183106B2
公开(公告)日：2012-05-22
申请号：US11460216
申请日：2006-07-26
申请人： Kuan Fu Chen , Yin Jen Chen , Meng Hsuan Weng , Tzung Ting Han , Ming Shang Chen , Chun Pei Wu
发明人： Kuan Fu Chen , Yin Jen Chen , Meng Hsuan Weng , Tzung Ting Han , Ming Shang Chen , Chun Pei Wu
IPC分类号： H01L21/3205 , H01L21/336 , H01L21/8238
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324
摘要： A method for fabricating a floating gate memory device comprises using self-aligned process for formation of a fourth poly layer over a partial gate structure that does not require an additional photolithographic step. Accordingly, enhanced device reliability can be achieved because a higher GCR can be maintained with lower gate bias levels. In addition, process complexity can be reduced, which can increase throughput and reduce device failures.
摘要翻译：一种用于制造浮动栅极存储器件的方法包括使用自对准工艺在不需要附加光刻步骤的部分栅极结构上形成第四多晶硅层。因此，可以实现增强的器件可靠性，因为可以以较低的栅极偏置电平保持更高的GCR。此外，可以减少流程复杂性，从而增加吞吐量并减少设备故障。

9. 发明授权

US07435648B2 Methods of trench and contact formation in memory cells 有权
标题翻译：记忆细胞中沟槽和接触形成的方法
公开(公告)号：US07435648B2
公开(公告)日：2008-10-14
申请号：US11459990
申请日：2006-07-26
申请人： Miao Chih Hsu , Tzung Ting Han , Ming Shang Chen
发明人： Miao Chih Hsu , Tzung Ting Han , Ming Shang Chen
IPC分类号： H01L21/336
CPC分类号： H01L21/76838 , H01L27/105 , H01L27/11521 , H01L27/11568
摘要： Methods of contact formation and memory arrays formed using such methods, which methods include providing a memory array having a plurality of bit lines disposed below a surface of a semiconductor substrate and a plurality of word lines disposed above the surface of the substrate and transverse to the bit lines; forming a hard mask material layer over the plurality of word lines, wherein an area above at least one of the bit lines and between two consecutive word lines is exposed below an opening in the hard mask material layer; forming an insulating material layer above the hard mask material layer; forming a contiguous trench and via pattern in the insulating material layer above the area such that a portion of the at least one bit line is exposed below the pattern; and forming an interconnection comprising a conductive material disposed in the contiguous trench and via pattern wherein the interconnection is in conductive contact with the exposed portion of the at least one bit line.
摘要翻译：使用这种方法形成的接触形成方法和存储器阵列，该方法包括提供存储阵列，该存储阵列具有设置在半导体衬底的表面下方的多个位线，以及设置在衬底的表面上方且横向于衬底的多个字线位线在所述多个字线上形成硬掩模材料层，其中在所述硬掩模材料层中的开口下方暴露位于所述位线中的至少一个之上并且在两个连续字线之间的区域; 在硬掩模材料层上形成绝缘材料层; 在所述区域上方的绝缘材料层中形成连续的沟槽和通孔图案，使得所述至少一个位线的一部分暴露在所述图案下方; 以及形成互连，其包括设置在所述连续沟槽中的导电材料和通孔图案，其中所述互连与所述至少一个位线的所述暴露部分导电接触。

10. 发明授权

US07486534B2 Diode-less array for one-time programmable memory 有权
标题翻译：一次可编程存储器的无二极管阵列
公开(公告)号：US07486534B2
公开(公告)日：2009-02-03
申请号：US11297529
申请日：2005-12-08
申请人： Kuan Fu Chen , Yin Jen Chen , Tzung Ting Han , Ming Shang Chen
发明人： Kuan Fu Chen , Yin Jen Chen , Tzung Ting Han , Ming Shang Chen
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , H01L21/8221 , H01L27/0688 , H01L27/101
摘要： A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor.
摘要翻译：一次可编程存储器阵列包括在第一行方向上延伸并且设置在第一高度的第一行导体，在第二行方向上延伸并设置在第二高度的第二行导体和沿列方向延伸的列导体并且设置成与第一行导体相邻并且与第二行导体相邻。阵列还包括覆盖列导体的至少一部分的电介质层，耦合在列导体上的电介质层和第二行导体之间的熔丝链。

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