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1. 发明申请

US20130058436A1 APPARATUS AND METHOD FOR PROCESSING A SIGNAL 审中-公开
标题翻译：用于处理信号的装置和方法
公开(公告)号：US20130058436A1
公开(公告)日：2013-03-07
申请号：US13564807
申请日：2012-08-02
申请人： SANG-WOO KIM , Yoon-Kyung Choi
发明人： SANG-WOO KIM , Yoon-Kyung Choi
IPC分类号： H04L27/00
CPC分类号： G06T1/60 , G09G3/3648 , G09G2320/103 , G09G2340/16 , G09G2360/16
摘要： A signal processing apparatus stores previously determined function values using parameters through a processing unit, and outputs the stored function data using subsequently input data as an address.
摘要翻译：信号处理装置通过处理单元使用参数存储预先确定的功能值，并且使用随后输入的数据作为地址输出所存储的功能数据。

2. 发明申请

US20070216563A1 Bit-adjacency capacitor-switched DAC, method, driver and display device 有权
标题翻译：位邻接电容切换DAC，方法，驱动和显示设备
公开(公告)号：US20070216563A1
公开(公告)日：2007-09-20
申请号：US11644991
申请日：2006-12-26
申请人： Zhong Wu , Yoon-Kyung Choi
发明人： Zhong Wu , Yoon-Kyung Choi
IPC分类号： H03M1/12
CPC分类号： H03M1/667
摘要： A cyclic digital to analog converter (CDAC) includes: first and second capacitors C1 and C2; an arrangement of switches selectively controllable to connect C1 and C2 in one of at least two charging-and-sharing configurations, the first configuration having the first capacitor C1 as a charging capacitor CCH and the second capacitor C2 as a sharing capacitor CSH, namely CCH=C1 and CSH=C2, and the second configuration having CCH=C2 and CSH=C1; and a controller to toggle the arrangement of switches between the first and second configurations based upon adjacent bits of a given input word.
摘要翻译：循环数模转换器（CDAC）包括：第一和第二电容器C 1和C 2; 选择性地控制开关以将至少两个充电和共享配置中的一个连接到C 1和C 2的开关的布置，所述第一配置具有作为充电电容器CCH的第一电容器C 1和作为共用电容器的第二电容器C 2 CSH，即CCH = C 1和CSH = C 2，第二配置具有CCH = C 2和CSH = C 1; 以及控制器，用于基于给定输入字的相邻位来切换第一和第二配置之间的开关的布置。

3. 发明申请

US20100156867A1 DIGITAL-TO-ANALOG CONVERTER, SOURCE DRIVING CIRCUIT AND DISPLAY DEVICE HAVING THE SAME 有权
标题翻译：数字到模拟转换器，源驱动电路和具有该数字转换器的显示设备
公开(公告)号：US20100156867A1
公开(公告)日：2010-06-24
申请号：US12639117
申请日：2009-12-16
申请人： Hyoung-Rae Kim , Yong-Joon Jeon , Gyu-Hyeong Cho , Sung-Woo Lee , Hyung-Min Lee , Yoon-Kyung Choi
发明人： Hyoung-Rae Kim , Yong-Joon Jeon , Gyu-Hyeong Cho , Sung-Woo Lee , Hyung-Min Lee , Yoon-Kyung Choi
IPC分类号： G09G5/00 , H03M1/66
CPC分类号： H03M1/0682 , G09G3/3648 , G09G3/3688 , G09G2310/027 , G09G2310/0272 , H03M1/68 , H03M1/745 , H03M1/765 , H03M1/802
摘要： A digital-to-analog converter includes a voltage-to-current converter, a current-mode digital-to-analog converter and an operational amplifier. The voltage-to-current converter generates a first current signal, and the current-mode digital-to-analog converter generates a second current signal. The operational amplifier modulates a drain current in response to the second current signal and generates an output signal having an offset.
摘要翻译：数模转换器包括电压 - 电流转换器，电流模式数模转换器和运算放大器。电压 - 电流转换器产生第一电流信号，并且电流模式数模转换器产生第二电流信号。运算放大器响应于第二电流信号调制漏极电流并产生具有偏移的输出信号。

4. 发明授权

US08581824B2 Hybrid digital to analog converter, source driver, and liquid crystal display device 有权
标题翻译：混合数模转换器，源驱动器和液晶显示装置
公开(公告)号：US08581824B2
公开(公告)日：2013-11-12
申请号：US12706031
申请日：2010-02-16
申请人： Jong-Hak Baek , Yoon-Kyung Choi , Oh-Kyong Kwon
发明人： Jong-Hak Baek , Yoon-Kyung Choi , Oh-Kyong Kwon
IPC分类号： G09G5/10
CPC分类号： H03M1/687 , G09G3/3685 , G09G3/3696 , G09G2300/0426 , G09G2310/027 , G09G2330/028 , H03M1/745 , H03M1/765
摘要： A hybrid digital to analog converter (DAC) includes a first digital to analog converting unit (DACU) and a second DAC unit. The first DAC unit provides an analog voltage corresponding to Q-bit upper data of P-bit gray data, in response to a plurality of gamma voltages, where P is a natural number equal to or greater than 10 and Q is a natural number less than 10. The second DAC unit provides an analog current having a magnitude according to each bit level of R-bit lower data of the P-bit gray data, based on a rated current generated from a reference voltage, where R is a natural number corresponding to P-Q.
摘要翻译：混合数模转换器（DAC）包括第一数模转换单元（DACU）和第二DAC单元。响应于多个伽马电压，第一DAC单元提供对应于P位灰度数据的Q位上位数据的模拟电压，其中P是等于或大于10的自然数，Q是自然数较少 10.根据从参考电压产生的额定电流，第二DAC单元提供具有根据P位灰度数据的R位下位数据的每个位电平的幅度的模拟电流，其中R是自然数对应于PQ。

5. 发明授权

US07652538B2 Circuits and methods for improving slew rate of differential amplifiers 有权
标题翻译：用于提高差分放大器的转换速率的电路和方法
公开(公告)号：US07652538B2
公开(公告)日：2010-01-26
申请号：US11228998
申请日：2005-09-16
申请人： Yoon-Kyung Choi
发明人： Yoon-Kyung Choi
IPC分类号： H03F1/14
CPC分类号： H03F1/34 , H03F1/08 , H03F3/3022 , H03F3/45192 , H03F3/45475 , H03F2203/45226 , H03F2203/45248 , H03F2203/45264 , H03F2203/45366 , H03F2203/45514 , H03F2203/45534
摘要： Circuits and methods are provided for providing high speed operational amplifiers and, in particular, operational amplifiers having frequency compensation circuits that provide improved slew rates with low power dissipation when configured with feedback. Frequency compensation schemes are provided to enable dynamic configuration of frequency compensation circuits implementing miller compensation whereby nodal connections of compensation capacitors are changed during driver setup and driving periods such that compensation capacitors are connected to source voltages to rapidly charge/discharge compensation capacitors using supply source currents during setup period, while providing frequency compensation during the setup and driving periods to maintain circuit stability and prevent oscillation of an output voltage due to the feedback.
摘要翻译：提供了用于提供高速运算放大器的电路和方法，特别是具有频率补偿电路的运算放大器，其在配置有反馈时提供具有低功耗的改进的压摆率。提供频率补偿方案以实现实现磨机补偿的频率补偿电路的动态配置，从而在驱动器建立和驱动周期期间改变补偿电容器的节点连接，使得补偿电容器连接到源电压以使用供电源电流快速充电/放电补偿电容器在建立期间，同时在建立和驱动期间提供频率补偿，以保持电路稳定性，并防止由于反馈引起的输出电压的振荡。

6. 发明申请

US20060091955A1 Circuits and methods for improving slew rate of differential amplifiers 有权
标题翻译：用于提高差分放大器的转换速率的电路和方法
公开(公告)号：US20060091955A1
公开(公告)日：2006-05-04
申请号：US11228998
申请日：2005-09-16
申请人： Yoon-Kyung Choi
发明人： Yoon-Kyung Choi
IPC分类号： H03F3/45
CPC分类号： H03F1/34 , H03F1/08 , H03F3/3022 , H03F3/45192 , H03F3/45475 , H03F2203/45226 , H03F2203/45248 , H03F2203/45264 , H03F2203/45366 , H03F2203/45514 , H03F2203/45534
摘要： Circuits and methods are provided for providing high speed operational amplifiers and, in particular, operational amplifiers having frequency compensation circuits that provide improved slew rates with low power dissipation when configured with feedback. Frequency compensation schemes are provided to enable dynamic configuration of frequency compensation circuits implementing miller compensation whereby nodal connections of compensation capacitors are changed during driver setup and driving periods such that compensation capacitors are connected to source voltages to rapidly charge/discharge compensation capacitors using supply source currents during setup period, while providing frequency compensation during the setup and driving periods to maintain circuit stability and prevent oscillation of an output voltage due to the feedback.
摘要翻译：提供了用于提供高速运算放大器的电路和方法，特别是具有频率补偿电路的运算放大器，其在配置有反馈时提供具有低功耗的改进的压摆率。提供频率补偿方案以实现实现磨机补偿的频率补偿电路的动态配置，从而在驱动器建立和驱动周期期间改变补偿电容器的节点连接，使得补偿电容器连接到源电压以使用供电源电流快速充电/放电补偿电容器在建立期间，同时在建立和驱动期间提供频率补偿，以保持电路稳定性，并防止由于反馈引起的输出电压的振荡。

7. 发明申请

US20100207967A1 HYBRID DIGITAL TO ANALOG CONVERTER, SOURCE DRIVER, AND LIQUID CRYSTAL DISPLAY DEVICE 有权
标题翻译：混合数字到模拟转换器，源驱动器和液晶显示器件
公开(公告)号：US20100207967A1
公开(公告)日：2010-08-19
申请号：US12706031
申请日：2010-02-16
申请人： Jong-Hak BAEK , Yoon-Kyung Choi , Oh-Kyong Kwon
发明人： Jong-Hak BAEK , Yoon-Kyung Choi , Oh-Kyong Kwon
IPC分类号： G09G5/10 , H03M1/66
CPC分类号： H03M1/687 , G09G3/3685 , G09G3/3696 , G09G2300/0426 , G09G2310/027 , G09G2330/028 , H03M1/745 , H03M1/765
摘要： A hybrid digital to analog converter (DAC) includes a first digital to analog converting unit (DACU) and a second DAC unit. The first DAC unit provides an analog voltage corresponding to Q-bit upper data of P-bit gray data, in response to a plurality of gamma voltages, where P is a natural number equal to or greater than 10 and Q is a natural number less than 10. The second DAC unit provides an analog current having a magnitude according to each bit level of R-bit lower data of the P-bit gray data, based on a rated current generated from a reference voltage, where R is a natural number corresponding to P-Q.
摘要翻译：混合数模转换器（DAC）包括第一数模转换单元（DACU）和第二DAC单元。响应于多个伽马电压，第一DAC单元提供对应于P位灰度数据的Q位上位数据的模拟电压，其中P是等于或大于10的自然数，Q是自然数较少 10.根据从参考电压产生的额定电流，第二DAC单元提供具有根据P位灰度数据的R位下位数据的每个位电平的幅度的模拟电流，其中R是自然数对应于PQ。

8. 发明申请

US20090322737A1 Gate Driver, Method of Driving the Gate Driver, and Display Panel Driving Apparatus Including the Gate Driver 有权
标题翻译：栅极驱动器，驱动栅极驱动器的方法以及包括栅极驱动器的显示面板驱动装置
公开(公告)号：US20090322737A1
公开(公告)日：2009-12-31
申请号：US12488803
申请日：2009-06-22
申请人： Hyoung-Rae Kim , Hyo-Sun Kim , Yoon-Kyung Choi , Jae-Youl Lee
发明人： Hyoung-Rae Kim , Hyo-Sun Kim , Yoon-Kyung Choi , Jae-Youl Lee
IPC分类号： G09G5/00
CPC分类号： G09G3/3677 , G09G2300/0426 , G09G2310/0248 , G09G2310/0291
摘要： A display panel driving apparatus and a method of driving the same are provided, and, in particular, a gate driver and a method of driving the gate driver. The gate driver includes a decoder that decodes gate line selection data and that generates a gate line selection signal. A gate driving circuit generates a gate driving signal in a pre-charging phase and a driving phase in response to the gate line selection signal and a pre-charging control signal that controls an off-state of non-selected gate lines. In a time period of the driving phase in which a gate line is not selected, a node that has been in a floating state is held to a target voltage level in response to a hold control signal. The hold control signal is generated based upon a timing relationship between the gate line selection signal and the pre-charging control signal.
摘要翻译：提供了显示面板驱动装置及其驱动方法，特别是栅极驱动器和驱动栅极驱动器的方法。栅极驱动器包括解码栅极线选择数据并产生栅极线选择信号的解码器。栅极驱动电路响应于栅极线选择信号而产生预充电阶段和驱动相位中的栅极驱动信号，以及控制非选择栅极线的截止状态的预充电控制信号。在没有选择栅极线的驱动阶段的时间段中，响应于保持控制信号将处于浮置状态的节点保持到目标电压电平。保持控制信号基于栅极线选择信号和预充电控制信号之间的定时关系而产生。

9. 发明申请

US20080291143A1 GRAY SCALE VOLTAGE DECODER AND DIGITAL-TO-ANALOG CONVERTER INCLUDING THE SAME 有权
标题翻译：灰度电压解码器和数字到模拟转换器，包括它们
公开(公告)号：US20080291143A1
公开(公告)日：2008-11-27
申请号：US12123787
申请日：2008-05-20
申请人： Yoon-Kyung Choi
发明人： Yoon-Kyung Choi
IPC分类号： G09G3/36 , H03M1/66
CPC分类号： G09G3/20 , G09G2310/027 , H03M1/68 , H03M1/76
摘要： A gray scale voltage decoder includes a first decoding unit and a second decoding unit, in which the first decoding unit includes row blocks. Each of the row blocks receives one of a number of gray scale voltages and determines whether to output the received gray scale voltage in response to first bits of digital image data provided through data input lines formed along a column direction. Row blocks outputting the received gray scale voltage according to the same values of the first bits are arranged adjacently. The first decoding unit selects part of the gray scale voltages to output the selected gray scale voltages. The second decoding unit selects one of the gray scale voltages selected by the first decoding unit in response to second bits of the digital image data and outputs the selected gray scale voltage.
摘要翻译：灰度级电压解码器包括第一解码单元和第二解码单元，其中第一解码单元包括行块。每个行块接收多个灰度级电压中的一个，并且响应于通过沿着列方向形成的数据输入线提供的数字图像数据的第一位来确定是否输出接收的灰度级电压。根据第一位的相同值输出接收到的灰度级电压的行块相邻布置。第一解码单元选择部分灰度电压以输出所选择的灰度级电压。第二解码单元响应于数字图像数据的第二位选择由第一解码单元选择的灰度级电压之一，并输出所选择的灰度级电压。

10. 发明授权

US07425913B2 Bit-adjacency capacitor-switched DAC, method, driver and display device 有权
标题翻译：位邻接电容切换DAC，方法，驱动和显示设备
公开(公告)号：US07425913B2
公开(公告)日：2008-09-16
申请号：US11644991
申请日：2006-12-26
申请人： Zhong Yuan Wu , Yoon-Kyung Choi
发明人： Zhong Yuan Wu , Yoon-Kyung Choi
IPC分类号： H03M1/66
CPC分类号： H03M1/667
摘要： A cyclic digital to analog converter (CDAC) includes: first and second capacitors C1 and C2; an arrangement of switches selectively controllable to connect C1 and C2 in one of at least two charging-and-sharing configurations, the first configuration having the first capacitor C1 as a charging capacitor CCH and the second capacitor C2 as a sharing capacitor CSH, namely CCH=C1 and CSH=C2, and the second configuration having CCH=C2 and CSH=C1; and a controller to toggle the arrangement of switches between the first and second configurations based upon adjacent bits of a given input word.
摘要翻译：循环数模转换器（CDAC）包括：第一和第二电容器C 1和C 2; 选择性地控制开关以将至少两个充电和共享配置中的一个连接到C 1和C 2的开关的布置，所述第一配置具有作为充电电容器CCH的第一电容器C 1和作为共用电容器的第二电容器C 2 CSH，即CCH = C 1和CSH = C 2，第二配置具有CCH = C 2和CSH = C 1; 以及控制器，用于基于给定输入字的相邻位来切换第一和第二配置之间的开关的布置。

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