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1. 发明授权

US08092766B2 Redox method for capture of total gaseous mercury by wet FGD 有权
标题翻译：通过湿FGD捕获总气态汞的氧化还原法
公开(公告)号：US08092766B2
公开(公告)日：2012-01-10
申请号：US12837131
申请日：2010-07-15
申请人： S. Behrooz Ghorishi , Luis G. Velazquez-Vargas , Hua Song , Lei Ji
发明人： S. Behrooz Ghorishi , Luis G. Velazquez-Vargas , Hua Song , Lei Ji
IPC分类号： B01D53/64
CPC分类号： B01D53/64 , B01D53/501 , B01D2251/106 , B01D2251/30 , B01D2251/60 , B01D2257/602
摘要： A method for capturing gaseous elemental mercury in a flue gas wherein a soluble mercury oxidizer is utilized to oxidize gaseous elemental mercury at a gas-liquid interface of a wet scrubber, and oxidized mercury product is removed prior to re-emission.
摘要翻译：一种用于捕获烟道气体中的气态元素汞的方法，其中使用可溶性汞氧化剂来氧化在湿式洗涤器的气 - 液界面处的气态元素汞，并且在再排放之前除去氧化的汞产物。

2. 发明申请

US20110014104A1 REDOX METHOD FOR CAPTURE OF TOTAL GASEOUS MERCURY BY WET FGD 有权
标题翻译：通过WET FGD捕获总气体汞的REDOX方法
公开(公告)号：US20110014104A1
公开(公告)日：2011-01-20
申请号：US12837131
申请日：2010-07-15
申请人： S. Behrooz Ghorishi , Luis G. Velazquez-Vargas , Hua Song , Lei Ji
发明人： S. Behrooz Ghorishi , Luis G. Velazquez-Vargas , Hua Song , Lei Ji
IPC分类号： B01D53/64 , B01D53/50
CPC分类号： B01D53/64 , B01D53/501 , B01D2251/106 , B01D2251/30 , B01D2251/60 , B01D2257/602
摘要： A method for capturing gaseous elemental mercury in a flue gas wherein a soluble mercury oxidizer is utilized to oxidize gaseous elemental mercury at a gas-liquid interface of a wet scrubber, and oxidized mercury product is removed prior to re-emission.
摘要翻译：一种用于捕获烟道气体中的气态元素汞的方法，其中使用可溶性汞氧化剂来氧化在湿式洗涤器的气 - 液界面处的气态元素汞，并且在再排放之前除去氧化的汞产物。

3. 发明授权

US07934174B2 Method and apparatus for using a database to quickly identify and correct a manufacturing problem area in a layout 有权
标题翻译：使用数据库快速识别和纠正布局中的制造问题区域的方法和装置
公开(公告)号：US07934174B2
公开(公告)日：2011-04-26
申请号：US12509854
申请日：2009-07-27
申请人： Zong Wu Tang , Daniel N. Zhang , Juhwan Kim , Hua Song , Weiping Fang , Lawrence S. Melvin, III
发明人： Zong Wu Tang , Daniel N. Zhang , Juhwan Kim , Hua Song , Weiping Fang , Lawrence S. Melvin, III
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/36 , G05B2219/45031 , G06F2217/12 , Y02P90/265
摘要： One embodiment provides a system for using a database to quickly identify a manufacturing problem area in a layout. During operation, the system receives a first check-figure which identifies a first area in a first layout, wherein the first area is associated with a first feature. Next, the system determines a first sample using the first check-figure, wherein the first sample represents the first layout's geometry within a first ambit of the first check-figure, wherein the first sample's geometry is expected to affect the shape of the first feature. The system then performs a model-based simulation using the first sample to obtain a first simulation-result which indicates whether the first feature is expected to have manufacturing problems. Next, the system stores the first simulation-result in a database which is used to quickly determine whether a second feature is expected to have manufacturing problems.
摘要翻译：一个实施例提供了一种使用数据库来快速识别布局中的制造问题区域的系统。在操作期间，系统接收第一检查图，其识别第一布局中的第一区域，其中第一区域与第一特征相关联。接下来，系统使用第一检查图确定第一样本，其中第一样本表示第一检查图的第一范围内的第一布局的几何形状，其中预期第一样本的几何形状影响第一特征的形状。然后，系统使用第一样本执行基于模型的模拟，以获得第一模拟结果，其指示第一特征是否预期具有制造问题。接下来，系统将第一模拟结果存储在用于快速确定第二特征是否期望具有制造问题的数据库中。

4. 发明申请

US20100115489A1 METHOD AND SYSTEM FOR PERFORMING LITHOGRAPHY VERIFICATION FOR A DOUBLE-PATTERNING PROCESS 有权
标题翻译：用于执行双图形化处理的方法和系统
公开(公告)号：US20100115489A1
公开(公告)日：2010-05-06
申请号：US12263278
申请日：2008-10-31
申请人： Hua Song , Lantian Wang , Gerard Terrence Luk-Pat , James P. Shiely
发明人： Hua Song , Lantian Wang , Gerard Terrence Luk-Pat , James P. Shiely
IPC分类号： G06F17/50
CPC分类号： G03F7/70466 , G03F7/705 , G03F7/70666 , G03F7/70675
摘要： One embodiment of the present invention provides a system that performs lithography verification for a double-patterning process on a mask layout without performing a full contour simulation of the mask layout. During operation, the system starts by receiving a first mask which is used in a first lithography step of the double-patterning process, and a second mask which is used in a second lithography step of the double-patterning process. Note that the first mask and the second mask are obtained by partitioning the mask layout. Next, the system receives an evaluation point on the mask layout. The system then determines whether the evaluation point is exclusively located on a polygon of the first mask, exclusively located on a polygon of the second mask, or located elsewhere. The system next computes a printing indicator at the evaluation point for the mask layout based on whether the evaluation point is exclusively located on a polygon of the first mask or exclusively located on a polygon of the second mask.
摘要翻译：本发明的一个实施例提供一种对掩模布局进行双重图案化处理的光刻验证，而不执行掩模布局的全轮廓模拟的系统。在操作期间，系统通过接收在双重图案化工艺的第一光刻步骤中使用的第一掩模和在双重图案化工艺的第二光刻步骤中使用的第二掩模开始。注意，通过分割掩模布局获得第一掩模和第二掩模。接下来，系统在掩码布局上接收评估点。然后，系统确定评估点是否仅排列在第一掩模的多边形上，专门位于第二掩模的多边形上，或位于其他位置。接下来，系统基于评估点是否仅位于第一掩模的多边形上或者仅位于第二掩模的多边形上，来计算掩模布局的评估点处的打印指示符。

5. 发明授权

US08527253B2 Modeling an arbitrarily polarized illumination source in an optical lithography system 有权
标题翻译：在光学光刻系统中建模任意偏振的照明光源
公开(公告)号：US08527253B2
公开(公告)日：2013-09-03
申请号：US11851021
申请日：2007-09-06
申请人： Qiaolin Zhang , Hua Song
发明人： Qiaolin Zhang , Hua Song
IPC分类号： G06F17/50
CPC分类号： G03F7/70566 , G03F1/36 , G03F7/70091 , G03F7/70441 , G03F7/705
摘要： One embodiment of the present invention provides a system that accurately models polarization states of an illumination source in an optical lithography system for manufacturing integrated circuits. During operation, the system starts by receiving a two-dimensional (2D) grid map for an illumination source pupil in the optical lithography system. The system then constructs a source-polarization model for the illumination source by defining a polarization state at each grid point in the grid map. Next, the system enhances a lithography model for the optical lithography system by incorporating the source-polarization model into the lithography/OPC model.
摘要翻译：本发明的一个实施例提供了一种在用于制造集成电路的光学光刻系统中精确地模拟照明源的偏振状态的系统。在操作期间，系统通过接收光刻系统中的照明源光瞳的二维（2D）网格图开始。然后，该系统通过在网格图中的每个网格点处定义偏振状态来为照明源构建源偏振模型。接下来，该系统通过将源偏振模型结合到光刻/ OPC模型中来增强光刻系统的光刻模型。

6. 发明申请

US20120284675A1 EUV LITHOGRAPHY FLARE CALCULATION AND COMPENSATION 有权
标题翻译： EUV LITHOGRAPHY FLARE计算和补偿
公开(公告)号：US20120284675A1
公开(公告)日：2012-11-08
申请号：US13098495
申请日：2011-05-02
申请人： James SHIELY , Hua Song
发明人： James SHIELY , Hua Song
IPC分类号： G06F17/50
CPC分类号： G03F7/705 , G03F1/24 , G03F1/70 , G03F1/84 , G03F7/70941
摘要： Extreme ultraviolet (EUV) lithography flare calculation and compensation is disclosed herein. A method of calculating flare for a mask for use in EUV lithography includes decomposing the flare power spectrum density (PSD) into a low frequency component and a high frequency component. Further, the method includes receiving a plurality of layouts in a flare map generator. Each of the plurality of layouts corresponds to a chip pattern location on the mask. Moreover, the method includes generating, using the flare map generator, a low frequency flare map for the mask from the low frequency component by using fast Fourier transform (FFT).
摘要翻译：本文公开了极紫外（EUV）光刻光斑计算和补偿。计算用于EUV光刻的掩模的光斑的方法包括将耀斑功率谱密度（PSD）分解为低频分量和高频分量。此外，该方法包括在耀斑图生成器中接收多个布局。多个布局中的每一个对应于掩模上的芯片图案位置。此外，该方法包括通过使用快速傅里叶变换（FFT）从低频分量生成使用闪光图生成器的用于掩模的低频闪光图。

7. 发明申请

US20120240086A1 MODELING EUV LITHOGRAPHY SHADOWING EFFECT 有权
标题翻译：建模EUV LITHOGRAPHY阴影效应
公开(公告)号：US20120240086A1
公开(公告)日：2012-09-20
申请号：US13363258
申请日：2012-01-31
申请人： Hua Song , James P. Shiely , Lena Zavyalova
发明人： Hua Song , James P. Shiely , Lena Zavyalova
IPC分类号： G06F17/50
CPC分类号： G03F7/705
摘要： Systems and techniques for modeling the EUV lithography shadowing effect are described. Some embodiments described herein provide a process model that includes an EUV lithography shadowing effect component. Polygon edges in a layout can be dissected into a set of segments. Next, the EUV lithography shadowing effect component can be used to bias each segment. The modified layout having the biased segments can then be used as input for other components in the process model.
摘要翻译：描述了用于建模EUV光刻阴影效果的系统和技术。本文描述的一些实施例提供了包括EUV光刻阴影效应组件的过程模型。布局中的多边形边可以分解成一组段。接下来，EUV光刻阴影效应组件可用于偏置每个片段。然后可以将具有偏置段的修改后的布局用作过程模型中的其它部件的输入。

8. 发明申请

US20090070083A1 MODELING AN ARBITRARILY POLARIZED ILLUMINATION SOURCE IN AN OPTICAL LITHOGRAPHY SYSTEM 有权
标题翻译：在光学平版印刷系统中建立棱镜极化照明源
公开(公告)号：US20090070083A1
公开(公告)日：2009-03-12
申请号：US11851021
申请日：2007-09-06
申请人： Qiaolin Zhang , Hua Song
发明人： Qiaolin Zhang , Hua Song
IPC分类号： G06G7/48
CPC分类号： G03F7/70566 , G03F1/36 , G03F7/70091 , G03F7/70441 , G03F7/705
摘要： One embodiment of the present invention provides a system that accurately models polarization states of an illumination source in an optical lithography system for manufacturing integrated circuits. During operation, the system starts by receiving a two-dimensional (2D) grid map for an illumination source pupil in the optical lithography system. The system then constructs a source-polarization model for the illumination source by defining a polarization state at each grid point in the grid map. Next, the system enhances a lithography model for the optical lithography system by incorporating the source-polarization model into the lithography/OPC model.
摘要翻译：本发明的一个实施例提供了一种在用于制造集成电路的光学光刻系统中精确地模拟照明源的偏振状态的系统。在操作期间，系统通过接收光刻系统中的照明源光瞳的二维（2D）网格图开始。然后，该系统通过在网格图中的每个网格点处定义偏振状态来为照明源构建源偏振模型。接下来，该系统通过将源偏振模型结合到光刻/ OPC模型中来增强光刻系统的光刻模型。

9. 发明申请

US20080109766A1 Locating critical dimension(s) of a layout feature in an IC design by modeling simulated intensities 有权
标题翻译：通过建模模拟强度来确定IC设计中布局特征的关键维度
公开(公告)号：US20080109766A1
公开(公告)日：2008-05-08
申请号：US11584356
申请日：2006-10-20
申请人： Hua Song , Lantiang Wang , ZongWu Tang
发明人： Hua Song , Lantiang Wang , ZongWu Tang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A computer is programmed to perform lithography simulation at a number of locations in a transverse direction relative to a length of a feature of an IC design, to obtain simulated intensities at the locations. The computer is further programmed to determine constants of a predetermined formula that models a trend of the simulated intensities as a function of distance (in the transverse direction), by curve-fitting. The computer is also programmed to compute a value (“CD predictor”) based on the just-determined constants, the formula and a known threshold intensity for a given position along the feature's length. The just-described process, of lithography-simulation, followed by curve-fitting, followed by CD predictor computation, is repeatedly performed to obtain a number of CD predictors at a corresponding number of positions along the feature's length. The CD predictors are used to identify a position of a critical dimension, for use in, for example, layout verification.
摘要翻译：计算机被编程为在相对于IC设计的特征的长度的横向方向上的多个位置处执行光刻模拟，以在位置处获得模拟的强度。计算机还被编程为通过曲线拟合来确定模拟强度的趋势作为距离（在横向方向上）的函数的预定公式的常数。计算机还被编程为基于刚刚确定的常数，公式和沿特征长度的给定位置的已知阈值强度来计算值（“CD预测器”）。重复执行刚才描述的光刻仿真过程，随后进行曲线拟合，随后进行CD预测器计算，以在沿着特征长度的相应位置的数量处获得多个CD预测器。 CD预测器用于识别临界尺寸的位置，用于例如布局验证。

10. 发明授权

US08889535B2 Semiconductor device and method for fabricating semiconductor buried layer 有权
标题翻译：半导体器件及半导体埋层制造方法
公开(公告)号：US08889535B2
公开(公告)日：2014-11-18
申请号：US13807305
申请日：2011-09-01
申请人： Hua Song , Hsiao-Chia Wu , Tse-Huang Lo
发明人： Hua Song , Hsiao-Chia Wu , Tse-Huang Lo
IPC分类号： H01L21/425 , H01L21/265 , H01L21/74 , H01L29/02 , H01L29/08
CPC分类号： H01L21/265 , H01L21/26513 , H01L21/74 , H01L29/02 , H01L29/0821
摘要： The present disclosure provides a semiconductor device and a method for fabricating a semiconductor buried layer. The method includes: preparing a substrate which includes a first oxide layer; forming a first buried layer region in the surface of the substrate by using a photoresist layer with a first buried layer region pattern as a mask, in which a doping state of the first buried layer region is different from a doping state of other region of the substrate; forming a second oxide layer on the surface of the substrate and the first buried layer region; and forming a second buried layer region in the surface of the substrate through self alignment process by using the second oxide layer as a mask. The method disclosed by the present disclosure reduces the complexity of the buried layer procedures and the cost thereof, as well as the probability of crystal defects.
摘要翻译：本公开提供了半导体器件和制造半导体掩埋层的方法。该方法包括：制备包括第一氧化物层的衬底; 通过使用具有第一掩埋层区域图案的光致抗蚀剂层作为掩模，在所述基板的表面中形成第一掩埋层区域，其中所述第一掩埋层区域的掺杂状态与所述第一掩埋层区域的其他区域的掺杂状态不同基质; 在所述基板的表面和所述第一掩埋层区域上形成第二氧化物层; 以及通过使用第二氧化物层作为掩模通过自对准工艺在衬底的表面中形成第二掩埋层区域。本发明公开的方法降低了掩埋层工艺的复杂性及其成本，以及晶体缺陷的可能性。

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