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1. 发明申请

US20110018050A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20110018050A1
公开(公告)日：2011-01-27
申请号：US12727830
申请日：2010-03-19
申请人： Tomoko FUJIWARA , Ryota Katsumata , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kidoh , Hiroyasu Tanaka , Yosuke Komori , Megumi Ishiduki , Junya Matsunami , Hideaki Aochi , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
发明人： Tomoko FUJIWARA , Ryota Katsumata , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kidoh , Hiroyasu Tanaka , Yosuke Komori , Megumi Ishiduki , Junya Matsunami , Hideaki Aochi , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
IPC分类号： H01L29/51 , H01L21/4763
CPC分类号： H01L27/11551 , H01L27/11524 , H01L27/11526 , H01L27/11529 , H01L27/11556
摘要： A nonvolatile semiconductor memory device, includes: a stacked structural unit including electrode films alternately stacked with inter-electrode insulating films; first and second semiconductor pillars piercing the stacked structural unit; a connection portion semiconductor layer electrically connect the first and second semiconductor pillars; a connection portion conductive layer provided to oppose the connection portion semiconductor layer; a memory layer and an inner insulating film provided between the first and semiconductor pillars and each of the electrode films, and between the connection portion conductive layer and the connection portion semiconductor layer; an outer insulating film provided between the memory layer and each of the electrode films; and a connection portion outer insulating film provided between the memory layer and the connection portion conductive layer. The connection portion outer insulating film has a film thickness thicker than a film thickness of the outer insulating film.
摘要翻译：一种非易失性半导体存储器件，包括：堆叠结构单元，其包括交替层叠有电极间绝缘膜的电极膜; 第一和第二半导体柱刺穿堆叠结构单元; 连接部分半导体层电连接第一和第二半导体柱; 连接部分导电层，设置成与连接部分半导体层相对; 设置在所述第一半导体柱和所述半导体柱之间以及所述电极膜之间并且位于所述连接部分导电层和所述连接部半导体层之间的存储层和内部绝缘膜; 设置在所述存储层和每个所述电极膜之间的外部绝缘膜; 以及设置在存储层和连接部分导电层之间的连接部分外绝缘膜。连接部外绝缘膜的膜厚比外绝缘膜的膜厚厚。

2. 发明授权

US08436414B2 Non-volatile semiconductor stacked memory device having two semiconductor pillars in a through hole and method for manufacturing same 有权
标题翻译：在通孔中具有两个半导体柱的非易失性半导体堆叠式存储器件及其制造方法
公开(公告)号：US08436414B2
公开(公告)日：2013-05-07
申请号：US12706127
申请日：2010-02-16
申请人： Hiroyasu Tanaka , Hideaki Aochi , Ryota Katsumata , Masaru Kidoh , Masaru Kito , Yoshiaki Fukuzumi , Yosuke Komori , Megumi Ishiduki , Tomoko Fujiwara , Junya Matsunami , Ryouhei Kirisawa
发明人： Hiroyasu Tanaka , Hideaki Aochi , Ryota Katsumata , Masaru Kidoh , Masaru Kito , Yoshiaki Fukuzumi , Yosuke Komori , Megumi Ishiduki , Tomoko Fujiwara , Junya Matsunami , Ryouhei Kirisawa
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L27/11578 , H01L27/11582 , H01L29/66833
摘要： A nonvolatile semiconductor memory device includes: a semiconductor substrate; a stacked body provided on the semiconductor substrate, the stacked body having electrode films and insulating films being alternately stacked; a first and second semiconductor pillars; and a first and second charge storage layers. The first and second semiconductor pillars are provided inside a through hole penetrating through the stacked body in a stacking direction of the stacked body. The through hole has a cross section of an oblate circle, when cutting in a direction perpendicular to the stacking direction. The first and second semiconductor pillars face each other in a major axis direction of the first oblate circle. The first and second semiconductor pillars extend in the stacking direction. The first and second charge storage layers are provided between the electrode film and the first and second semiconductor pillars, respectively.
摘要翻译：非易失性半导体存储器件包括：半导体衬底; 设置在所述半导体基板上的层叠体，具有交替堆叠的电极膜和绝缘膜的层叠体，第一和第二半导体柱; 以及第一和第二电荷存储层。第一半导体柱和第二半导体柱设置在层叠体的层叠方向上贯穿层叠体的贯通孔内。当沿垂直于堆叠方向的方向切割时，通孔具有扁圆形的横截面。第一和第二半导体柱在第一扁圆的长轴方向上彼此面对。第一和第二半导体柱沿层叠方向延伸。第一和第二电荷存储层分别设置在电极膜和第一和第二半导体柱之间。

3. 发明授权

US08189371B2 Nonvolatile semiconductor memory device and method for driving same 有权
标题翻译：非易失性半导体存储器件及其驱动方法
公开(公告)号：US08189371B2
公开(公告)日：2012-05-29
申请号：US12851002
申请日：2010-08-05
申请人： Ryota Katsumata , Hideaki Aochi , Hiroyasu Tanaka , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kidoh , Yosuke Komori , Megumi Ishiduki , Junya Matsunami , Tomoko Fujiwara , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
发明人： Ryota Katsumata , Hideaki Aochi , Hiroyasu Tanaka , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kidoh , Yosuke Komori , Megumi Ishiduki , Junya Matsunami , Tomoko Fujiwara , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
IPC分类号： G11C11/14
CPC分类号： G11C16/0483 , G11C16/06 , H01L27/11582 , H01L29/66833 , H01L29/7926
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array includes a stacked body, a through-hole, a semiconductor pillar, and a charge storage film. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. The through-hole is made in the stacked body to align in a stacking direction. The semiconductor pillar is buried in the through-hole. The charge storage film is provided between the electrode films and the semiconductor pillar. Memory cells are formed at each intersection between the electrode films and the semiconductor pillar. The control circuit writs a first value to at least some of the memory cells, performs an erasing operation of the first value from the memory cell written with the first value, reads data stored in the memory cell having undergone the erasing operation, and sets the memory cell to be unusable in a case that the first value is read from the memory cell.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括存储单元阵列和控制电路。存储单元阵列包括层叠体，通孔，半导体柱和电荷存储膜。层叠体包括交替层叠有多个电极膜的多个绝缘膜。通孔形成在堆叠体中以沿堆叠方向对齐。半导体柱埋在通孔中。电荷存储膜设置在电极膜和半导体柱之间。在电极膜和半导体柱之间的每个交叉处形成存储单元。控制电路将第一值写入至少部分存储单元，从写入第一值的存储单元执行第一值的擦除操作，读取存储在经过擦除操作的存储单元中的数据，并将在从存储器单元读取第一值的情况下，存储器单元不可用。

4. 发明授权

US08188530B2 Nonvolatile semiconductor memory device and method for manufacturing same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08188530B2
公开(公告)日：2012-05-29
申请号：US12728727
申请日：2010-03-22
申请人： Hiroyasu Tanaka , Ryota Katsumata , Hideaki Aochi , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kidoh , Yosuke Komori , Megumi Ishiduki , Junya Matsunami , Tomoko Fujiwara , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
发明人： Hiroyasu Tanaka , Ryota Katsumata , Hideaki Aochi , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kidoh , Yosuke Komori , Megumi Ishiduki , Junya Matsunami , Tomoko Fujiwara , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
IPC分类号： H01L21/8239 , H01L29/78 , H01L27/088
CPC分类号： H01L27/11578 , H01L27/11573 , H01L27/11575 , H01L27/11582
摘要： A semiconductor memory device provided with a cell array section and a peripheral circuit section, the device includes: a back gate electrode; a stacked body provided on the back gate electrode; a plurality of semiconductor pillars extending in a stacking direction; connection members, each of the connection members connecting one of the semiconductor pillars to another one of the semiconductor pillars; a back-gate electrode contact applying a potential to the back gate electrode; a gate electrode provided in the peripheral circuit section; and a gate electrode contact applying a potential to the gate electrode, the back gate electrode and the gate electrode respectively including: a lower semiconductor layer; a conductive layer provided on the lower semiconductor layer; and an upper semiconductor layer provided on the conductive layer, the connection members being provided in or on the upper semiconductor layer, the back-gate electrode contact and the gate electrode contact being in contact with the conductive layer.
摘要翻译：一种设置有单元阵列部分和外围电路部分的半导体存储器件，该器件包括：背栅电极; 设置在所述背栅电极上的层叠体; 沿层叠方向延伸的多个半导体柱; 连接构件，每个连接构件将半导体柱之一连接到另一个半导体柱; 向所述背栅电极施加电位的背栅极电极接触; 设置在所述外围电路部中的栅电极; 以及向所述栅电极，所述背栅电极和所述栅电极施加电位的栅电极接触部，分别包括：下半导体层; 设置在下半导体层上的导电层; 以及设置在所述导电层上的上半导体层，所述连接构件设置在所述上半导体层中或所述上半导体层上，所述背栅电极接触和所述栅电极接触与所述导电层接触。

5. 发明申请

US20110075481A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110075481A1
公开(公告)日：2011-03-31
申请号：US12694677
申请日：2010-01-27
申请人： Yoshiaki Fukuzumi , Ryota Katsumata , Masaru Kito , Masaru Kidoh , Hiroyasu Tanaka , Tomoko Fujiwara , Megumi Ishiduki , Yosuke Komori , Yoshimasa Mikajiri , Shigeto Oota , Ryouhei Kirisawa , Hideaki Aochi
发明人： Yoshiaki Fukuzumi , Ryota Katsumata , Masaru Kito , Masaru Kidoh , Hiroyasu Tanaka , Tomoko Fujiwara , Megumi Ishiduki , Yosuke Komori , Yoshimasa Mikajiri , Shigeto Oota , Ryouhei Kirisawa , Hideaki Aochi
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C11/34 , G11C5/02 , G11C16/26
摘要： A nonvolatile semiconductor memory device comprises: a bit line; a source line; a memory string having a plurality of electrically data-rewritable memory transistors connected in series; a first select transistor provided between one end of the memory string and the bit line; a second select transistor provided between the other end of the memory string and the source line; and a control circuit configured to control a read operation. A plurality of the memory strings connected to one bit line via a plurality of the first select transistors. During reading of data from a selected one of the memory strings, the control circuit renders conductive the first select transistor connected to an unselected one of the memory strings and renders non-conductive the second select transistor connected to unselected one of the memory strings.
摘要翻译：非易失性半导体存储器件包括：位线; 源线; 具有串联连接的多个电数据可重写存储晶体管的存储器串; 设置在存储器串的一端和位线之间的第一选择晶体管; 设置在存储器串的另一端与源极线之间的第二选择晶体管; 以及控制电路，被配置为控制读取操作。经由多个第一选择晶体管连接到一个位线的多个存储器串。在从选择的一个存储器串读取数据期间，控制电路使连接到未选择的一个存储器串的第一选择晶体管导通，并且使第二选择晶体管连接到未选择的一个存储器串。

6. 发明授权

US08294191B2 Multi-layer memory device including vertical and U-shape charge storage regions 失效
标题翻译：多层存储器件包括垂直和U形电荷存储区域
公开(公告)号：US08294191B2
公开(公告)日：2012-10-23
申请号：US12943349
申请日：2010-11-10
申请人： Ryota Katsumata , Hideaki Aochi , Masaru Kito , Masaru Kidoh , Ryouhei Kirisawa
发明人： Ryota Katsumata , Hideaki Aochi , Masaru Kito , Masaru Kidoh , Ryouhei Kirisawa
IPC分类号： H01L29/792
CPC分类号： H01L27/11582 , H01L27/1157 , H01L27/11573
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a first and a second stacked structure, a first and a second semiconductor pillar, a semiconductor connection portion, a first and a second connection portion conductive layer, a first and a second pillar portion memory layer, a first and a second connection portion memory layer. The first and second stacked structures include electrode films and inter-electrode insulating films alternately stacked in a first direction. The second stacked structure is adjacent to the first stacked structure. The first and second semiconductor pillars pierce the first and second stacked structures, respectively. The semiconductor connection portion connects the first and second semiconductor pillars. The first and second pillar portion memory layers are provided between the electrode films and the semiconductor pillar. The first and second connection portion memory layers are provided between the connection portion conductive layers and the semiconductor connection portion.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括第一和第二堆叠结构，第一和第二半导体柱，半导体连接部分，第一和第二连接部分导电层，第一和第二柱部存储器层，第一和第二连接部分存储层。第一和第二堆叠结构包括在第一方向上交替堆叠的电极膜和电极间绝缘膜。第二堆叠结构与第一堆叠结构相邻。第一和第二半导体柱分别刺穿第一和第二堆叠结构。半导体连接部分连接第一和第二半导体柱。第一和第二柱部存储层设置在电极膜和半导体柱之间。第一和第二连接部分存储层设置在连接部分导电层和半导体连接部分之间。

7. 发明授权

US08218358B2 Nonvolatile semiconductor memory device and method for driving same 有权
标题翻译：非易失性半导体存储器件及其驱动方法
公开(公告)号：US08218358B2
公开(公告)日：2012-07-10
申请号：US12851054
申请日：2010-08-05
申请人： Ryota Katsumata , Hideaki Aochi , Hiroyasu Tanaka , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kidoh , Yosuke Komori , Megumi Ishiduki , Junya Matsunami , Tomoko Fujiwara , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
发明人： Ryota Katsumata , Hideaki Aochi , Hiroyasu Tanaka , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kidoh , Yosuke Komori , Megumi Ishiduki , Junya Matsunami , Tomoko Fujiwara , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
IPC分类号： G11C11/14
CPC分类号： H01L27/11578 , G11C16/0466 , G11C16/06 , H01L27/11565 , H01L27/11582
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, and a drive circuit. The stacked body is provided on the substrate. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. A through-hole is made in the stacked body to align in a stacking direction. The semiconductor pillar is buried in an interior of the through-hole. The charge storage film is provided between the electrode film and the semiconductor pillar. The drive circuit supplies a potential to the electrode film. The diameter of the through-hole differs by a position in the stacking direction. The drive circuit supplies a potential to reduce a potential difference with the semiconductor pillar as a diameter of the through-hole piercing the electrode film decreases.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括衬底，堆叠体，半导体柱，电荷存储膜和驱动电路。层叠体设置在基板上。层叠体包括交替层叠有多个电极膜的多个绝缘膜。在堆叠体中形成通孔，以在堆叠方向上对齐。半导体柱被埋在通孔的内部。电荷存储膜设置在电极膜和半导体柱之间。驱动电路为电极膜提供电位。通孔的直径与层叠方向的位置不同。当穿透电极膜的通孔的直径减小时，驱动电路提供降低与半导体柱的电位差的电位。

8. 发明授权

US08178919B2 Nonvolatile semiconductor memory device and method for manufacturing same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08178919B2
公开(公告)日：2012-05-15
申请号：US12727830
申请日：2010-03-19
申请人： Tomoko Fujiwara , Ryota Katsumata , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kidoh , Hiroyasu Tanaka , Yosuke Komori , Megumi Ishiduki , Junya Matsunami , Hideaki Aochi , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
发明人： Tomoko Fujiwara , Ryota Katsumata , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kidoh , Hiroyasu Tanaka , Yosuke Komori , Megumi Ishiduki , Junya Matsunami , Hideaki Aochi , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
IPC分类号： H01L21/00
CPC分类号： H01L27/11551 , H01L27/11524 , H01L27/11526 , H01L27/11529 , H01L27/11556
摘要： A nonvolatile semiconductor memory device, includes: a stacked structural unit including electrode films alternately stacked with inter-electrode insulating films; first and second semiconductor pillars piercing the stacked structural unit; a connection portion semiconductor layer electrically connect the first and second semiconductor pillars; a connection portion conductive layer provided to oppose the connection portion semiconductor layer; a memory layer and an inner insulating film provided between the first and semiconductor pillars and each of the electrode films, and between the connection portion conductive layer and the connection portion semiconductor layer; an outer insulating film provided between the memory layer and each of the electrode films; and a connection portion outer insulating film provided between the memory layer and the connection portion conductive layer. The connection portion outer insulating film has a film thickness thicker than a film thickness of the outer insulating film.
摘要翻译：一种非易失性半导体存储器件，包括：堆叠结构单元，其包括交替层叠有电极间绝缘膜的电极膜; 第一和第二半导体柱刺穿堆叠结构单元; 连接部分半导体层电连接第一和第二半导体柱; 连接部分导电层，设置成与连接部分半导体层相对; 设置在所述第一半导体柱和所述半导体柱之间以及所述电极膜之间并且位于所述连接部分导电层和所述连接部半导体层之间的存储层和内部绝缘膜; 设置在所述存储层和每个所述电极膜之间的外部绝缘膜; 以及设置在存储层和连接部分导电层之间的连接部分外绝缘膜。连接部外绝缘膜的膜厚比外绝缘膜的膜厚厚。

9. 发明申请

US20120043599A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20120043599A1
公开(公告)日：2012-02-23
申请号：US12943349
申请日：2010-11-10
申请人： Ryota Katsumata , Hideaki Aochi , Masaru Kito , Masaru Kidoh , Ryouhei Kirisawa
发明人： Ryota Katsumata , Hideaki Aochi , Masaru Kito , Masaru Kidoh , Ryouhei Kirisawa
IPC分类号： H01L29/78 , H01L21/28
CPC分类号： H01L27/11582 , H01L27/1157 , H01L27/11573
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a first and a second stacked structure, a first and a second semiconductor pillar, a semiconductor connection portion, a first and a second connection portion conductive layer, a first and a second pillar portion memory layer, a first and a second connection portion memory layer. The first and second stacked structures include electrode films and inter-electrode insulating films alternately stacked in a first direction. The second stacked structure is adjacent to the first stacked structure. The first and second semiconductor pillars pierce the first and second stacked structures, respectively. The semiconductor connection portion connects the first and second semiconductor pillars. The first and second pillar portion memory layers are provided between the electrode films and the semiconductor pillar. The first and second connection portion memory layers are provided between the connection portion conductive layers and the semiconductor connection portion.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括第一和第二堆叠结构，第一和第二半导体柱，半导体连接部分，第一和第二连接部分导电层，第一和第二柱部存储器层，第一和第二连接部分存储层。第一和第二堆叠结构包括在第一方向上交替堆叠的电极膜和电极间绝缘膜。第二堆叠结构与第一堆叠结构相邻。第一和第二半导体柱分别刺穿第一和第二堆叠结构。半导体连接部分连接第一和第二半导体柱。第一和第二柱部存储层设置在电极膜和半导体柱之间。第一和第二连接部分存储层设置在连接部分导电层和半导体连接部分之间。

10. 发明申请

US20110031550A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20110031550A1
公开(公告)日：2011-02-10
申请号：US12727712
申请日：2010-03-19
申请人： Yosuke Komori , Hideaki Aochi , Ryota Katsumata , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kidoh , Hiroyasu Tanaka , Megumi Ishiduki , Tomoko Fujiwara , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
发明人： Yosuke Komori , Hideaki Aochi , Ryota Katsumata , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kidoh , Hiroyasu Tanaka , Megumi Ishiduki , Tomoko Fujiwara , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L29/792 , H01L27/11573 , H01L27/11578 , H01L27/11582 , H01L29/66833 , H01L29/7926
摘要： A nonvolatile semiconductor memory device includes: a stacked structural unit including a plurality of electrode films and a plurality of inter-electrode insulating films alternately stacked in a first direction; a first selection gate electrode stacked on the stacked structural unit in the first direction; a first semiconductor pillar piercing the stacked structural unit and the first selection gate electrode in the first direction; a first memory unit provided at an intersection of each of the electrode films and the first semiconductor pillar; and a first selection gate insulating film provided between the first semiconductor pillar and the first selection gate electrode, the first selection gate electrode including a first silicide layer provided on a face of the first selection gate electrode perpendicular to the first direction.
摘要翻译：非易失性半导体存储器件包括：堆叠结构单元，包括多个电极膜和沿第一方向交替堆叠的多个电极间绝缘膜; 第一选择栅电极，沿第一方向堆叠在层叠结构单元上; 第一半导体柱在第一方向上穿透层叠结构单元和第一选择栅电极; 设置在每个电极膜和第一半导体柱的交点处的第一存储单元; 以及设置在所述第一半导体柱和所述第一选择栅极之间的第一选择栅极绝缘膜，所述第一选择栅电极包括设置在所述第一选择栅电极的与所述第一方向垂直的面上的第一硅化物层。

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