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1. 发明申请

US20120119352A1 ELECTROLESS GOLD PLATING SOLUTION FOR FORMING FINE GOLD STRUCTURE, METHOD OF FORMING FINE GOLD STRUCTURE USING SAME, AND FINE GOLD STRUCTURE FORMED USING SAME 有权
标题翻译：用于形成细金结构的电镀金解决方案，使用其形成精细金结构的方法和使用其形成的精细金结构
公开(公告)号：US20120119352A1
公开(公告)日：2012-05-17
申请号：US13255392
申请日：2010-03-10
申请人： Ryota Iwai , Tomoaki Tokuhisa , Masaru Kato , Tokihiro Yokoshima , Masahiro Aoyagi , Yasuhiro Yamaji , Katsuya Kikuchi , Hiroshi Nakagawa
发明人： Ryota Iwai , Tomoaki Tokuhisa , Masaru Kato , Tokihiro Yokoshima , Masahiro Aoyagi , Yasuhiro Yamaji , Katsuya Kikuchi , Hiroshi Nakagawa
IPC分类号： H01L23/48 , C09D1/00 , H01L21/768
CPC分类号： H05K3/187 , C23C18/1605 , C23C18/1607 , C23C18/165 , C23C18/1834 , C23C18/1844 , C23C18/1851 , C23C18/44
摘要： An electroless gold plating solution with which one or more openings formed in a resist overlying a substrate can be filled in a short time, the openings having a width on the order of micrometer, in particular, 100 μm or smaller, in terms of the width of the exposed substrate area, and having a height of 3 μm or larger. The electroless gold plating solution contains a deposition accelerator for deposition in fine areas, and a microfine pattern of 100 μm or finer is formed therefrom.
摘要翻译：可以在短时间内填充形成在覆盖基板的抗蚀剂中形成的一个或多个开口的无电镀金液，所述开口宽度在数量级以上，特别是100μm以下的暴露的基板区域，并且具有3μm或更大的高度。无电镀金液含有用于在微细区域中沉积的沉积促进剂，由此形成100μm以上的微细图案。

2. 发明授权

US09345145B2 Electroless gold plating solution for forming fine gold structure, method of forming fine gold structure using same, and fine gold structure formed using same 有权
标题翻译：用于形成细金结构的无电镀金液，使用其形成精金结构的方法，以及使用其形成的精金结构
公开(公告)号：US09345145B2
公开(公告)日：2016-05-17
申请号：US13255392
申请日：2010-03-10
申请人： Ryota Iwai , Tomoaki Tokuhisa , Masaru Kato , Tokihiko Yokoshima , Masahiro Aoyagi , Yasuhiro Yamaji , Katsuya Kikuchi , Hiroshi Nakagawa
发明人： Ryota Iwai , Tomoaki Tokuhisa , Masaru Kato , Tokihiko Yokoshima , Masahiro Aoyagi , Yasuhiro Yamaji , Katsuya Kikuchi , Hiroshi Nakagawa
IPC分类号： H01L23/48 , H05K3/18 , C23C18/16 , C23C18/44 , C23C18/18
CPC分类号： H05K3/187 , C23C18/1605 , C23C18/1607 , C23C18/165 , C23C18/1834 , C23C18/1844 , C23C18/1851 , C23C18/44
摘要： An electroless gold plating solution with which one or more openings formed in a resist overlying a substrate can be filled in a short time, the openings having a width on the order of micrometer, in particular, 100 μm or smaller, in terms of the width of the exposed substrate area, and having a height of 3 μm or larger. The electroless gold plating solution contains a deposition accelerator for deposition in fine areas, and a microfine pattern of 100 μm or finer is formed therefrom.
摘要翻译：可以在短时间内填充形成在覆盖基板的抗蚀剂中形成的一个或多个开口的无电镀金液，所述开口宽度在数量级以上，特别是100μm以下的暴露的基板区域，并且具有3μm或更大的高度。无电镀金液含有用于在微细区域中沉积的沉积促进剂，由此形成100μm以上的微细图案。

3. 发明申请

US20100044870A1 Electrode connection structure of semiconductor chip, conductive member, and semiconductor device and method for manufacturing the same 失效
标题翻译：半导体芯片，导电部件和半导体器件的电极连接结构及其制造方法
公开(公告)号：US20100044870A1
公开(公告)日：2010-02-25
申请号：US12309207
申请日：2007-07-06
申请人： Yasuhiro Yamaji , Tokihiko Yokoshima , Masahiro Aoyagi , Hiroshi Nakagawa , Katsuya Kikuchi
发明人： Yasuhiro Yamaji , Tokihiko Yokoshima , Masahiro Aoyagi , Hiroshi Nakagawa , Katsuya Kikuchi
IPC分类号： H01L23/48 , H01L21/00
CPC分类号： H01L24/90 , H01L21/563 , H01L24/11 , H01L24/16 , H01L24/28 , H01L24/83 , H01L25/0657 , H01L2224/0401 , H01L2224/0603 , H01L2224/13011 , H01L2224/13012 , H01L2224/13015 , H01L2224/13017 , H01L2224/13018 , H01L2224/13099 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/1403 , H01L2224/16 , H01L2224/24145 , H01L2224/73203 , H01L2224/83192 , H01L2224/83194 , H01L2224/838 , H01L2224/9202 , H01L2225/06551 , H01L2225/06575 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01051 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/00012
摘要： An electrode connection structure of a semiconductor chip is provided to realize a highly reliable electrical connection with low stress without using a bump. A conductive member may be used for such an electrode connection structure. A semiconductor device is provided wherein semiconductor chips are arranged in layers without providing the semiconductor chips with a through via, and a method is provided for manufacturing such a semiconductor device. A part or all of the surface of a horizontal recess, which is formed in an adhesive layer arranged between a first electrode of a lower layer and a second electrode of an upper layer, is provided with a conductive member for connecting the first electrode and the second electrode.
摘要翻译：提供半导体芯片的电极连接结构，以在不使用凸块的情况下实现具有低应力的高度可靠的电连接。导电构件可用于这种电极连接结构。提供了半导体器件，其中半导体芯片被布置成层，而不向半导体芯片提供通孔，并且提供了制造这种半导体器件的方法。形成在布置在下层的第一电极和上层的第二电极之间的粘合剂层中的水平凹部的一部分或全部表面设置有用于将第一电极和第二电极连接的导电构件第二电极。

4. 发明授权

US08367468B2 Electrode connection structure of semiconductor chip, conductive member, and semiconductor device and method for manufacturing the same 失效
公开(公告)号：US08367468B2
公开(公告)日：2013-02-05
申请号：US13096496
申请日：2011-04-28
申请人： Yasuhiro Yamaji , Tokihiko Yokoshima , Masahiro Aoyagi , Hiroshi Nakagawa , Katsuya Kikuchi
发明人： Yasuhiro Yamaji , Tokihiko Yokoshima , Masahiro Aoyagi , Hiroshi Nakagawa , Katsuya Kikuchi
IPC分类号： H01L21/77 , H01L23/48
CPC分类号： H01L24/90 , H01L21/563 , H01L24/11 , H01L24/16 , H01L24/28 , H01L24/83 , H01L25/0657 , H01L2224/0401 , H01L2224/0603 , H01L2224/13011 , H01L2224/13012 , H01L2224/13015 , H01L2224/13017 , H01L2224/13018 , H01L2224/13099 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/1403 , H01L2224/16 , H01L2224/24145 , H01L2224/73203 , H01L2224/83192 , H01L2224/83194 , H01L2224/838 , H01L2224/9202 , H01L2225/06551 , H01L2225/06575 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01051 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/00012
摘要： An electrode connection structure of a semiconductor chip is provided to realize a highly reliable electrical connection with low stress without using a bump. A conductive member may be used for such an electrode connection structure. A semiconductor device is provided wherein semiconductor chips are arranged in layers without providing the semiconductor chips with a through via, and a method is provided for manufacturing such a semiconductor device. A part or all of the surface of a horizontal recess, which is formed in an adhesive layer arranged between a first electrode of a lower layer and a second electrode of an upper layer, is provided with a conductive member for connecting the first electrode and the second electrode.

5. 发明授权

US08399979B2 Electrode connection structure of semiconductor chip, conductive member, and semiconductor device and method for manufacturing the same 失效
标题翻译：半导体芯片，导电部件和半导体器件的电极连接结构及其制造方法
公开(公告)号：US08399979B2
公开(公告)日：2013-03-19
申请号：US12309207
申请日：2007-07-06
申请人： Yasuhiro Yamaji , Tokihiko Yokoshima , Masahiro Aoyagi , Hiroshi Nakagawa , Katsuya Kikuchi
发明人： Yasuhiro Yamaji , Tokihiko Yokoshima , Masahiro Aoyagi , Hiroshi Nakagawa , Katsuya Kikuchi
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L24/90 , H01L21/563 , H01L24/11 , H01L24/16 , H01L24/28 , H01L24/83 , H01L25/0657 , H01L2224/0401 , H01L2224/0603 , H01L2224/13011 , H01L2224/13012 , H01L2224/13015 , H01L2224/13017 , H01L2224/13018 , H01L2224/13099 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/1403 , H01L2224/16 , H01L2224/24145 , H01L2224/73203 , H01L2224/83192 , H01L2224/83194 , H01L2224/838 , H01L2224/9202 , H01L2225/06551 , H01L2225/06575 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01051 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/00012
摘要： An electrode connection structure of a semiconductor chip is provided to realize a highly reliable electrical connection with low stress without using a bump. A conductive member may be used for such an electrode connection structure. A semiconductor device is provided wherein semiconductor chips are arranged in layers without providing the semiconductor chips with a through via, and a method is provided for manufacturing such a semiconductor device. A part or all of the surface of a horizontal recess, which is formed in an adhesive layer arranged between a first electrode of a lower layer and a second electrode of an upper layer, is provided with a conductive member for connecting the first electrode and the second electrode.
摘要翻译：提供半导体芯片的电极连接结构，以在不使用凸块的情况下实现具有低应力的高度可靠的电连接。导电构件可用于这种电极连接结构。提供了半导体器件，其中半导体芯片被布置成层，而不向半导体芯片提供通孔，并且提供了制造这种半导体器件的方法。形成在布置在下层的第一电极和上层的第二电极之间的粘合剂层中的水平凹部的一部分或全部表面设置有用于将第一电极和第二电极连接的导电构件第二电极。

6. 发明申请

US20120108008A1 ELECTRODE CONNECTION STRUCTURE OF SEMICONDUCTOR CHIP, CONDUCTIVE MEMBER, AND SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 失效
标题翻译：半导体芯片，导电构件和半导体器件的电极连接结构及其制造方法
公开(公告)号：US20120108008A1
公开(公告)日：2012-05-03
申请号：US13096496
申请日：2011-04-28
申请人： Yasuhiro Yamaji , Tokihiko Yokoshima , Masahiro Aoyagi , Hiroshi Nakagawa , Katsuya Kikuchi
发明人： Yasuhiro Yamaji , Tokihiko Yokoshima , Masahiro Aoyagi , Hiroshi Nakagawa , Katsuya Kikuchi
IPC分类号： H01L21/50
CPC分类号： H01L24/90 , H01L21/563 , H01L24/11 , H01L24/16 , H01L24/28 , H01L24/83 , H01L25/0657 , H01L2224/0401 , H01L2224/0603 , H01L2224/13011 , H01L2224/13012 , H01L2224/13015 , H01L2224/13017 , H01L2224/13018 , H01L2224/13099 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/1403 , H01L2224/16 , H01L2224/24145 , H01L2224/73203 , H01L2224/83192 , H01L2224/83194 , H01L2224/838 , H01L2224/9202 , H01L2225/06551 , H01L2225/06575 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01051 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/00012
摘要： An electrode connection structure of a semiconductor chip is provided to realize a highly reliable electrical connection with low stress without using a bump. A conductive member may be used for such an electrode connection structure. A semiconductor device is provided wherein semiconductor chips are arranged in layers without providing the semiconductor chips with a through via, and a method is provided for manufacturing such a semiconductor device. A part or all of the surface of a horizontal recess, which is formed in an adhesive layer arranged between a first electrode of a lower layer and a second electrode of an upper layer, is provided with a conductive member for connecting the first electrode and the second electrode.
摘要翻译：提供半导体芯片的电极连接结构，以在不使用凸块的情况下实现具有低应力的高度可靠的电连接。导电构件可用于这种电极连接结构。提供了半导体器件，其中半导体芯片被布置成层，而不向半导体芯片提供通孔，并且提供了制造这种半导体器件的方法。形成在布置在下层的第一电极和上层的第二电极之间的粘合剂层中的水平凹部的一部分或全部表面设置有导电构件，用于将第一电极和第二电极。

7. 发明授权

US07767574B2 Method of forming micro metal bump 有权
标题翻译：形成微金属凸块的方法
公开(公告)号：US07767574B2
公开(公告)日：2010-08-03
申请号：US12225741
申请日：2007-03-30
申请人： Yoshihiro Gomi , Masahiro Aoyagi , Hiroshi Nakagawa , Katsuya Kikuchi , Yoshikuni Okada , Hirotaka Oosato
发明人： Yoshihiro Gomi , Masahiro Aoyagi , Hiroshi Nakagawa , Katsuya Kikuchi , Yoshikuni Okada , Hirotaka Oosato
IPC分类号： H01L21/44
CPC分类号： C23C14/541 , B23K1/0016 , B23K3/0607 , C23C14/042 , C23C14/228 , H01L21/4853 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/742 , H01L2224/0401 , H01L2224/0603 , H01L2224/1131 , H01L2224/1147 , H01L2224/13012 , H01L2224/13016 , H01L2224/13099 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/1403 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079
摘要： The present invention provides a method of forming a micro metal bump, which is capable of stably and industrially forming a micro metal bump, by a gas deposition process, at a prescribed position of a metal part formed on one side surface of a substrate. The method comprises the steps of: forming a straight hole (34) in a mask layer (30) covering one side surface of a substrate (10) on which a wiring pattern (12) is formed, wherein a prescribed position of the wiring pattern (12) is exposed in a bottom surface of the straight hole and the straight hole has an inner wall perpendicular to the one side surface of the substrate (10) and a sharp top opening portion; providing a metal plate, whose area is larger than that of the substrate (10), on the other side surface of the substrate (10) as a heat sink; placing the substrate (10) and the metal plate in a vacuum; forming a tapered metal bump (14) on the exposed surface of the wiring pattern (12), which is exposed in the bottom surface of the straight hole (34), by a gas deposition process, in which metal nanoparticles obtained by evaporating a metal are ejected from a nozzle together with a carrier gas so as to deposit on the prescribed position, with cooling the substrate (10) to a temperature lower than upper temperature limit of resin constituting the mask layer (30), by the metal plate as the heat sink, so as to retain a configuration of the straight hole (34); and removing the mask layer (30) from the one side surface of the substrate so as to complete the tapered metal bump (14) at the prescribed position of the wiring pattern (12).
摘要翻译：本发明提供一种通过气相沉积工艺在形成在基板的一个侧表面上的金属部件的规定位置上形成能够稳定地和工业上形成微小金属凸块的微型金属凸块的方法。该方法包括以下步骤：在覆盖其上形成有布线图案（12）的基板（10）的一个侧表面的掩模层（30）中形成直孔（34），其中布线图案（12）暴露在直孔的底面上，直孔具有与基板（10）的一个侧面垂直的内壁和尖锐的开口部; 在作为散热器的基板（10）的另一侧表面上设置面积比基板（10）的面积大的金属板; 将基板（10）和金属板放置在真空中; 在通过气相沉积工艺暴露在直孔（34）的底表面中的布线图案（12）的暴露表面上形成锥形金属凸块（14），其中通过蒸发金属与载气一起从喷嘴喷射，以便沉积在规定位置，通过金属板作为基板（10）冷却至低于构成掩模层（30）的树脂的上限温度的温度散热器，以保持直孔（34）的构造; 以及从所述基板的一个侧表面去除所述掩模层（30），以在所述布线图案（12）的规定位置处完成所述锥形金属凸块（14）。

8. 发明申请

US20080044950A1 Multi-layer fin wiring interposer fabrication process 有权
标题翻译：多层翅片接线插件制造工艺
公开(公告)号：US20080044950A1
公开(公告)日：2008-02-21
申请号：US11890502
申请日：2007-08-07
申请人： Masahiro Aoyagi , Hiroshi Nakagawa , Kazuhiko Tokoro , Katsuya Kikuchi , Yoshikuni Okada
发明人： Masahiro Aoyagi , Hiroshi Nakagawa , Kazuhiko Tokoro , Katsuya Kikuchi , Yoshikuni Okada
IPC分类号： H01L21/00
CPC分类号： H01L25/0657 , H01L21/486 , H01L21/768 , H01L21/76898 , H01L23/3114 , H01L23/49827 , H01L25/0655 , H01L2225/06513 , H01L2225/06541 , H01L2225/06572 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An interposer having multi-layer fine wiring structure which comprises an insulating layer made of photosensitive polyimide which is photosensitive organic material and a wiring layer portion made of metal, such as copper, silver, gold, aluminum, palladium, indium, titanium, tantalum, and niobium, functions as wiring in an integrated circuit chip, wherein junctions between the integrated circuit chip and the interposer are formed by micron to submicron size fine connection metal pads or bumps which are formed on both the integrated circuit chip and the interposer.
摘要翻译：具有多层精细布线结构的插入件，其包括由感光性有机材料构成的感光性聚酰亚胺构成的绝缘层和铜，银，金，铝，钯，铟，钛，钽等金属制的布线层部，和铌，用作集成电路芯片中的布线，其中集成电路芯片和插入器之间的接合部由形成在集成电路芯片和插入器两者上的微米至亚微米尺寸的精细连接金属焊盘或凸块形成。

9. 发明授权

US07323348B2 Superconducting integrated circuit and method for fabrication thereof 失效
标题翻译：超导集成电路及其制造方法
公开(公告)号：US07323348B2
公开(公告)日：2008-01-29
申请号：US11031995
申请日：2005-01-11
申请人： Masahiro Aoyagi , Hiroshi Nakagawa , Kazuhiko Tokoro , Katsuya Kikuchi , Hiroshi Itatani , Sigemasa Segawa
发明人： Masahiro Aoyagi , Hiroshi Nakagawa , Kazuhiko Tokoro , Katsuya Kikuchi , Hiroshi Itatani , Sigemasa Segawa
IPC分类号： H01L21/00
CPC分类号： H01L39/223 , H01L27/18 , H01L39/2493
摘要： A superconducting integrated circuit includes a substrate, a multilayer structure formed on the substrate and composed of a lower superconducting electrode, a tunnel barrier and an upper superconducting electrode sequentially joined together upward in the order mentioned, and an insulating layer perforated to form via holes to get electrical contacts with the lower and upper electrodes. The insulating layer is formed of a high-resolution, photosensitive, solvent-soluble, organic insulating material. The superconducting integrated circuit is produced by a method that includes the steps of depositing the multiplayer on the substrate, applying the insulating material to the front surface of the substrate inclusive of the multiplayer, forming the via holes in the insulating material by the lithographic technique at the prospective positions to get electrical contacts with the upper and lower electrodes, and laying wirings for connecting the upper and lower electrodes through the via holes.
摘要翻译：超导集成电路包括基板，形成在基板上并由下部超导电极，隧道势垒和上部超导电极按顺序连接在一起的多层结构，以及穿孔以形成通孔的绝缘层与下电极和上电极电接触。绝缘层由高分辨率，光敏，溶剂可溶的有机绝缘材料形成。超导集成电路是通过以下步骤制造的，所述方法包括以下步骤：在衬底上沉积多层板，将绝缘材料施加到包括多层板的衬底的前表面，通过光刻技术在绝缘材料中形成通孔与上下电极电接触的预期位置，以及布置用于通过通孔连接上电极和下电极的布线。

10. 发明申请

US20050191763A1 Superconducting integrated circuit and method for fabrication thereof 失效
公开(公告)号：US20050191763A1
公开(公告)日：2005-09-01
申请号：US11031995
申请日：2005-01-11
申请人： Masahiro Aoyagi , Hiroshi Nakagawa , Kazuhiko Tokoro , Katsuya Kikuchi , Hiroshi Itatani , Sigemasa Segawa
发明人： Masahiro Aoyagi , Hiroshi Nakagawa , Kazuhiko Tokoro , Katsuya Kikuchi , Hiroshi Itatani , Sigemasa Segawa
IPC分类号： H01L39/00 , H01L21/312 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522 , H01L27/18 , H01L39/22 , H01L39/24 , H01L21/00 , H01B12/00 , H01L23/48 , H01L29/00 , H01L45/00
CPC分类号： H01L39/223 , H01L27/18 , H01L39/2493
摘要： A superconducting integrated circuit includes a substrate, a multilayer structure formed on the substrate and composed of a lower superconducting electrode, a tunnel barrier and an upper superconducting electrode sequentially joined together upward in the order mentioned, and an insulating layer perforated to form via holes to get electrical contacts with the lower and upper electrodes. The insulating layer is formed of a high-resolution, photosensitive, solvent-soluble, organic insulating material. The superconducting integrated circuit is produced by a method that includes the steps of depositing the multiplayer on the substrate, applying the insulating material to the front surface of the substrate inclusive of the multiplayer, forming the via holes in the insulating material by the lithographic technique at the prospective positions to get electrical contacts with the upper and lower electrodes, and laying wirings for connecting the upper and lower electrodes through the via holes.

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