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1. 发明授权

US07323348B2 Superconducting integrated circuit and method for fabrication thereof 失效
标题翻译：超导集成电路及其制造方法
公开(公告)号：US07323348B2
公开(公告)日：2008-01-29
申请号：US11031995
申请日：2005-01-11
申请人： Masahiro Aoyagi , Hiroshi Nakagawa , Kazuhiko Tokoro , Katsuya Kikuchi , Hiroshi Itatani , Sigemasa Segawa
发明人： Masahiro Aoyagi , Hiroshi Nakagawa , Kazuhiko Tokoro , Katsuya Kikuchi , Hiroshi Itatani , Sigemasa Segawa
IPC分类号： H01L21/00
CPC分类号： H01L39/223 , H01L27/18 , H01L39/2493
摘要： A superconducting integrated circuit includes a substrate, a multilayer structure formed on the substrate and composed of a lower superconducting electrode, a tunnel barrier and an upper superconducting electrode sequentially joined together upward in the order mentioned, and an insulating layer perforated to form via holes to get electrical contacts with the lower and upper electrodes. The insulating layer is formed of a high-resolution, photosensitive, solvent-soluble, organic insulating material. The superconducting integrated circuit is produced by a method that includes the steps of depositing the multiplayer on the substrate, applying the insulating material to the front surface of the substrate inclusive of the multiplayer, forming the via holes in the insulating material by the lithographic technique at the prospective positions to get electrical contacts with the upper and lower electrodes, and laying wirings for connecting the upper and lower electrodes through the via holes.
摘要翻译：超导集成电路包括基板，形成在基板上并由下部超导电极，隧道势垒和上部超导电极按顺序连接在一起的多层结构，以及穿孔以形成通孔的绝缘层与下电极和上电极电接触。绝缘层由高分辨率，光敏，溶剂可溶的有机绝缘材料形成。超导集成电路是通过以下步骤制造的，所述方法包括以下步骤：在衬底上沉积多层板，将绝缘材料施加到包括多层板的衬底的前表面，通过光刻技术在绝缘材料中形成通孔与上下电极电接触的预期位置，以及布置用于通过通孔连接上电极和下电极的布线。

2. 发明申请

US20050191763A1 Superconducting integrated circuit and method for fabrication thereof 失效
公开(公告)号：US20050191763A1
公开(公告)日：2005-09-01
申请号：US11031995
申请日：2005-01-11
申请人： Masahiro Aoyagi , Hiroshi Nakagawa , Kazuhiko Tokoro , Katsuya Kikuchi , Hiroshi Itatani , Sigemasa Segawa
发明人： Masahiro Aoyagi , Hiroshi Nakagawa , Kazuhiko Tokoro , Katsuya Kikuchi , Hiroshi Itatani , Sigemasa Segawa
IPC分类号： H01L39/00 , H01L21/312 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522 , H01L27/18 , H01L39/22 , H01L39/24 , H01L21/00 , H01B12/00 , H01L23/48 , H01L29/00 , H01L45/00
CPC分类号： H01L39/223 , H01L27/18 , H01L39/2493
摘要： A superconducting integrated circuit includes a substrate, a multilayer structure formed on the substrate and composed of a lower superconducting electrode, a tunnel barrier and an upper superconducting electrode sequentially joined together upward in the order mentioned, and an insulating layer perforated to form via holes to get electrical contacts with the lower and upper electrodes. The insulating layer is formed of a high-resolution, photosensitive, solvent-soluble, organic insulating material. The superconducting integrated circuit is produced by a method that includes the steps of depositing the multiplayer on the substrate, applying the insulating material to the front surface of the substrate inclusive of the multiplayer, forming the via holes in the insulating material by the lithographic technique at the prospective positions to get electrical contacts with the upper and lower electrodes, and laying wirings for connecting the upper and lower electrodes through the via holes.

3. 发明授权

US06911665B2 Superconducting integrated circuit and method for fabrication thereof 失效
标题翻译：超导集成电路及其制造方法
公开(公告)号：US06911665B2
公开(公告)日：2005-06-28
申请号：US10631791
申请日：2003-08-01
申请人： Masahiro Aoyagi , Hiroshi Nakagawa , Kazuhiko Tokoro , Katsuya Kikuchi , Hiroshi Itatani , Sigemasa Segawa
发明人： Masahiro Aoyagi , Hiroshi Nakagawa , Kazuhiko Tokoro , Katsuya Kikuchi , Hiroshi Itatani , Sigemasa Segawa
IPC分类号： H01L39/00 , H01L21/312 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522 , H01L27/18 , H01L39/22 , H01L39/24
CPC分类号： H01L39/223 , H01L27/18 , H01L39/2493
摘要： A superconducting integrated circuit includes a substrate, a multilayer structure formed on the substrate and composed of a lower superconducting electrode, a tunnel barrier and an upper superconducting electrode sequentially joined together upward in the order mentioned, and an insulating layer perforated to form via holes to get electrical contacts with the lower and upper electrodes. The insulating layer is formed of a high-resolution, photosensitive, solvent-soluble, organic insulating material. The superconducting integrated circuit is produced by a method that includes the steps of depositing the multiplayer on the substrate, applying the insulating material to the front surface of the substrate inclusive of the multiplayer, forming the via holes in the insulating material by the lithographic technique at the prospective positions to get electrical contacts with the upper and lower electrodes, and laying wirings for connecting the upper and lower electrodes through the via holes.
摘要翻译：超导集成电路包括基板，形成在基板上并由下部超导电极，隧道势垒和上部超导电极按顺序连接在一起的多层结构，以及穿孔以形成通孔的绝缘层与下电极和上电极电接触。绝缘层由高分辨率，光敏，溶剂可溶的有机绝缘材料形成。超导集成电路是通过以下步骤制造的，所述方法包括以下步骤：将多层板沉积在基板上，将绝缘材料施加到包括多层板的基板的前表面，通过光刻技术在绝缘材料中形成通孔与上下电极电接触的预期位置，以及布置用于通过通孔连接上电极和下电极的布线。

4. 发明申请

US20070065956A1 Contact probe, measuring pad used for the contact probe, and method of manufacturing the contact probe 有权
公开(公告)号：US20070065956A1
公开(公告)日：2007-03-22
申请号：US11602240
申请日：2006-11-21
申请人： Masahiro Aoyagi , Hiroshi Nakagawa , Kazuhiko Tokoro , Katsuya Kikuchi , Yoshikuni Okada , Shigeo Kiyota
发明人： Masahiro Aoyagi , Hiroshi Nakagawa , Kazuhiko Tokoro , Katsuya Kikuchi , Yoshikuni Okada , Shigeo Kiyota
IPC分类号： H01L21/66
CPC分类号： G01R1/06772 , H05K1/0219 , H05K1/117 , Y10T29/49117
摘要： There is provided a contact probe that is smaller than 50 μm in a pitch between a signal electrode and a ground electrode and can correctly conduct a high-speed high-frequency measurement, a measuring pad used for the contact probe, and a method of manufacturing the contact probe. The contact probe includes: a tip member having a signal electrode 10a and a ground electrode 11a that are put into contact with an object to be measured; and a coaxial cable 1 having a core 1b electrically connected to the signal electrode 10a and an outer covering conductor la electrically connected to the ground electrode 11a, wherein the tip member is formed on a printed wiring board 2, and wherein the signal electrode 10a and the ground electrode 11a are constructed of fine coplanar strip lines formed on an insulating board 2a.

5. 发明申请

US20080044950A1 Multi-layer fin wiring interposer fabrication process 有权
标题翻译：多层翅片接线插件制造工艺
公开(公告)号：US20080044950A1
公开(公告)日：2008-02-21
申请号：US11890502
申请日：2007-08-07
申请人： Masahiro Aoyagi , Hiroshi Nakagawa , Kazuhiko Tokoro , Katsuya Kikuchi , Yoshikuni Okada
发明人： Masahiro Aoyagi , Hiroshi Nakagawa , Kazuhiko Tokoro , Katsuya Kikuchi , Yoshikuni Okada
IPC分类号： H01L21/00
CPC分类号： H01L25/0657 , H01L21/486 , H01L21/768 , H01L21/76898 , H01L23/3114 , H01L23/49827 , H01L25/0655 , H01L2225/06513 , H01L2225/06541 , H01L2225/06572 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An interposer having multi-layer fine wiring structure which comprises an insulating layer made of photosensitive polyimide which is photosensitive organic material and a wiring layer portion made of metal, such as copper, silver, gold, aluminum, palladium, indium, titanium, tantalum, and niobium, functions as wiring in an integrated circuit chip, wherein junctions between the integrated circuit chip and the interposer are formed by micron to submicron size fine connection metal pads or bumps which are formed on both the integrated circuit chip and the interposer.
摘要翻译：具有多层精细布线结构的插入件，其包括由感光性有机材料构成的感光性聚酰亚胺构成的绝缘层和铜，银，金，铝，钯，铟，钛，钽等金属制的布线层部，和铌，用作集成电路芯片中的布线，其中集成电路芯片和插入器之间的接合部由形成在集成电路芯片和插入器两者上的微米至亚微米尺寸的精细连接金属焊盘或凸块形成。

6. 发明授权

US07227352B2 Contact probe, measuring pad used for the contact probe, and method of manufacturing the contact probe 有权
标题翻译：接触式探针，用于接触式探针的测量垫以及接触式探头的制造方法
公开(公告)号：US07227352B2
公开(公告)日：2007-06-05
申请号：US11602240
申请日：2006-11-21
申请人： Masahiro Aoyagi , Hiroshi Nakagawa , Kazuhiko Tokoro , Katsuya Kikuchi , Yoshikuni Okada , Shigeo Kiyota
发明人： Masahiro Aoyagi , Hiroshi Nakagawa , Kazuhiko Tokoro , Katsuya Kikuchi , Yoshikuni Okada , Shigeo Kiyota
IPC分类号： G01R31/02 , H01R43/00
CPC分类号： G01R1/06772 , H05K1/0219 , H05K1/117 , Y10T29/49117
摘要： There is provided a contact probe that is smaller than 50 μm in a pitch between a signal electrode and a ground electrode and can correctly conduct a high-speed high-frequency measurement, a measuring pad used for the contact probe, and a method of manufacturing the contact probe. The contact probe includes: a tip member having a signal electrode 10a and a ground electrode 11a that are put into contact with an object to be measured; and a coaxial cable 1 having a core 1b electrically connected to the signal electrode 10a and an outer covering conductor la electrically connected to the ground electrode 11a, wherein the tip member is formed on a printed wiring board 2, and wherein the signal electrode 10a and the ground electrode 11a are constructed of fine coplanar strip lines formed on an insulating board 2a.
摘要翻译：提供了在信号电极和接地电极之间以间距小于50um的接触探针，并且可以正确地进行高速高频测量，用于接触探针的测量垫以及制造方法接触探头。接触探针包括：具有与被测量物体接触的信号电极10a和接地电极11a的尖端部件; 以及具有电连接到信号电极10a的芯1b和电连接到接地电极11a的外覆盖导体1a的同轴电缆1，其中尖端构件形成在印刷线路板2上，并且其中信号电极10a和接地电极11a由形成在绝缘板2a上的细共面带状线构成。

7. 发明授权

US07414422B2 System in-package test inspection apparatus and test inspection method 失效
标题翻译：系统包装试验检验装置及试验检验方法
公开(公告)号：US07414422B2
公开(公告)日：2008-08-19
申请号：US11108861
申请日：2005-04-19
申请人： Masahiro Aoyagi , Hiroshi Nakagawa , Kazuhiko Tokoro , Katsuya Kikuchi , Yoshikuni Okada , Hiroyuki Fujita , Kenichi Kobayashi
发明人： Masahiro Aoyagi , Hiroshi Nakagawa , Kazuhiko Tokoro , Katsuya Kikuchi , Yoshikuni Okada , Hiroyuki Fujita , Kenichi Kobayashi
IPC分类号： G01R31/26
CPC分类号： G01R31/2822 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48227 , H01L2924/00014 , H01L2924/15192 , H01L2924/15311 , H01L2224/05599 , H01L2924/00012
摘要： A system in-package test inspection apparatus for measuring and evaluating the high-speed/high frequency characteristic of a system in-package through an electrode pad in which I/O terminals are formed on one side of an LSI package containing metallic wiring internally and plural LSI chips are stacked in multiple layers on the other face while electric connection between the LSI chip and the LSI package and the electric connection between the LSI chips are implemented, the system in-package test inspection apparatus comprising: a printed wiring substrate to which the I/O terminals of the system in-package are connected to enable transmission of high speed and high frequency signals; LSI chip driving means for driving the LSI chip; a contact probe having a contact electrode and for transmitting a high frequency signal; evaluation signal generating means for supplying a high frequency evaluation signal to the contact probe; output signal detecting means for detecting an output signal of the system in-package through the printed wiring board; and analyzing means for analyzing a signal detected by the output signal detecting means, wherein by contacting the contact electrode of the contact probe with an electrode pad formed on the LSI chip, the evaluation signal is inputted to the LSI chip not through metallic wiring within the LSI package.
摘要翻译：一种用于测量和评估通过其内部形成有包含金属布线的LSI封装的一侧上的I / O端子的电极焊盘的系统的封装中的高速/高频特性的系统级封装测试检查装置，在LSI芯片和LSI封装之间的电连接和LSI芯片之间的电连接被实现的同时，多个LSI芯片被堆叠在多个层中，该系统的封装测试检查装置包括：印刷布线基板，连接系统内置的I / O端子，实现高速和高频信号的传输; 用于驱动LSI芯片的LSI芯片驱动装置; 具有接触电极并用于发送高频信号的接触探针; 评估信号发生装置，用于向接触探针提供高频评估信号; 输出信号检测装置，用于检测通过印刷电路板的封装中的系统的输出信号; 以及分析装置，用于分析由输出信号检测装置检测到的信号，其中通过使接触探针的接触电极与形成在LSI芯片上的电极焊盘接触，评估信号不通过金属布线输入到LSI芯片 LSI封装。

8. 发明申请

US20050264313A1 Contact probe, measuring pad used for the contact probe, and method of manufacturing the contact probe 有权
标题翻译：接触式探针，用于接触式探针的测量垫以及接触式探头的制造方法
公开(公告)号：US20050264313A1
公开(公告)日：2005-12-01
申请号：US11136572
申请日：2005-05-25
申请人： Masahiro Aoyagi , Hiroshi Nakagawa , Kazuhiko Tokoro , Katsuya Kikuchi , Yoshikuni Okada , Shigeo Kiyota
发明人： Masahiro Aoyagi , Hiroshi Nakagawa , Kazuhiko Tokoro , Katsuya Kikuchi , Yoshikuni Okada , Shigeo Kiyota
IPC分类号： G01R1/067 , G01R31/02 , H05K1/02 , H05K1/11
CPC分类号： G01R1/06772 , H05K1/0219 , H05K1/117 , Y10T29/49117
摘要： There is provided a contact probe that is smaller than 50 μm in a pitch between a signal electrode and a ground electrode and can correctly conduct a high-speed high-frequency measurement, a measuring pad used for the contact probe, and a method of manufacturing the contact probe. The contact probe includes: a tip member having a signal electrode 10a and a ground electrode 11a that are put into contact with an object to be measured; and a coaxial cable 1 having a core 1b electrically connected to the signal electrode 10a and an outer covering conductor 1a electrically connected to the ground electrode 1a, wherein the tip member is formed on a printed wiring board 2, and wherein the signal electrode 10a and the ground electrode 11a are constructed of fine coplanar strip lines formed on an insulating board 2a.
摘要翻译：提供了在信号电极和接地电极之间以间距小于50um的接触探针，并且可以正确地进行高速高频测量，用于接触探针的测量垫以及制造方法接触探头。接触探针包括：具有与被测量物体接触的信号电极10a和接地电极11a的尖端部件; 以及具有电连接到信号电极10a的芯1b和电连接到接地电极1a的外部覆盖导体1A的同轴电缆1，其中尖端构件形成在印刷线路板2上，并且其中，信号电极10a和接地电极11a由形成在绝缘板2a上的精细共面带状线构成。

9. 发明申请

US20050236717A1 System in-package test inspection apparatus and test inspection method 失效
标题翻译：系统包装试验检验装置及试验检验方法
公开(公告)号：US20050236717A1
公开(公告)日：2005-10-27
申请号：US11108861
申请日：2005-04-19
申请人： Masahiro Aoyagi , Hiroshi Nakagawa , Kazuhiko Tokoro , Katsuya Kikuchi , Yoshikuni Okada , Hiroyuki Fujita , Kenichi Kobayashi
发明人： Masahiro Aoyagi , Hiroshi Nakagawa , Kazuhiko Tokoro , Katsuya Kikuchi , Yoshikuni Okada , Hiroyuki Fujita , Kenichi Kobayashi
IPC分类号： G01R1/073 , G01R31/28 , H01L23/48
CPC分类号： G01R31/2822 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/48091 , H01L2224/48137 , H01L2224/48145 , H01L2224/48227 , H01L2924/00014 , H01L2924/15192 , H01L2924/15311 , H01L2224/05599 , H01L2924/00012
摘要： A system in-package test inspection apparatus for measuring and evaluating the high-speed/high frequency characteristic of a system in-package through an electrode pad in which I/O terminals are formed on one side of an LSI package containing metallic wiring internally and plural LSI chips are stacked in multiple layers on the other face while electric connection between the LSI chip and the LSI package and the electric connection between the LSI chips are implemented, the system in-package test inspection apparatus comprising: a printed wiring substrate to which the I/O terminals of the system in-package are connected to enable transmission of high speed and high frequency signals; LSI chip driving means for driving the LSI chip; a contact probe having a contact electrode and for transmitting a high frequency signal; evaluation signal generating means for supplying a high frequency evaluation signal to the contact probe; output signal detecting means for detecting an output signal of the system in-package through the printed wiring board; and analyzing means for analyzing a signal detected by the output signal detecting means, wherein by contacting the contact electrode of the contact probe with an electrode pad formed on the LSI chip, the evaluation signal is inputted to the LSI chip not through metallic wiring within the LSI package.
摘要翻译：一种用于测量和评估通过其内部形成有包含金属布线的LSI封装的一侧上的I / O端子的电极焊盘的系统的封装中的高速/高频特性的系统级封装测试检查装置，在LSI芯片和LSI封装之间的电连接和LSI芯片之间的电连接被实现的同时，多个LSI芯片被堆叠在多个层中，该系统的封装测试检查装置包括：印刷布线基板，连接系统内置的I / O端子，实现高速和高频信号的传输; 用于驱动LSI芯片的LSI芯片驱动装置; 具有接触电极并用于发送高频信号的接触探针; 评估信号发生装置，用于向接触探针提供高频评估信号; 输出信号检测装置，用于检测通过印刷电路板的封装中的系统的输出信号; 以及分析装置，用于分析由输出信号检测装置检测到的信号，其中通过使接触探针的接触电极与形成在LSI芯片上的电极焊盘接触，评估信号不通过金属布线输入到LSI芯片 LSI封装。

10. 发明授权

US07833835B2 Multi-layer fin wiring interposer fabrication process 有权
标题翻译：多层翅片接线插件制造工艺
公开(公告)号：US07833835B2
公开(公告)日：2010-11-16
申请号：US11890502
申请日：2007-08-07
申请人： Masahiro Aoyagi , Hiroshi Nakagawa , Kazuhiko Tokoro , Katsuya Kikuchi , Yoshikuni Okada
发明人： Masahiro Aoyagi , Hiroshi Nakagawa , Kazuhiko Tokoro , Katsuya Kikuchi , Yoshikuni Okada
IPC分类号： H01L21/60
CPC分类号： H01L25/0657 , H01L21/486 , H01L21/768 , H01L21/76898 , H01L23/3114 , H01L23/49827 , H01L25/0655 , H01L2225/06513 , H01L2225/06541 , H01L2225/06572 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An interposer having multi-layer fine wiring structure which comprises an insulating layer made of photosensitive polyimide which is photosensitive organic material and a wiring layer portion made of metal, such as copper, silver, gold, aluminum, palladium, indium, titanium, tantalum, and niobium, functions as wiring in an integrated circuit chip, wherein junctions between the integrated circuit chip and the interposer are formed by micron to submicron size fine connection metal pads or bumps which are formed on both the integrated circuit chip and the interposer.
摘要翻译：具有多层精细布线结构的插入件，其包括由感光性有机材料构成的感光性聚酰亚胺构成的绝缘层和铜，银，金，铝，钯，铟，钛，钽等金属制的布线层部，和铌，用作集成电路芯片中的布线，其中集成电路芯片和插入器之间的接合部由形成在集成电路芯片和插入器两者上的微米至亚微米尺寸的精细连接金属焊盘或凸块形成。

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