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1. 发明授权

US07492817B2 Adaptive digital filter 有权
标题翻译：自适应数字滤波器
公开(公告)号：US07492817B2
公开(公告)日：2009-02-17
申请号：US11056449
申请日：2005-02-11
申请人： Ryohei Tanaka , Toyokazu Kitano
发明人： Ryohei Tanaka , Toyokazu Kitano
IPC分类号： H03H7/30
CPC分类号： H03H21/0012
摘要： An adaptive digital filter includes a filtering circuit and a coefficient renewal circuit. The filtering circuit has a coefficient a defined by a fundamental formula: a[n+1]=a[n]+β·e[n]·q[n]/p[n]. β is a number greater than 0 and smaller than 2, e[n] is a difference between the input and the output of the filter, and q[n] and p[n] are formulas. The renewal circuit calculates a renewal value of the coefficient a. The coefficient renewal circuit calculates 2m (m is an integer) greater than p[n] in the fundamental formula, and also calculates the renewal value of the coefficient a in accordance with an execution formula: a[n+1]=a[n]+β·e[n]·q[n]/2m in place of the fundamental formula.
摘要翻译：自适应数字滤波器包括滤波电路和系数更新电路。滤波电路具有由基本公式a [n + 1] = a [n] + beta.e [n] .q [n] / p [n]定义的系数α。 β是大于0且小于2的数，e [n]是滤波器的输入和输出之间的差，q [n]和p [n]是公式。更新电路计算系数a的更新值。系数更新电路在基本公式中计算大于p [n]的2m（m是整数），并且还根据执行公式计算系数a的更新值：a [n + 1] = a [n ] + beta.e [n] .q [n] / 2m代替基本公式。

2. 发明申请

US20050069128A1 Data-generating device and data-writing device for FPGA 审中-公开
标题翻译：用于FPGA的数据生成设备和数据写入设备
公开(公告)号：US20050069128A1
公开(公告)日：2005-03-31
申请号：US10966173
申请日：2004-09-29
申请人： Takeshi Inoue , Hiroshi Matoba , Ryohei Tanaka , Toyokazu Kitano
发明人： Takeshi Inoue , Hiroshi Matoba , Ryohei Tanaka , Toyokazu Kitano
IPC分类号： G06F7/00 , G06F21/00 , H01L21/82 , H03K19/173 , H04L9/00
CPC分类号： G06F21/34 , G06F21/10 , H04L9/00 , H04L2209/56
摘要： Configuration-wiring information is generated by a function-restricted netlist. A data-writing device writes the generated information to FPGAs. The restriction-lifting section lifts the restriction of the restricted configuration-wiring data. Then, a bit stream is generated based on the configuration-wiring data. The bit stream is encrypted in the encryption section and then decrypted in the decryption section. The decrypted data is written to the FPGA by the data writing section. A dongle stores permitted writing count information contracted with an IP vendor. A remaining writing count is calculated based on the writing count information every time the writing to the FPGA is performed. When the remaining writing count becomes zero, the functional restriction lifting and the decryption are prohibited, so that IP netlist cannot be written to the FPGA.
摘要翻译：配置接线信息由功能受限制的网表生成。数据写入设备将生成的信息写入FPGA。限制提升部分提升了限制配置接线数据的限制。然后，基于配置布线数据生成位流。比特流在加密部分被加密，然后在解密部分解密。解密的数据由数据写入部分写入FPGA。加密狗商店允许与IP供应商签订的书面计数信息。每次执行对FPGA的写入时，基于写入计数信息计算剩余写入计数。当剩余写入次数为零时，禁止功能限制提升和解密，因此IP网表不能写入FPGA。

3. 发明申请

US20060248138A1 Signal processing device for computing phase difference between alternating current signals 有权
标题翻译：信号处理装置，用于计算交流信号之间的相位差
公开(公告)号：US20060248138A1
公开(公告)日：2006-11-02
申请号：US11406885
申请日：2006-04-19
申请人： Ryohei Tanaka , Toyokazu Kitano
发明人： Ryohei Tanaka , Toyokazu Kitano
IPC分类号： G06G7/00
CPC分类号： G01R19/2506 , G01R25/00 , H03H21/0012
摘要： A signal processing device includes a converting unit, a filtering unit, a differential computing unit, and a phase difference computing unit. The converting unit samples two alternating signals with a predetermined period and converts the sampled level values into digital alternating signal data. The filtering unit filters the two digital alternating signal data generated by the converting unit so as to abstract digital alternating signal data having a predetermined frequency, and the filtering unit comprises an adaptive digital filter. The differential computing unit computes differentials of the digital alternating signal data generated by the filtering unit. The phase difference computing unit computes phase difference using the two digital alternating signal data generated by the filtering unit, and the two digital alternating signal data generated by the differential computing unit.
摘要翻译：信号处理装置包括转换单元，滤波单元，差分计算单元和相位差计算单元。转换单元以预定周期对两个交替信号进行采样，并将采样的电平值转换为数字交替信号数据。滤波单元对由转换单元产生的两个数字交替信号数据进行滤波，以抽出具有预定频率的数字交替信号数据，并且滤波单元包括自适应数字滤波器。差分计算单元计算由滤波单元产生的数字交流信号数据的差分。相位差计算单元使用由滤波单元生成的两个数字交替信号数据和由差分计算单元生成的两个数字交替信号数据来计算相位差。

4. 发明授权

US07702702B2 Signal processing device for computing phase difference between alternating current signals 有权
标题翻译：信号处理装置，用于计算交流信号之间的相位差
公开(公告)号：US07702702B2
公开(公告)日：2010-04-20
申请号：US11406885
申请日：2006-04-19
申请人： Ryohei Tanaka , Toyokazu Kitano
发明人： Ryohei Tanaka , Toyokazu Kitano
IPC分类号： H03M1/00 , G06F1/02 , G06F17/10 , G01R25/00 , H03D13/00
CPC分类号： G01R19/2506 , G01R25/00 , H03H21/0012
摘要： A signal processing device includes a converting unit, a filtering unit, a differential computing unit, and a phase difference computing unit. The converting unit samples two alternating signals with a predetermined period and converts the sampled level values into digital alternating signal data. The filtering unit filters the two digital alternating signal data generated by the converting unit so as to abstract digital alternating signal data having a predetermined frequency, and the filtering unit comprises an adaptive digital filter. The differential computing unit computes differentials of the digital alternating signal data generated by the filtering unit. The phase difference computing unit computes phase difference using the two digital alternating signal data generated by the filtering unit, and the two digital alternating signal data generated by the differential computing unit.
摘要翻译：信号处理装置包括转换单元，滤波单元，差分计算单元和相位差计算单元。转换单元以预定周期对两个交替信号进行采样，并将采样的电平值转换为数字交替信号数据。滤波单元对由转换单元产生的两个数字交替信号数据进行滤波，以抽出具有预定频率的数字交替信号数据，并且滤波单元包括自适应数字滤波器。差分计算单元计算由滤波单元产生的数字交流信号数据的差分。相位差计算单元使用由滤波单元生成的两个数字交替信号数据和由差分计算单元生成的两个数字交替信号数据来计算相位差。

5. 发明申请

US20050180497A1 Adaptive digital filter 有权
标题翻译：自适应数字滤波器
公开(公告)号：US20050180497A1
公开(公告)日：2005-08-18
申请号：US11056449
申请日：2005-02-11
申请人： Ryohei Tanaka , Toyokazu Kitano
发明人： Ryohei Tanaka , Toyokazu Kitano
IPC分类号： H03H17/04 , H03H21/00 , H03K5/159
CPC分类号： H03H21/0012
摘要： An adaptive digital filter includes a filtering circuit and a coefficient renewal circuit. The filtering circuit has a coefficient a defined by a fundamental formula: a[n+1]=a[n]+β·e[n]·q[n]/p[n]. β is a number greater than 0 and smaller than 2, e[n] is a difference between the input and the output of the filter, and q[n] and p[n] are formulas. The renewal circuit calculates a renewal value of the coefficient a. The coefficient renewal circuit calculates 2m (m is an integer) greater than p[n] in the fundamental formula, and also calculates the renewal value of the coefficient a in accordance with an execution formula: a[n+1]=a[n]+β·e[n]·q[n]/2m in place of the fundamental formula.
摘要翻译：自适应数字滤波器包括滤波电路和系数更新电路。滤波电路具有由基本公式a [n + 1] = a [n] + beta.e [n] .q [n] / p [n]定义的系数α。 β是大于0且小于2的数，e [n]是滤波器的输入和输出之间的差，q [n]和p [n]是公式。更新电路计算系数a的更新值。系数更新电路计算基本公式中大于p [n]的2（m是整数），并且还根据执行公式计算系数a的更新值：a [ n + 1] = a [n] + beta.e [n] .q [n] / 2 代替基本公式。

6. 发明申请

US20050171992A1 Signal processing apparatus, and voltage or current measurer utilizing the same 审中-公开
标题翻译：信号处理装置，利用该信号处理装置的电压或电流测量装置
公开(公告)号：US20050171992A1
公开(公告)日：2005-08-04
申请号：US11048434
申请日：2005-01-31
申请人： Ryohei Tanaka , Toyokazu Kitano
发明人： Ryohei Tanaka , Toyokazu Kitano
IPC分类号： G01R19/02 , G01R19/00 , G06G7/02
CPC分类号： G01R19/02 , G01R19/0061
摘要： A signal processing apparatus produces a signal representing the effective value of an inputted alternating signal. The apparatus includes a square calculator, a filter and a square-root calculator. The square calculator produces a square signal representing several squared values of the inputted alternating signal. The filter extracts a DC component signal from the square signal. The square-root calculator produces a signal representing the square root of a level value of the extracted DC component signal.
摘要翻译：信号处理装置产生表示输入的交变信号的有效值的信号。该装置包括平方计算器，滤波器和平方根计算器。平方计算器产生表示输入的交变信号的几个平方值的平方信号。滤波器从平方信号中提取直流分量信号。平方根计算器产生表示提取的DC分量信号的电平值的平方根的信号。

7. 发明授权

US08654831B2 Signal detection apparatus 有权
标题翻译：信号检测装置
公开(公告)号：US08654831B2
公开(公告)日：2014-02-18
申请号：US13237182
申请日：2011-09-20
申请人： Toyokazu Kitano
发明人： Toyokazu Kitano
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： G01R25/005
摘要： A signal detection apparatus detects the frequency of an input signal without using a PLL. The detection apparatus includes a first and a second orthogonalizer, a phase difference calculator and an integrator, to control the variable coefficient a1 of a band-pass filter. Information e[k]=M·sin(φ) representing the phase difference φ between the input data x[k] and the output data y[k] is calculated with the first and second orthogonalizers and the phase difference calculator. The sign of e[k] is inverted and a predetermined integral calculation is performed with the integrator, and the calculated integral value is set as the coefficient a1 of the band-pass filter. Every time input data x[k] is input, the coefficient a1 is changed by reducing it when e[k]>0 and increasing it when e[k]
摘要翻译：信号检测装置在不使用PLL的情况下检测输入信号的频率。检测装置包括第一和第二正交器，相位差计算器和积分器，以控制带通滤波器的可变系数a1。使用第一和第二正交分析器和相位差计算器计算表示输入数据x [k]和输出数据y [k]之间的相位差phi的信息e [k] = M·sin（phi）。 e [k]的符号被反相，并且利用积分器执行预定的积分计算，并将计算的积分值设置为带通滤波器的系数a1。每当输入数据x [k]输入时，当e [k]> 0时，系数a1通过减小而改变，并且当e [k] <0时增加系数a1。因此，带通滤波器的输出信号的频率与输入信号相匹配。

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