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1. 发明授权

US5249100A Electronic circuit device provided with a ceramic substrate having lead pins bonded thereto by solder 失效
标题翻译：电子电路设备提供有一个陶瓷衬底，具有焊接的焊丝
公开(公告)号：US5249100A
公开(公告)日：1993-09-28
申请号：US522531
申请日：1990-05-11
申请人： Ryohei Satoh , Kazuo Hirota , Takaji Takenaka , Hideki Watanabe , Toshinori Ameya , Toshihiko Ohta
发明人： Ryohei Satoh , Kazuo Hirota , Takaji Takenaka , Hideki Watanabe , Toshinori Ameya , Toshihiko Ohta
IPC分类号： H01L23/50 , B23K35/30 , C04B37/02 , H01L21/60 , H01L23/433 , H01L23/498
CPC分类号： H01L24/81 , B23K35/3013 , C04B37/026 , H01L23/433 , H01L23/49811 , C04B2235/6565 , C04B2237/125 , C04B2237/126 , C04B2237/341 , C04B2237/343 , C04B2237/40 , C04B2237/568 , C04B2237/76 , C04B2237/80 , H01L2224/16 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/014 , H01L2924/09701 , H01L2924/15312 , H01L2924/15787 , H01L2924/351
摘要： Disclosed is an electronic circuit device in which the solder (14) connecting lead pins (6) to the ceramic substrate (2) has a melting point of 356.degree. C. to 450.degree. C. and has a tensile strength being low in such an extent that a thermal contraction stress generated in a cooling process of the solder (14) from the melting point thereof is low and the substrate (2) does not break. The solder (14) is a Au-Ge alloy containing 10-15 wt % of Ge. Electronic circuit devices, which employ the above solder (14) in the connections, are free from damages in the ceramic wiring substrate (2) due to the bonding. Further, when the electronic circuit device undergoes a series of assembly processes after the above bonding, such solder (14) does not melt, and wettability of such solder (14) is favorable.
摘要翻译：公开了一种电子电路装置，其中将引脚（6）连接到陶瓷基板（2）的焊料（14）的熔点为356℃至450℃，并且在这种在焊料（14）的熔点冷却过程中产生的热收缩应力低，基板（2）不破裂的程度。焊料（14）是含有10-15重量％的Ge的Au-Ge合金。在连接中使用上述焊料（14）的电子电路装置在陶瓷布线基板（2）中由于接合而没有损坏。此外，当电子电路装置经过上述接合之后的一系列装配工艺时，这种焊料（14）不熔化，并且这种焊料（14）的润湿性是有利的。

2. 发明授权

US5291419A Method for diagnosing the life of a solder connection 失效
标题翻译：用于诊断焊料连接寿命的方法
公开(公告)号：US5291419A
公开(公告)日：1994-03-01
申请号：US938517
申请日：1992-01-06
申请人： Ryohei Satoh , Katsuhiro Arakawa , Kiyoshi Kanai , Tsutomu Takahashi , Takaji Takenaka , Haruhiko Imada
发明人： Ryohei Satoh , Katsuhiro Arakawa , Kiyoshi Kanai , Tsutomu Takahashi , Takaji Takenaka , Haruhiko Imada
IPC分类号： G01N3/00 , G01N3/32 , G01N3/60 , G01M5/00
CPC分类号： G01N3/00 , G01N3/32 , G01N3/60 , G01N2203/0224 , G01N2203/0296
摘要： A method for evaluating the life of a connection between members including the steps of extracting parameters defining the shearing strain of a predetermined model representing the connection thereby to calculate the values of plural shearing strains of the connection, calculating the equivalent strain amplitude corresponding to thermal fatigue stress for each of the values of the plural shearing strains defining the relationship between the shearing strain and the equivalent strain amplitude, formulating a life evaluation criterion equation expressed using the equivalent strain amplitude, calculating, for the connection, the equivalent strain amplitude corresponding to each of the shearing strains actually measured using the equation, and substituting the equivalent strain amplitude for the life evaluation criterion equation to acquire the life of the connection. Further, in this method, an equation for evaluating the advancement of a crack is made using the equivalent strain amplitude, and the equivalent is substituted for the crack advancement evaluation equation to calculate the length of the crack.
摘要翻译：一种用于评估构件之间的连接寿命的方法，包括提取定义表示连接的预定模型的剪切应变的参数的步骤，从而计算连接的多个剪切应变值，计算对应于热疲劳的等效应变幅度制定剪切应变与等效应变幅度之间的关系的多个剪切应变中的每个值的应力，制定使用等效应变振幅表示的寿命评估标准方程，为连接计算对应于每个剪切应变的等效应变幅度的剪切应变使用等式实际测量，并将等效应变幅度代入寿命评估标准方程来获得连接的寿命。此外，在该方法中，使用等效应变振幅来进行用于评价裂纹的推进的方程，并且将等效物代入裂纹推进评价方程式来计算裂纹的长度。

3. 发明授权

US5136360A Electronic circuit device, method of connecting with solder and solder for connecting gold-plated terminals 失效
标题翻译：电子电路器件，连接焊料和焊料的方法，用于连接镀金端子
公开(公告)号：US5136360A
公开(公告)日：1992-08-04
申请号：US563281
申请日：1990-08-06
申请人： Masahide Harada , Ryohei Satoh , Fumiyuki Kobayashi , Takaji Takenaka , Toshitada Netsu , Hideaki Sasaki , Mitugu Shirai
发明人： Masahide Harada , Ryohei Satoh , Fumiyuki Kobayashi , Takaji Takenaka , Toshitada Netsu , Hideaki Sasaki , Mitugu Shirai
IPC分类号： B23K35/22 , B23K35/26 , C22C13/00 , H01L21/60 , H01L23/488 , H05K3/34
CPC分类号： H05K3/3463 , B23K35/262 , H01L23/488 , H01L2224/16225
摘要： An electronic circuit device comprising an electronic part having a gold-plated connecting terminal arranged thereon connected through a solder to a circuit substrate on the predetermined connecting element thereof, in which the connecting terminal of the electronic part and the solder-connected portion of the circuit substrate are constituted by an alloy composition consisting of 1.0 to 8.0 wt. % of Ag, 0.1 to 6.0 wt % of Au and the balance of Sn, is provided. The device is made by using a solder for use in connecting a gold-plated connecting terminal which consists of 1.0 to 8.0 wt % of Ag and the balance of Sn and a method of connecting an electronic part having a gold-plated connecting terminal arranged thereon to a circuit substrate, which comprises the steps of placing the electronic part and the gold-plated connected terminal so as to face each other via a solder and then melting the solder to connect and fix the connecting terminal to the circuit substrate onto the predetermined element thereof, the composition of said solder consisting of 1.0 to 8.0 wt % Ag and the balance of Sn.
摘要翻译：一种电子电路装置，包括电子部件，该电子部件具有通过焊料连接到其预定连接元件上的电路基板上的镀金连接端子，其中电子部件的连接端子和电路的焊接部分基材由1.0〜8.0重量份的合金组成构成。提供Ag的％，0.1〜6.0重量％的Au和余量的Sn。该装置通过使用焊料制成，用于连接由1.0至8.0重量％的Ag组成的镀金连接端子和余量的Sn，以及连接其上布置有镀金连接端子的电子部件的方法电路基板，其包括以下步骤：通过焊料将电子部件和镀金连接的端子放置成彼此面对，然后熔化焊料以将连接端子连接并固定到电路基板到预定元件所述焊料的组成由1.0至8.0重量％的Ag和余量的Sn组成。

4. 发明授权

US4673772A Electronic circuit device and method of producing the same 失效
标题翻译：电子电路装置及其制造方法
公开(公告)号：US4673772A
公开(公告)日：1987-06-16
申请号：US784035
申请日：1985-10-04
申请人： Ryohei Satoh , Muneo Oshima , Minoru Tanaka , Suguru Sakaguchi , Akira Murata , Kazuo Hirota
发明人： Ryohei Satoh , Muneo Oshima , Minoru Tanaka , Suguru Sakaguchi , Akira Murata , Kazuo Hirota
IPC分类号： B23K35/14 , H01L21/60 , H01L21/607 , H01L23/485 , H05K3/34 , H01L23/14
CPC分类号： H01L24/10 , H01L24/13 , H01L24/81 , H05K3/3436 , H01L2224/13 , H01L2224/13099 , H01L2224/131 , H01L2224/13116 , H01L2224/13144 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/81801 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01025 , H01L2924/01027 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15787 , H01L2924/16195 , H01L2924/19041 , H01L2924/19043 , H05K2201/10636 , H05K2201/10727 , H05K2201/10992 , H05K2203/0108 , H05K2203/033 , H05K2203/0338 , H05K2203/0405 , H05K2203/0415 , H05K3/3442 , Y02P70/611 , Y02P70/613 , Y10T29/49144
摘要： In connecting an electronic circuit part such as a semiconductor or other part to a substrate for mounting the part with solder, the solder is composed of a high-melting-point solder portion which is subjected to working such as rolling and heat treatment in order to break the cast structure thereof, and a smaller volume of low-melting-point solder portions. The high-melting-point solder portion is connected to both the electronic circuit substrate and the electronic circuit part through the low-point-melting solder portions.This method enables interconnection between objects to be connected without impairing the high ductility and toughness of the high-melting-point solder which is subjected to working and heat treatment. This soldering method ensures highly reliable manufacture of miniaturized high density circuits, such as LSI.
摘要翻译：在将诸如半导体或其他部分的电子电路部分连接到用于用焊料安装部件的基板时，焊料由经受诸如轧制和热处理的加工的高熔点焊料部分组成，以便破坏其铸造结构和较低体积的低熔点焊料部分。高熔点焊料部分通过低熔点焊料部分与电子电路基板和电子电路部分连接。该方法能够连接物体之间的连接，而不会损害经受加工和热处理的高熔点焊料的高延展性和韧性。这种焊接方法确保了LSI等小型化高密度电路的高可靠性制造。

5. 发明授权

US5731066A Electronic circuit device 失效
标题翻译：电子电路装置
公开(公告)号：US5731066A
公开(公告)日：1998-03-24
申请号：US546795
申请日：1995-10-23
申请人： Akihiro Ando , Osamu Yamada , Ryohei Satoh , Takashi Inoue , Masahide Okamoto , Fumiyuki Kobayashi , Toshihiko Ohta , Minoru Tanaka
发明人： Akihiro Ando , Osamu Yamada , Ryohei Satoh , Takashi Inoue , Masahide Okamoto , Fumiyuki Kobayashi , Toshihiko Ohta , Minoru Tanaka
IPC分类号： H05K1/09 , B23K1/00 , H01L23/498 , H05K1/11 , H05K1/18 , H05K3/40 , H05K3/46 , B32B3/00 , B32B15/00 , B23K31/02 , H01R9/09
CPC分类号： H01L23/49811 , B23K1/0016 , H05K1/111 , B23K2201/40 , H01L2924/0002 , H01L2924/09701 , H05K1/092 , H05K2201/0376 , H05K2201/098 , H05K3/4007 , H05K3/4611 , H05K3/4629 , Y02P70/611 , Y10T428/24926
摘要： In an electronic circuit device having an input/output pin junction electrode, in order to remarkably improve the junction characteristics such as wettability and junction strength and to drastically simplify the production process, in forming an electronic circuit board in which glass ceramics is used for board material and a wiring conductor and junction electrode wherein the Cu is sized to extend beyond the pin hole so that solder only contacts it and not the ceramic circuit board. The wiring and junction electrode is formed in a same process while forming a cover coat on the electrode using board material, and Au or Au--Ni laminated film is formed on this electrode as occasion demands, and then an electronic component is connected thereto using a solder such a Au--Sn or Au--Ge.
摘要翻译：在具有输入/输出引脚接合电极的电子电路装置中，为了显着地改善诸如润湿性和接合强度的接合特性并且大大简化了制造工艺，在形成玻璃陶瓷用于板的电子电路板材料和布线导体和接合电极，其中Cu的尺寸设置成延伸超过针孔，使得焊料仅与其接触而不是陶瓷电路板。在使用基板材料的电极上形成覆盖层时，以相同的工序形成布线和接合电极，根据需要在该电极上形成Au或Au-Ni层叠膜，然后使用焊接如Au-Sn或Au-Ge。

6. 发明申请

US20120053905A1 DESIGN WORKFLOW CONSTRUCTION APPARATUS, DESIGN WORKFLOW CONSTRUCTION METHOD, DESIGN SYSTEM, DESIGN METHOD, DESIGN WORKFLOW CONSTRUCTION PROGRAM, AND COMPUTER READABLE RECORDING MEDIUM IN WHICH DESIGN WORKFLOW CONSTRUCTION PROGRAM IS STORED 有权
标题翻译：设计工作流施工设备，设计工作流程施工方法，设计系统，设计方法，设计工作流程构造程序和设计工作流程构建程序存储的计算机可读记录介质
公开(公告)号：US20120053905A1
公开(公告)日：2012-03-01
申请号：US13201854
申请日：2010-02-16
申请人： Yoshiharu Iwata , Ryohei Satoh , Keiji Kudo , Atsushi Taya , Kazuya Okamoto , Hidenori Murata , Koichiro Atsumi , Eiji Arai , Eiji Morinaga
发明人： Yoshiharu Iwata , Ryohei Satoh , Keiji Kudo , Atsushi Taya , Kazuya Okamoto , Hidenori Murata , Koichiro Atsumi , Eiji Arai , Eiji Morinaga
IPC分类号： G06F17/50
CPC分类号： G06Q10/06 , G06Q10/0633
摘要： A design system (1) is provided with a function of acquiring a design specification of an object to be designed and an evaluation index for evaluating a value of the object to be designed in the design specification; a function of acquiring profile data of the object to be designed; a function (design order determining section (12)) of extracting entity design elements and important design variables from the profile data and prioritizing the entity design elements and the important design variables so as to construct a design workflow; a function (evaluation approach construction section (13)) of constructing an evaluation formula for performance/evaluation of a design result of each of the entity design elements in conformity with the design workflow; a function of finding an appropriate solution by performing automatic optimization while evaluating the design result with use of the evaluation index in accordance with the design workflow with which the evaluation formula is associated; and a function of outputting the appropriate solution thus found. This allows the object to be designed to be parametrically handled, and makes it possible to create a design workflow for efficiently finding an optimum design solution by properly combining a series of design elements and to find an appropriate solution with the use of the design workflow.
摘要翻译：设计系统（1）具有获取要设计的对象的设计规范和评估设计规范中要设计的对象的值的评估指标的功能; 获取要设计的对象的简档数据的功能; 从简档数据中提取实体设计元素和重要设计变量的功能（设计顺序确定部分（12）），并对实体设计元素和重要设计变量进行优先排序，从而构建设计工作流程; （评估方法构建部（13）），其根据设计工作流程构建用于对每个实体设计元素的设计结果进行性能/评估的评估公式; 通过根据与评估公式相关联的设计工作流程使用评估指数来评估设计结果，通过执行自动优化来找到适当的解决方案的功能; 以及输出由此找到的适当解决方案的功能。这允许将对象设计为参数化处理，并且可以创建设计工作流，以通过适当地组合一系列设计元素来有效地找到最佳设计解决方案，并使用设计工作流程找到适当的解决方案。

7. 发明授权

US07846641B2 Glass substrate having circuit pattern and process for producing the same 有权
标题翻译：具有电路图案的玻璃基板及其制造方法
公开(公告)号：US07846641B2
公开(公告)日：2010-12-07
申请号：US12143446
申请日：2008-06-20
申请人： Ryohei Satoh , Koji Nakagawa , Reo Usui , Kenji Tanaka , Satoru Takaki , Kenichi Ebata , Yumiko Aoki
发明人： Ryohei Satoh , Koji Nakagawa , Reo Usui , Kenji Tanaka , Satoru Takaki , Kenichi Ebata , Yumiko Aoki
IPC分类号： G03F7/26
CPC分类号： H05K3/28 , H01J9/02 , H01J11/12 , H01J11/34 , H05K1/0306 , H05K3/027 , H05K3/38 , H05K2201/0269 , Y10T428/24868
摘要： A process for producing a glass substrate having a circuit pattern is disclosed. The process includes forming a thin film layer on a glass substrate and then irradiating the thin film layer with laser light to form a circuit pattern on the glass substrate; depositing a low-melting point glass having a softening point of from 450 to 630° C. on the glass substrate having the circuit pattern formed thereon; and sintering the low-melting point glass to form a low-melting point glass layer which includes the low-melting point glass sintered on the glass substrate having the circuit pattern formed thereon and which forms a compatible layer between the glass substrate and the low-melting point glass layer.
摘要翻译：公开了一种具有电路图案的玻璃基板的制造方法。该方法包括在玻璃基板上形成薄膜层，然后用激光照射薄膜层，以在玻璃基板上形成电路图案; 在其上形成有电路图案的玻璃基板上沉积软化点为450〜630℃的低熔点玻璃; 并烧结低熔点玻璃以形成低熔点玻璃层，该低熔点玻璃层包括在其上形成有电路图案的玻璃基板上烧结的低熔点玻璃，并且在玻璃基板和低熔点玻璃之间形成相容层，熔点玻璃层。

8. 发明授权

US06919670B2 Rib structure for display device and its manufacture process 失效
标题翻译：显示器件的肋结构及其制造工艺
公开(公告)号：US06919670B2
公开(公告)日：2005-07-19
申请号：US09989063
申请日：2001-11-21
申请人： Yoshimi Kawanami , Yasuhiko Kunii , Tadashi Furukawa , Akihiro Fujinaga , Kazunori Ishizuka , Shoichi Iwanaga , Fumihiro Namiki , Ryohei Satoh
发明人： Yoshimi Kawanami , Yasuhiko Kunii , Tadashi Furukawa , Akihiro Fujinaga , Kazunori Ishizuka , Shoichi Iwanaga , Fumihiro Namiki , Ryohei Satoh
IPC分类号： H01J9/02 , H01J9/24 , H01J11/22 , H01J11/34 , H01J11/36 , H01J17/49
CPC分类号： H01J9/242 , H01J9/245 , H01J11/12 , H01J11/36 , H01J2211/366
摘要： A rib structure for a display device includes a light-transmissive rib structure containing therein a material absorbent of visible light so that a visible light absorption distance is 40 to 1200 μm (the visible light absorption distance L (μm) means a distance such that visible light decreases to exp(−T/L) times less in connection to the travel distance T (μm), that is, visible light is absorbed by 1-exp(−T/L)).
摘要翻译：用于显示装置的肋结构包括透光肋结构，其中包含可见光的材料吸收剂，使得可见光吸收距离为40至1200μm（可见光吸收距离L（mum）表示使得可见光相对于行驶距离T（mum），光减少到exp（-T / L）次，即可见光被1-exp（-T / L）吸收）。

9. 发明授权

US5865365A Method of fabricating an electronic circuit device 失效
标题翻译：制造电子电路装置的方法
公开(公告)号：US5865365A
公开(公告)日：1999-02-02
申请号：US761430
申请日：1996-12-06
申请人： Toru Nishikawa , Ryohei Satoh , Masahide Hara , Tetsuya Hayashida , Mitugu Shirai , Osamu Yamada , Hiroko Takehara , Yasuhiro Iwata , Mitsunori Tamura , Masahito Ijuin
发明人： Toru Nishikawa , Ryohei Satoh , Masahide Hara , Tetsuya Hayashida , Mitugu Shirai , Osamu Yamada , Hiroko Takehara , Yasuhiro Iwata , Mitsunori Tamura , Masahito Ijuin
IPC分类号： B23K1/00 , H01L21/48 , H01L21/56 , H01L21/60 , H01L21/68 , H01L23/498 , H05K3/34
CPC分类号： H01L24/12 , B23K1/0016 , H01L21/4853 , H01L21/563 , H01L21/6835 , H01L23/49816 , H01L24/11 , H01L24/29 , H01L24/81 , H01L24/83 , H05K3/3489 , B23K2201/40 , H01L2224/11003 , H01L2224/11334 , H01L2224/13099 , H01L2224/13111 , H01L2224/16225 , H01L2224/29109 , H01L2224/29111 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/81801 , H01L2224/83192 , H01L2224/83805 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01018 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/15787 , H01L2924/3025 , H05K2203/0278 , H05K2203/041 , H05K2203/0435 , H05K2203/086 , H05K2203/087 , H05K2203/095 , H05K2203/1157 , H05K3/3426
摘要： A method of soldering used in fabricating an electronic circuit device employs an organic material supplied to at least one of the connecting members to be bonded. The connecting members are positioned in an oxidizing atmosphere, and heated in a nonoxidizing atmosphere to remove oxide and/or contamination layers present on the surface of presoldered portions or metallized bonding portions. By this method, fluxless soldering is performed, positional shifts are reduced, and high reliability of the soldering connections with reduction in residues after reflow are obtained.
摘要翻译：用于制造电子电路器件的焊接方法使用供应至待接合的至少一个连接部件的有机材料。连接构件位于氧化气氛中，并在非氧化气氛中加热以除去存在于预制部分或金属化粘合部分的表面上的氧化物和/或污染层。通过该方法，进行无焊剂焊接，位移偏移降低，并且获得了在回流之后具有减少残留物的焊接连接的高可靠性。

10. 发明申请

US20060240338A1 Pattern formation method, electronic circuit manufactured by the same, and electronic device using the same 失效
标题翻译：图案形成方法，由其制造的电子电路和使用其的电子装置
公开(公告)号：US20060240338A1
公开(公告)日：2006-10-26
申请号：US11431504
申请日：2006-05-11
申请人： Ryohei Satoh , Yoshinori Iwata , Koji Nakagawa , Reo Usui
发明人： Ryohei Satoh , Yoshinori Iwata , Koji Nakagawa , Reo Usui
IPC分类号： G03C5/00 , G03F1/00
CPC分类号： H01L21/76838 , H01L21/0272
摘要： There is provided a method for forming a continuous thin film circuit pattern with good precision, at low cost and with low environmental burden; an electronic circuit fabricated by the same, and an electronic device including the same. There are a step for forming a mask layer 2 on a substrate 1; a step for forming an opening pattern in the mask layer 2; a step for forming a thin film 3 on the substrate 1 and on the mask layer 2; and a step for removing, from the substrate 1, the mask layer 2 and a portion of the thin film 3 formed on the mask layer 2; wherein the opening pattern is formed under a dry condition.
摘要翻译：提供了一种以低成本，低环境负荷精度良好地形成连续薄膜电路图案的方法。由其制造的电子电路和包括该电子电路的电子设备。在基板1上形成掩模层2的步骤; 用于在掩模层2中形成开口图案的步骤; 在基板1和掩模层2上形成薄膜3的工序; 以及从基板1除去掩模层2和形成在掩模层2上的薄膜3的一部分的步骤; 其中所述开口图案在干燥条件下形成。

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