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1. 发明授权

US06954848B2 Marking in history table instructions slowable/delayable for subsequent executions when result is not used immediately 失效
标题翻译：当结果未立即使用时，在历史记录表中指示可以缓慢/延迟后续执行
公开(公告)号：US06954848B2
公开(公告)日：2005-10-11
申请号：US10038038
申请日：2002-01-02
申请人： Ryan Rakvic , Christopher Wilkerson , Bryan Black , Edward Grochowski , John Shen , Edward Brekelbaum
发明人： Ryan Rakvic , Christopher Wilkerson , Bryan Black , Edward Grochowski , John Shen , Edward Brekelbaum
IPC分类号： G06F9/00 , G06F9/30 , G06F9/38
CPC分类号： G06F9/3824 , G06F9/3836 , G06F9/3838
摘要： After an instruction loads data into a register at a first time, the register is monitored to see if it is read in a next clock cycle. When the data is not read in the next clock cycle, the instruction is classified as a slowable instruction. An instruction address associated with the instruction is used to update a history table. The history table stores information to indicate if an instruction is a slowable instruction or a non-slowable instruction. When the instruction address of the instruction is encountered at a second time, the history table is used to determine if the instruction is slowable or non-slowable.
摘要翻译：在第一次指令将数据加载到寄存器中之后，监视寄存器以查看是否在下一个时钟周期读取。当数据在下一个时钟周期内未被读取时，指令被分类为慢指令。与指令相关联的指令地址用于更新历史表。历史表存储用于指示指令是指令是慢指令还是非慢指令的信息。当第二次遇到指令的指令地址时，使用历史表来确定指令是可慢还是不慢。

2. 发明申请

US20050081017A1 Method and apparatus for predication using micro-operations 有权
标题翻译：使用微操作进行预测的方法和装置
公开(公告)号：US20050081017A1
公开(公告)日：2005-04-14
申请号：US10685654
申请日：2003-10-14
申请人： Jeffrey Rupley , Edward Brekelbaum , Edward Grochowski , Bryan Black
发明人： Jeffrey Rupley , Edward Brekelbaum , Edward Grochowski , Bryan Black
IPC分类号： G06F9/30 , G06F9/312 , G06F9/38
CPC分类号： G06F9/30043 , G06F9/30072 , G06F9/30145 , G06F9/30167 , G06F9/3017 , G06F9/3836 , G06F9/384
摘要： Disclosed are an apparatus, system, and method for implementing predicated instructions using micro-operations. A micro-code engine receives an instruction, decomposes the instruction, and generates a plurality of micro-operations to implement the instruction. Each of the decomposed micro-operations indicates a single destination register. For predicated instructions, the decomposed micro-operations include “conditional move” micro-operations to select between two potential output values. Except in the case that one of the potential output values is a constant, the decomposed micro-operations for a predicated instruction also include an append instruction that saves the incoming value of a destination register in a temporary variable. For at least one embodiment, the qualifying predicate for a predicated instruction is appended to the incoming value stored in the temporary register.
摘要翻译：公开了一种用于使用微操作来实现预定指令的装置，系统和方法。微码引擎接收指令，分解指令，并产生多个微操作来实现该指令。每个分解的微操作指示单个目的地寄存器。对于预测指令，分解的微操作包括在两个潜在输出值之间选择的“条件移动”微操作。除了在一个潜在输出值是常数的情况下，用于预测指令的分解的微操作还包括将目的地寄存器的输入值保存在临时变量中的附加指令。对于至少一个实施例，用于预测指令的限定谓词附加到存储在临时寄存器中的输入值。

3. 发明授权

US07120749B2 Cache mechanism 失效
标题翻译：缓存机制
公开(公告)号：US07120749B2
公开(公告)日：2006-10-10
申请号：US10803452
申请日：2004-03-18
申请人： Ryan Rakvic , Youfeng Wu , Bryan Black , John Shen
发明人： Ryan Rakvic , Youfeng Wu , Bryan Black , John Shen
IPC分类号： G06F12/12
CPC分类号： G06F12/0848 , G06F12/0888
摘要： According to one embodiment a system is disclosed. The system includes a central processing unit (CPU), a first cache memory coupled to the CPU to store only data for vital loads that are to be immediately processed at the CPU, a second cache memory coupled to the CPU to store data for semi-vital loads to be processed at the CPU, and a third cache memory coupled to the CPU, the first cache memory and the second cache memory to store non-vital loads to be processed at the CPU.
摘要翻译：根据一个实施例，公开了一种系统。该系统包括中央处理单元（CPU），第一高速缓存存储器，其耦合到CPU以仅存储要在CPU处理的重要负载的数据;耦合到CPU的第二高速缓存存储器，在CPU处理的重要负载，以及耦合到CPU，第一高速缓冲存储器和第二高速缓冲存储器的第三高速缓存存储器，用于存储要在CPU处理的非重要负载。

4. 发明申请

US20050210197A1 Cache mechanism 失效
标题翻译：缓存机制
公开(公告)号：US20050210197A1
公开(公告)日：2005-09-22
申请号：US10803452
申请日：2004-03-18
申请人： Ryan Rakvic , Youfeng Wu , Bryan Black , John Shen
发明人： Ryan Rakvic , Youfeng Wu , Bryan Black , John Shen
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0848 , G06F12/0888
摘要： According to one embodiment a system is disclosed. The system includes a central processing unit (CPU), a first cache memory coupled to the CPU to store only data for vital loads that are to be immediately processed at the CPU, a second cache memory coupled to the CPU to store data for semi-vital loads to be processed at the CPU, and a third cache memory coupled to the CPU, the first cache memory and the second cache memory to store non-vital loads to be processed at the CPU.
摘要翻译：根据一个实施例，公开了一种系统。该系统包括中央处理单元（CPU），第一高速缓存存储器，其耦合到CPU以仅存储要在CPU处理的重要负载的数据;耦合到CPU的第二高速缓存存储器，在CPU处理的重要负载，以及耦合到CPU，第一高速缓冲存储器和第二高速缓冲存储器的第三高速缓存存储器，用于存储要在CPU处理的非重要负载。

5. 发明授权

US07228402B2 Predicate register file write by an instruction with a pending instruction having data dependency 有权
标题翻译：通过具有数据相关性的挂起指令的指令来写入寄存器文件
公开(公告)号：US07228402B2
公开(公告)日：2007-06-05
申请号：US10037592
申请日：2002-01-02
申请人： Bohuslav Rychlik , Ryan N. Rakvic , Edward Brekelbaum , Bryan Black
发明人： Bohuslav Rychlik , Ryan N. Rakvic , Edward Brekelbaum , Bryan Black
IPC分类号： G06F9/00
CPC分类号： G06F9/3013 , G06F9/30072 , G06F9/3836 , G06F9/3838 , G06F9/384
摘要： A method to handle data dependencies in a pipelined computer system is disclosed. The method includes allocating a plurality of registers, enabling execution of computer instructions concurrently by using the plurality of registers, and tracking and reducing data dependencies in the computer instructions by correlating a busy condition of a computer instruction to each register.
摘要翻译：公开了一种在流水线计算机系统中处理数据依赖性的方法。该方法包括分配多个寄存器，使得能够通过使用多个寄存器来同时执行计算机指令，以及通过将计算机指令的繁忙状态与每个寄存器相关联来跟踪和减少计算机指令中的数据依赖性。

6. 发明申请

US20060010292A1 Multi-purpose register cache 有权
标题翻译：多用途寄存器缓存
公开(公告)号：US20060010292A1
公开(公告)日：2006-01-12
申请号：US10886402
申请日：2004-07-06
申请人： John DeVale , Bryan Black , Edward Brekelbaum , Jeffrey Rupley
发明人： John DeVale , Bryan Black , Edward Brekelbaum , Jeffrey Rupley
IPC分类号： G06F12/00
CPC分类号： G06F9/3826 , G06F9/3824 , G06F9/3836 , G06F9/3857 , G06F9/3859 , G06F12/0875 , Y02D10/13
摘要： A technique to use available register cache resources if register file resources are unavailable. Embodiments of the invention pertain to a register cache writeback algorithm for storing writeback data to a register cache if register file write ports or space is unavailable.
摘要翻译：如果注册文件资源不可用，则使用可用的注册缓存资源的技术。如果寄存器文件写入端口或空间不可用，本发明的实施例涉及用于将写回数据存储到寄存器高速缓存的寄存器高速缓存回写算法。

7. 发明申请

US20050027968A1 Renaming for register with multiple bit fields 有权
标题翻译：重命名为多个位字段注册
公开(公告)号：US20050027968A1
公开(公告)日：2005-02-03
申请号：US10632432
申请日：2003-07-31
申请人： Jeffrey Rupley , Edward Brekelbaum , Bryan Black
发明人： Jeffrey Rupley , Edward Brekelbaum , Bryan Black
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38
CPC分类号： G06F9/3836 , G06F9/30036 , G06F9/30072 , G06F9/30094 , G06F9/30112 , G06F9/384
摘要： An apparatus and method are provided for renaming a logical register for which bit accesses of varying lengths are permitted, such as a predicate register. Rename logic supports renaming for both partial-bit accesses and bulk-bit accesses to bits of the register. Rename logic utilizes a rename map table associated with the logical register to be renamed and also includes a plurality of physical rename registers. They physical rename registers include a set of skinny physical rename registers to be used for renaming for partial-bit writes. The physical rename registers also include a set of fat physical rename registers to be used for renaming for bulk-bit writes. Additional sizes of physical rename registers may also be employed. The entries of the single physical rename map table may point to either fat or skinny physical rename registers.
摘要翻译：提供了一种装置和方法，用于重命名允许不同长度的比特访问的逻辑寄存器，例如谓词寄存器。重命名逻辑支持对部分位访问和对寄存器的位的批量访问进行重命名。重命名逻辑利用与逻辑寄存器相关联的重命名映射表来重命名，并且还包括多个物理重命名寄存器。它们的物理重命名寄存器包括一组用于部分位写入重命名的瘦物理重命名寄存器。物理重命名寄存器还包括一组用于批量位写入重命名的胖物理重命名寄存器。还可以使用附加大小的物理重命名寄存器。单个物理重命名映射表的条目可能指向胖或瘦身体重命名寄存器。

8. 发明申请

US20050149681A1 Predictive filtering of register cache entry 有权
标题翻译：寄存器缓存条目的预测过滤
公开(公告)号：US20050149681A1
公开(公告)日：2005-07-07
申请号：US10747625
申请日：2003-12-30
申请人： John Devale , Bryan Black , Edward Brekelbaum , Jeffrey Rupley
发明人： John Devale , Bryan Black , Edward Brekelbaum , Jeffrey Rupley
IPC分类号： G06F12/00
CPC分类号： G06F9/30138
摘要： A mechanism, which supports predictive register cache allocation and entry, uses a counter look-up table to determine the potential significances of physical register references.
摘要翻译：支持预测寄存器高速缓存分配和输入的机制使用计数器查找表来确定物理寄存器引用的潜在重要性。

9. 发明申请

US20170213787A1 INTERPOSER WITH BEYOND RETICLE FIELD CONDUCTOR PADS 有权
公开(公告)号：US20170213787A1
公开(公告)日：2017-07-27
申请号：US15007791
申请日：2016-01-27
申请人： Michael S. Alfano , Bryan Black , Michael Z. Su , Joseph R. Siegel , Julius E. Din , Anwar Kashem
发明人： Michael S. Alfano , Bryan Black , Michael Z. Su , Joseph R. Siegel , Julius E. Din , Anwar Kashem
IPC分类号： H01L23/498 , H01L23/00 , H01L21/48
CPC分类号： H01L24/81 , H01L21/4846 , H01L21/486 , H01L23/147 , H01L23/49816 , H01L23/49822 , H01L23/5384 , H01L24/16 , H01L2224/16227
摘要： Various interposers and methods of manufacturing related thereto are disclosed. In one aspect, an apparatus is provided that includes an interposer that has a first side and a second side opposite the first side. The first side has a first reticle field and a second reticle field larger than the first reticle field. Plural conductor pads are positioned on the first side in the first reticle field. Plural dummy conductor pads are positioned on the first side in the second reticle field and outside the first reticle field.

10. 发明申请

US20130341783A1 INTERPOSER WITH IDENTIFICATION SYSTEM 审中-公开
标题翻译：具有识别系统的插件
公开(公告)号：US20130341783A1
公开(公告)日：2013-12-26
申请号：US13529736
申请日：2012-06-21
申请人： Michael Alfano , Joe Siegel , Michael Z. Su , Bryan Black , Julius Din
发明人： Michael Alfano , Joe Siegel , Michael Z. Su , Bryan Black , Julius Din
IPC分类号： H01L21/50 , H01L23/52
CPC分类号： H01L23/49827 , H01L22/14 , H01L22/20 , H01L23/147 , H01L23/49822 , H01L23/5382 , H01L23/544 , H01L24/16 , H01L24/97 , H01L25/0652 , H01L25/0655 , H01L2223/5444 , H01L2223/54446 , H01L2223/54453 , H01L2223/54473 , H01L2223/54486 , H01L2224/1134 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13164 , H01L2224/13169 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/01322 , H01L2924/12042 , H01L2924/15311 , H01L2224/81 , H01L2924/01047 , H01L2924/00012 , H01L2924/01029 , H01L2924/00014 , H01L2924/00
摘要： Various interposers and method of manufacturing related thereto are disclosed. In one aspect, a method of manufacturing is provided that includes coupling an identification structure to an interposer. The identification structure is operable to provide identification information about the interposer. The identification structure is programmable to create or alter the identification information.
摘要翻译：公开了各种插入件及其制造方法。一方面，提供一种制造方法，其包括将识别结构耦合到插入器。识别结构可操作以提供关于插入器的识别信息。识别结构是可编程的，以创建或改变识别信息。

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