专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20130036297A1 META PREDICTOR RESTORATION UPON DETECTING MISPREDICTION 有权
标题翻译： META预测恢复检测故障
公开(公告)号：US20130036297A1
公开(公告)日：2013-02-07
申请号：US13647153
申请日：2012-10-08
申请人： Stephan Jourdan , Adi Yoaz , Mattan Erez , Ronny Ronen
发明人： Stephan Jourdan , Adi Yoaz , Mattan Erez , Ronny Ronen
IPC分类号： G06F9/38
CPC分类号： G06F9/3861 , G06F9/3848
摘要： Methods and apparatus for restoring a meta predictor system upon detecting a branch or binary misprediction, are disclosed. An example apparatus may include a base misprediction history register to store a set of misprediction history values each indicating whether a previous branch prediction taken by a previous branch instruction was predicted correctly or incorrectly. The apparatus may comprise a meta predictor to detect a branch misprediction of a current branch prediction based at least in part on an output of the base misprediction history register. The meta predictor may restore the base misprediction history register based on the detecting of the branch misprediction. Additional apparatus, systems, and methods are disclosed.
摘要翻译：公开了在检测到分支或二进制错误预测时恢复元预测系统的方法和装置。一个示例性装置可以包括一个基本错误预测历史寄存器，用于存储一组错误预测历史值，每个错误预测历史值指示是否正确或不正确地预测了由先前的分支指令取得的先前分支预测。该装置可以包括元预测器，用于至少部分地基于基本错误预测历史寄存器的输出来检测当前分支预测的分支错误预测。元预测器可以基于检测到分支错误预测来恢复基本的错误预测历史寄存器。公开了附加装置，系统和方法。

2. 发明授权

US08572358B2 Meta predictor restoration upon detecting misprediction 有权
公开(公告)号：US08572358B2
公开(公告)日：2013-10-29
申请号：US13647153
申请日：2012-10-08
申请人： Ronny Ronen , Mattan Erez , Stephan Jourdan , Adi Yoaz
发明人： Ronny Ronen , Mattan Erez , Stephan Jourdan , Adi Yoaz
IPC分类号： G06F9/00 , G06F9/44
CPC分类号： G06F9/3861 , G06F9/3848
摘要： Methods and apparatus for restoring a meta predictor system upon detecting a branch or binary misprediction, are disclosed. An example apparatus may include a base misprediction history register to store a set of misprediction history values each indicating whether a previous branch prediction taken by a previous branch instruction was predicted correctly or incorrectly. The apparatus may comprise a meta predictor to detect a branch misprediction of a current branch prediction based at least in part on an output of the base misprediction history register. The meta predictor may restore the base misprediction history register based on the detecting of the branch misprediction. Additional apparatus, systems, and methods are disclosed.

3. 发明申请

US20050132138A1 Memory cache bank prediction 失效
公开(公告)号：US20050132138A1
公开(公告)日：2005-06-16
申请号：US11045528
申请日：2005-01-28
申请人： Adi Yoaz , Ronny Ronen , Lihu Rappoport , Mattan Erez , Stephan Jourdan , Bob Valentine
发明人： Adi Yoaz , Ronny Ronen , Lihu Rappoport , Mattan Erez , Stephan Jourdan , Bob Valentine
IPC分类号： G06F9/38 , G06F12/08 , G06F12/00
CPC分类号： G06F9/3885 , G06F9/3824 , G06F9/3832 , G06F9/3836 , G06F12/0846
摘要： A memory cache bank prediction unit is provided for use in a processor having a plurality of memory cache banks. The memory cache bank prediction unit has an input port that receives an instruction. The memory cache bank prediction unit also has an evaluation unit, coupled to the input port, that predicts which of the plurality of memory cache banks is associated with the instruction.

4. 发明授权

US07644236B2 Memory cache bank prediction 失效
标题翻译：内存缓存库预测
公开(公告)号：US07644236B2
公开(公告)日：2010-01-05
申请号：US11045528
申请日：2005-01-28
申请人： Adi Yoaz , Ronny Ronen , Lihu Rappoport , Mattan Erez , Stephan J. Jourdan , Bob Valentine
发明人： Adi Yoaz , Ronny Ronen , Lihu Rappoport , Mattan Erez , Stephan J. Jourdan , Bob Valentine
IPC分类号： G06F12/00
CPC分类号： G06F9/3885 , G06F9/3824 , G06F9/3832 , G06F9/3836 , G06F12/0846
摘要： A memory cache bank prediction unit is provided for use in a processor having a plurality of memory cache banks. The memory cache bank prediction unit has an input port that receives an instruction. The memory cache bank prediction unit also has an evaluation unit, coupled to the input port, that predicts which of the plurality of memory cache banks is associated with the instruction.
摘要翻译：提供了一种用于具有多个存储器高速缓存组的处理器中的存储器高速缓存组预测单元。存储器缓存库预测单元具有接收指令的输入端口。存储器缓存库预测单元还具有耦合到输入端口的评估单元，该评估单元预测多个存储器高速缓冲存储体中的哪一个与该指令相关联。

5. 发明授权

US06880063B2 Memory cache bank prediction 有权
标题翻译：内存缓存库预测
公开(公告)号：US06880063B2
公开(公告)日：2005-04-12
申请号：US10755017
申请日：2004-01-09
申请人： Adi Yoaz , Ronny Ronen , Lihu Rappoport , Mattan Erez , Stephan J. Jourdan , Bob Valentine
发明人： Adi Yoaz , Ronny Ronen , Lihu Rappoport , Mattan Erez , Stephan J. Jourdan , Bob Valentine
IPC分类号： G06F9/38 , G06F12/08
CPC分类号： G06F9/3885 , G06F9/3824 , G06F9/3832 , G06F9/3836 , G06F12/0846
摘要： A memory cache bank prediction unit is provided for use in a processor having a plurality of memory cache banks. The memory cache bank prediction unit has an input port that receives an instruction. The memory cache bank prediction unit also has an evaluation unit, coupled to the input port, that predicts which of the plurality of memory cache banks is associated with the instruction.
摘要翻译：提供了一种用于具有多个存储器高速缓存组的处理器中的存储器高速缓存组预测单元。存储器缓存库预测单元具有接收指令的输入端口。存储器缓存库预测单元还具有耦合到输入端口的评估单元，该评估单元预测多个存储器高速缓冲存储体中的哪一个与该指令相关联。

6. 发明授权

US08285976B2 Method and apparatus for predicting branches using a meta predictor 有权
标题翻译：使用元预测器预测分支的方法和装置
公开(公告)号：US08285976B2
公开(公告)日：2012-10-09
申请号：US09749405
申请日：2000-12-28
申请人： Stephan J. Jourdan , Adi Yoaz , Mattan Erez , Ronny Ronen
发明人： Stephan J. Jourdan , Adi Yoaz , Mattan Erez , Ronny Ronen
IPC分类号： G06F9/00 , G06F9/44
CPC分类号： G06F9/3861 , G06F9/3848
摘要： A branch predicting apparatus is disclosed that reduces branch mispredictions in a processor. The branch prediction apparatus includes a base misprediction history register. The branch prediction apparatus includes a meta predictor that receives an index value and a branch prediction to generate a misprediction value in accordance with the base misprediction history register. The branch prediction apparatus also includes a logic gate that receives the branch prediction and the misprediction value to generate a final prediction. The final prediction may be used to predict whether a branch is taken or not taken.
摘要翻译：公开了一种分支预测装置，其减少处理器中的分支错误预测。分支预测装置包括基本错误预测历史寄存器。分支预测装置包括元预测器，其接收索引值和分支预测，以根据基本错误预测历史寄存器生成错误预测值。分支预测装置还包括接收分支预测和误预测值以产生最终预测的逻辑门。最终预测可用于预测是否采取分支。

7. 发明授权

US06697932B1 System and method for early resolution of low confidence branches and safe data cache accesses 失效
标题翻译：用于早期解决低置信度分支和安全数据高速缓存访问的系统和方法
公开(公告)号：US06697932B1
公开(公告)日：2004-02-24
申请号：US09475645
申请日：1999-12-30
申请人： Adi Yoaz , Mattan Erez , Ronny Ronen
发明人： Adi Yoaz , Mattan Erez , Ronny Ronen
IPC分类号： G06F938
CPC分类号： G06F9/3838 , G06F9/3824 , G06F9/3836 , G06F9/3844 , G06F9/3857 , G06F9/3861
摘要： The present invention is directed to a computer system and method for early resolution of a set of critical instructions. The computer system may include a scoreboard, a scheduling window and a confidence predictor. The scoreboard may include a set of reservation stations. Each one of the set of reservation stations may correspond to one of a set of decoded instructions. Each one of the set of reservation stations may have a priority field. The scheduling window may maintain the scoreboard, wherein if one of the set of decoded instructions is one of the set of critical instructions, the scheduling window may mark the priority field corresponding to the particular one of the set of decoded instructions and also may find and mark the priority field of each of a set of base instructions upon which the particular one of the set of decoded instructions depends. The confidence predictor may also be used to predict whether one of the set of decoded instructions is one of the set of critical instructions.
摘要翻译：本发明涉及一种用于早期解决一组关键指令的计算机系统和方法。计算机系统可以包括记分板，调度窗口和置信度预测器。记分板可以包括一组保留站。该组保留站中的每一个可对应于一组解码指令中的一个。该组保留站中的每一个可以具有优先级字段。调度窗口可以维持记分板，其中如果解码指令集合中的一个是关键指令集合中的一个，则调度窗口可以标记与该组解码指令中的特定一个对应的优先级字段，并且还可以找到和标记所述一组解码指令中的特定一个所依赖的一组基本指令中的每一个的优先级字段。置信度预测器还可以用于预测该组解码指令中的一个是否是该组关键指令之一。

8. 发明授权

US06757816B1 Fast branch misprediction recovery method and system 有权
标题翻译：快速分支错误预测恢复方法和系统
公开(公告)号：US06757816B1
公开(公告)日：2004-06-29
申请号：US09476227
申请日：1999-12-30
申请人： Adi Yoaz , Gregory Pribush , Freddy Gabby , Mattan Erez , Ronny Ronen
发明人： Adi Yoaz , Gregory Pribush , Freddy Gabby , Mattan Erez , Ronny Ronen
IPC分类号： G06F900
CPC分类号： G06F9/3861 , G06F9/30058 , G06F9/3804 , G06F9/384 , G06F9/3842 , G06F9/3844
摘要： A system and method for recovering from mispredicted paths in pipelined computer architectures. Targets within an instruction window exhibit spatial locality. To exploit this property, a mechanism detects the branch target within the instruction window. A second process eliminates the need for full renaming and re-execution of mispredicted paths by handling a dependency chain of instructions.
摘要翻译：一种用于在流水线计算机体系结构中从错误预测路径中恢复的系统和方法。指令窗口内的目标表现出空间局部性。为了利用此属性，机制将在指令窗口中检测分支目标。第二个过程消除了通过处理指令的依赖关系链来完全重命名和重新执行错误的路径的需要。

9. 发明授权

US06694421B2 Cache memory bank access prediction 有权
标题翻译：缓存存储器存取预测
公开(公告)号：US06694421B2
公开(公告)日：2004-02-17
申请号：US09474381
申请日：1999-12-29
申请人： Adi Yoaz , Ronny Ronen , Lihu Rappoport , Mattan Erez , Stephan J. Jourdan , Bob Valentine
发明人： Adi Yoaz , Ronny Ronen , Lihu Rappoport , Mattan Erez , Stephan J. Jourdan , Bob Valentine
IPC分类号： G06F1208
CPC分类号： G06F9/3885 , G06F9/3824 , G06F9/3832 , G06F9/3836 , G06F12/0846
摘要： A cache bank prediction unit is provided for use in a processor having a plurality of cache memory banks. The cache bank prediction unit has an input port that receives an instruction. The cache bank prediction unit also has an evaluation unit, coupled to the input port, that predicts which of the plurality of cache banks is associated with the instruction.
摘要翻译：提供了一种用于具有多个高速缓存存储体的处理器中的高速缓存存储体预测单元。高速缓存库预测单元具有接收指令的输入端口。高速缓存库预测单元还具有耦合到输入端口的评估单元，该评估单元预测多个高速缓存组中的哪一个与该指令相关联。

10. 发明授权

US08959292B1 Atomic memory access hardware implementations 有权
标题翻译：原子存储器访问硬件实现
公开(公告)号：US08959292B1
公开(公告)日：2015-02-17
申请号：US11643026
申请日：2006-12-20
申请人： Jung Ho Ahn , Mattan Erez , William J. Dally
发明人： Jung Ho Ahn , Mattan Erez , William J. Dally
IPC分类号： G06F12/00 , G06F9/38 , G06F3/06
CPC分类号： G06F3/067 , G06F9/3895 , G06F12/0802
摘要： Atomic memory access requests are handled using a variety of systems and methods. According to one example method, a data-processing circuit having an address-request generator that issues requests to a common memory implements a method of processing the requests using a memory-access intervention circuit coupled between the generator and the common memory. The method identifies a current atomic-memory access request from a plurality of memory access requests. A data set is stored that corresponds to the current atomic-memory access request in a data storage circuit within the intervention circuit. It is determined whether the current atomic-memory access request corresponds to at least one previously-stored atomic-memory access request. In response to determining correspondence, the current request is implemented by retrieving data from the common memory. The data is modified in response to the current request and at least one other access request in the memory-access intervention circuit.
摘要翻译：使用各种系统和方法来处理原子存储器访问请求。根据一个示例性方法，具有向公共存储器发出请求的地址请求生成器的数据处理电路实现使用耦合在发生器和公共存储器之间的存储器访问干预电路来处理请求的方法。该方法从多个存储器访问请求中识别当前的原子存储器访问请求。存储对应于干预电路内的数据存储电路中的当前原子存储器访问请求的数据集。确定当前的原子存储器访问请求是否对应于至少一个先前存储的原子存储器访问请求。响应于确定对应关系，通过从公共存储器检索数据来实现当前请求。响应于当前请求和存储器访问干预电路中的至少一个其他访问请求修改数据。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式