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1. 发明授权

US08959292B1 Atomic memory access hardware implementations 有权
标题翻译：原子存储器访问硬件实现
公开(公告)号：US08959292B1
公开(公告)日：2015-02-17
申请号：US11643026
申请日：2006-12-20
申请人： Jung Ho Ahn , Mattan Erez , William J. Dally
发明人： Jung Ho Ahn , Mattan Erez , William J. Dally
IPC分类号： G06F12/00 , G06F9/38 , G06F3/06
CPC分类号： G06F3/067 , G06F9/3895 , G06F12/0802
摘要： Atomic memory access requests are handled using a variety of systems and methods. According to one example method, a data-processing circuit having an address-request generator that issues requests to a common memory implements a method of processing the requests using a memory-access intervention circuit coupled between the generator and the common memory. The method identifies a current atomic-memory access request from a plurality of memory access requests. A data set is stored that corresponds to the current atomic-memory access request in a data storage circuit within the intervention circuit. It is determined whether the current atomic-memory access request corresponds to at least one previously-stored atomic-memory access request. In response to determining correspondence, the current request is implemented by retrieving data from the common memory. The data is modified in response to the current request and at least one other access request in the memory-access intervention circuit.
摘要翻译：使用各种系统和方法来处理原子存储器访问请求。根据一个示例性方法，具有向公共存储器发出请求的地址请求生成器的数据处理电路实现使用耦合在发生器和公共存储器之间的存储器访问干预电路来处理请求的方法。该方法从多个存储器访问请求中识别当前的原子存储器访问请求。存储对应于干预电路内的数据存储电路中的当前原子存储器访问请求的数据集。确定当前的原子存储器访问请求是否对应于至少一个先前存储的原子存储器访问请求。响应于确定对应关系，通过从公共存储器检索数据来实现当前请求。响应于当前请求和存储器访问干预电路中的至少一个其他访问请求修改数据。

2. 发明授权

US08059443B2 Three-dimensional memory module architectures 有权
标题翻译：三维内存模块架构
公开(公告)号：US08059443B2
公开(公告)日：2011-11-15
申请号：US11975963
申请日：2007-10-23
申请人： Moray McLaren , Jung Ho Ahn , Alan Lynn Davis , Nathan Lorenzo Binkert , Norman Paul Jouppi
发明人： Moray McLaren , Jung Ho Ahn , Alan Lynn Davis , Nathan Lorenzo Binkert , Norman Paul Jouppi
IPC分类号： G11C13/04
CPC分类号： G11C5/04 , G11C5/02 , G11C5/025 , G11C13/04 , G11C2211/4016 , G11C2213/71 , H01L25/0657 , H01L25/18 , H01L2225/06534 , H01L2225/06541 , H01L2225/06565 , H01L2924/0002 , H01L2924/15311 , H01L2924/00
摘要： Various embodiments of the present invention are directed to stacked memory modules. In one embodiment of the present invention, a memory module comprises at least one memory-controller layer stacked with at least one memory layer. Fine pitched through vias (e.g., through silicon vias) extend approximately perpendicular to a surface of the at least one memory controller through the stack providing electronic communication between the at least one memory controller and the at least one memory layers. Additionally, the memory-controller layer includes at least one external interface configured to transmit data to and from the memory module. Furthermore, the memory module can include an optical layer. The optical layer can be included in the stack and has a bus waveguide to transmit data to and from the at least one memory controller. The external interface can be an optical external interface which interfaces with the optical layer.
摘要翻译：本发明的各种实施例涉及堆叠的存储器模块。在本发明的一个实施例中，存储器模块包括至少一个堆叠有至少一个存储器层的存储器 - 控制器层。通过通孔（例如，通过硅通孔）精细地延伸通过堆叠大致垂直于至少一个存储器控制器的表面延伸，从而提供至少一个存储器控制器与至少一个存储器层之间的电子通信。此外，存储器控制器层包括被配置为向存储器模块传送数据和从存储器模块传送数据的至少一个外部接口。此外，存储器模块可以包括光学层。光学层可以被包括在堆叠中并且具有总线波导以将数据传送到至少一个存储器控制器和从至少一个存储器控制器传送数据。外部接口可以是与光学层接口的光学外部接口。

3. 发明申请

US20110069963A1 Optoelectronic Switches Using On-chip Optical Waveguides 有权
标题翻译：使用片上光波导的光电开关
公开(公告)号：US20110069963A1
公开(公告)日：2011-03-24
申请号：US12921768
申请日：2008-03-11
申请人： Moray McLaren , Jung Ho Ahn , Nathan L. Binkert , Alan L. Davis , Norman P. Jouppi
发明人： Moray McLaren , Jung Ho Ahn , Nathan L. Binkert , Alan L. Davis , Norman P. Jouppi
IPC分类号： H04B10/00 , G02B6/35
CPC分类号： G02B6/12007 , G02B6/29338 , G02B6/35 , G02B6/3546 , G02B6/356 , G02F1/3137 , G02F1/3138 , G02F2201/17 , G02F2202/32 , G02F2203/15 , H04Q11/0005 , H04Q11/0066 , H04Q2011/0016 , H04Q2011/0035 , H04Q2011/0058
摘要： Embodiments of the present invention are directed to optoelectronic network switches. In one embodiment, an optoelectronic switch includes a set of roughly parallel input waveguides and a set of roughly parallel output waveguides positioned roughly perpendicular to the input waveguides. Each of the output waveguides crosses the set of input waveguides. The optoelectronic switch includes at least one switch element configured to switch one or more optical signals transmitted on one or more input waveguides onto one or more crossing output waveguides.
摘要翻译：本发明的实施例涉及光电网络交换机。在一个实施例中，光电开关包括一组大致平行的输入波导和大致垂直于输入波导定位的大致平行的输出波导组。每个输出波导穿过该组输入波导。光电开关包括至少一个开关元件，其被配置为将在一个或多个输入波导上传输的一个或多个光信号切换到一个或多个交叉输出波导上。

4. 发明授权

US08938139B2 Optoelectronic switches using on-chip optical waveguides 有权
标题翻译：使用片上光波导的光电开关
公开(公告)号：US08938139B2
公开(公告)日：2015-01-20
申请号：US12921768
申请日：2008-03-11
申请人： Moray McLaren , Jung Ho Ahn , Nathan L. Binkert , Alan L. Davis , Norman Paul Jouppi
发明人： Moray McLaren , Jung Ho Ahn , Nathan L. Binkert , Alan L. Davis , Norman Paul Jouppi
IPC分类号： G02B6/26 , G02B6/12 , G02F1/313 , H04Q11/00 , G02B6/293 , G02B6/35
CPC分类号： G02B6/12007 , G02B6/29338 , G02B6/35 , G02B6/3546 , G02B6/356 , G02F1/3137 , G02F1/3138 , G02F2201/17 , G02F2202/32 , G02F2203/15 , H04Q11/0005 , H04Q11/0066 , H04Q2011/0016 , H04Q2011/0035 , H04Q2011/0058
摘要： Embodiments of the present invention are directed to optoelectronic network switches. In one embodiment, an optoelectronic switch includes a set of roughly parallel input waveguides and a set of roughly parallel output waveguides positioned roughly perpendicular to the input waveguides. Each of the output waveguides crosses the set of input waveguides. The optoelectronic switch includes at least one switch element configured to switch one or more optical signals transmitted on one or more input waveguides onto one or more crossing output waveguides.
摘要翻译：本发明的实施例涉及光电网络交换机。在一个实施例中，光电开关包括一组大致平行的输入波导和大致垂直于输入波导定位的大致平行的输出波导组。每个输出波导穿过该组输入波导。光电开关包括至少一个开关元件，其被配置为将在一个或多个输入波导上传输的一个或多个光信号切换到一个或多个交叉输出波导上。

5. 发明授权

US08924639B2 Independently controllable and reconfigurable virtual memory devices in memory modules that are pin-compatible with standard memory modules 有权
标题翻译：与标准内存模块引脚兼容的内存模块中的独立可控和可重新配置的虚拟内存设备
公开(公告)号：US08924639B2
公开(公告)日：2014-12-30
申请号：US13058048
申请日：2008-08-08
申请人： Jung Ho Ahn , Norman P. Jouppi , Robert S. Schreiber
发明人： Jung Ho Ahn , Norman P. Jouppi , Robert S. Schreiber
IPC分类号： G06F12/00 , G06F12/06 , G11C5/04 , G11C8/12 , G06F13/16
CPC分类号： G11C5/04 , G06F12/06 , G06F12/0646 , G06F13/1684 , G06F2212/1028 , G11C8/12 , Y02D10/13 , Y02D10/14
摘要： Various embodiments of the present invention are directed multi-core memory modules. In one embodiment, a memory module (500) includes memory chips, and a demultiplexer register (502) electronically connected to each of the memory chips and a memory controller. The memory controller groups one or more of the memory chips into at least one virtual memory device in accordance with changing performance and/or energy efficiency needs. The demultiplexer register (502) is configured to receive a command indentifying one of the virtual memory devices and send the command to the memory chips of the identified virtual memory device. In certain embodiments, the memory chips can be dynamic random access memory chips.
摘要翻译：本发明的各种实施例是多核存储器模块。在一个实施例中，存储器模块（500）包括存储器芯片和电连接到每个存储器芯片的解复用器寄存器（502）和存储器控制器。存储器控制器根据改变的性能和/或能量效率需求将一个或多个存储器芯片组合成至少一个虚拟存储器设备。解复用器寄存器（502）被配置为接收识别虚拟存储器设备中的一个并且将命令发送到所识别的虚拟存储器设备的存储器芯片的命令。在某些实施例中，存储器芯片可以是动态随机存取存储器芯片。

6. 发明授权

US08054231B2 Mobile terminal having metal case and antenna structure 有权
标题翻译：具有金属外壳和天线结构的移动终端
公开(公告)号：US08054231B2
公开(公告)日：2011-11-08
申请号：US12419503
申请日：2009-04-07
申请人： Jung Ho Ahn , Yong Jin Kim , Dong Hwan Kim , Jae Ho Lee , Seung Hwan Kim
发明人： Jung Ho Ahn , Yong Jin Kim , Dong Hwan Kim , Jae Ho Lee , Seung Hwan Kim
IPC分类号： H01Q1/24 , H01Q13/10
CPC分类号： H01Q1/243 , H01Q13/106
摘要： A mobile terminal including a metal case and an antenna structure that can exhibit optimum radiation performance is provided. The antenna structure includes an antenna having a radiation unit for transmitting and for receiving electric waves, a Printed Circuit Board (PCB) to which the antenna is mechanically coupled at one surface thereof and having a power supply unit electrically coupled to the radiation unit, and a case constructed using a metal material within which the PCB is disposed, wherein the case has at least one slot formed in a surface thereof opposite to the surface to which the PCB is fastened and adjacent to the radiation unit.
摘要翻译：提供一种包括金属外壳和能够呈现最佳辐射性能的天线结构的移动终端。天线结构包括具有用于发送和接收电波的辐射单元的天线，天线在其一个表面机械耦合并具有电耦合到辐射单元的电源单元的印刷电路板（PCB），以及使用其中布置有PCB的金属材料构造的壳体，其中所述壳体具有形成在其与所述PCB被紧固并邻近所述辐射单元的表面相对的表面中的至少一个槽。

7. 发明授权

US07528455B2 Narrow width metal oxide semiconductor transistor 有权
标题翻译：窄宽度的金属氧化物半导体晶体管
公开(公告)号：US07528455B2
公开(公告)日：2009-05-05
申请号：US11646727
申请日：2006-12-27
申请人： Jung Ho Ahn
发明人： Jung Ho Ahn
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L27/10 , H01L29/739 , H01L29/73
CPC分类号： H01L29/41758 , H01L29/78
摘要： Disclosed is a semiconductor transistor for enhancing performance of PMOS and NMOS transistors, particularly current driving performance, while reducing a narrow width effect. A narrow width MOS transistor includes: a channel of which width is W0 and length is L0; an active area including source and drain areas formed at both sides with the channel as a center; a gate insulating layer formed on the channel; a gate conductor formed on the gate insulating layer and intersecting the active area; a first additional active area of width is larger than that W0 of the channel as an active area added to the source area; and a second additional active area of width is larger than that W0 of the channel as an active area added to the drain area. When the structure of the transistor having the additional active areas is applied to NMOS and PMOS transistors, a driving current is represented as 107.27% and 103.31%, respectively. Accordingly, the driving currents of both PMOS and NMOS transistors are enhanced.
摘要翻译：公开了一种用于增强PMOS和NMOS晶体管的性能的半导体晶体管，特别是电流驱动性能，同时减小窄宽度效应。窄宽度的MOS晶体管包括：宽度为W0且长度为L0的沟道; 一个有效区域，包括以通道为中心形成在两侧的源区和漏区; 形成在所述通道上的栅极绝缘层; 栅极导体，形成在栅极绝缘层上并与有源区相交; 宽度的第一附加有效区域大于作为添加到源区域的活动区域的信道的W0; 并且宽度的第二附加有源区域大于作为添加到漏极区域的有源区域的沟道的W0。当具有附加有源区的晶体管的结构被施加到NMOS和PMOS晶体管时，驱动电流分别表示为107.27％和103.31％。因此，增加了PMOS和NMOS晶体管的驱动电流。

8. 发明授权

US08543005B2 Intentionally skewed optical clock signal distribution 有权
标题翻译：有意偏斜的光时钟信号分布
公开(公告)号：US08543005B2
公开(公告)日：2013-09-24
申请号：US12990494
申请日：2008-04-30
申请人： Nathan L. Binkert , Norman P. Jouppi , Robert S. Schreiber , Jung Ho Ahn
发明人： Nathan L. Binkert , Norman P. Jouppi , Robert S. Schreiber , Jung Ho Ahn
IPC分类号： H04B10/00
CPC分类号： H04B10/1121 , G06F1/105
摘要： Embodiments of the present invention relate to systems and methods for distributing an intentionally skewed optical-clock signal to nodes of a source synchronous computer system. In one system embodiment, a source synchronous system comprises a waveguide, an optical-system clock optically coupled to the waveguide, and a number of nodes optically coupled to the waveguide. The optical-system clock generates and injects a master optical-clock signal into the waveguide. The master optical-clock signal acquiring a skew as it passes between nodes. Each node extracts a portion of the master optical-clock signal and processes optical signals using the portion of the master optical-clock signal having a different skew for the respective extracting node.
摘要翻译：本发明的实施例涉及将故意偏斜的光时钟信号分配给源同步计算机系统的节点的系统和方法。在一个系统实施例中，源同步系统包括波导，光学耦合到波导的光学系统时钟以及光耦合到波导的多个节点。光学系统时钟产生并将主光时钟信号注入到波导中。主光时钟信号在节点之间通过时获取偏斜。每个节点提取主光时钟信号的一部分，并使用对于相应提取节点具有不同偏斜的主光学时钟信号的部分来处理光信号。

9. 发明申请

US20090103929A1 Synchronous optical bus providing communication between computer system components 有权
标题翻译：提供计算机系统组件之间的通信的同步光学总线
公开(公告)号：US20090103929A1
公开(公告)日：2009-04-23
申请号：US11977369
申请日：2007-10-23
申请人： Nathan Binkert , Norm Jouppi , Robert Schreiber , Jung Ho Ahn , Moray McLaren
发明人： Nathan Binkert , Norm Jouppi , Robert Schreiber , Jung Ho Ahn , Moray McLaren
IPC分类号： H04B10/00
CPC分类号： H04B10/278 , H04B10/801
摘要： A synchronous optical bus system for communication between computer system components is described. In one example, the optical bus system is used for communication between a memory controller and memory devices optically coupled to an optical interconnect. Optical bus interface units couple the components to the optical interconnect and are arranged on the optical interconnect in order that a sum of an optical path length from a controller component to each computer system component and from each computer system component to the controller component is the same for all the coupled computer system components. A synchronous protocol is used for communication between the components.
摘要翻译：描述了用于计算机系统组件之间的通信的同步光总线系统。在一个示例中，光总线系统用于存储器控制器与光学互连光耦合的存储器件之间的通信。光总线接口单元将组件耦合到光互连，并且布置在光互连上，以便从控制器组件到每个计算机系统组件以及从每个计算机系统组件到控制器组件的光路长度之和相等适用于所有耦合的计算机系统组件。同步协议用于组件之间的通信。

10. 发明申请

US20070152281A1 NARROW WIDTH METAL OXIDE SEMICONDUCTOR TRANSISTOR HAVING A SUPPLEMENTAL GATE CONDUCTOR PATTERN 审中-公开
标题翻译：具有补充栅极导体图案的纳米宽金属氧化物半导体晶体管
公开(公告)号：US20070152281A1
公开(公告)日：2007-07-05
申请号：US11616255
申请日：2006-12-26
申请人： Jung Ho Ahn
发明人： Jung Ho Ahn
IPC分类号： H01L29/76
CPC分类号： H01L29/4238 , H01L29/78
摘要： A MOS transistor may include at least one of: a channel having a width W0 and a length L0; an active area with a channel between a source area and a drain area; a gate insulating layer formed over a channel; and/or a gate conductor formed over a gate insulating layer and intersecting the active area. In embodiments, a gate conductor may include at least one of: a connection pattern formed with a gate contact hole which electrically connects the gate conductor to the outside; an additional pattern connected to a connection pattern and positioned in parallel with both source and drain areas while being spaced apart from the active area at a certain distance; and a channel pattern connected to an additional pattern in the shape of a T and defining the length of a channel.
摘要翻译： MOS晶体管可以包括以下至少一个：具有宽度W 0和长度L 0的沟道; 具有在源区域和漏极区域之间的通道的有源区域; 形成在通道上的栅极绝缘层; 和/或形成在栅极绝缘层上并与有源区相交的栅极导体。在实施例中，栅极导体可以包括以下中的至少一个：形成有栅极接触孔的连接图案，其将栅极导体电连接到外部; 连接到连接图案并且与源极和漏极区域平行定位的附加图案，同时在一定距离处与有源区域间隔开; 以及连接到T形状的附加图案并定义通道的长度的通道图案。

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