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    • 1. 发明授权
    • Magnetoresistive (MR) sensor element with enhanced resistivity sensitivity and enhanced magnetic exchange bias
    • 具有增强的电阻率敏感性和增强的磁交换偏置的磁阻(MR)传感器元件
    • US06291087B1
    • 2001-09-18
    • US09336786
    • 1999-06-21
    • Rongfu XiaoChyu-Jiuh TorngKochan JuCheng HorngJei-Wei Chang
    • Rongfu XiaoChyu-Jiuh TorngKochan JuCheng HorngJei-Wei Chang
    • G11B566
    • B82Y25/00B82Y10/00G11B5/3163G11B5/3903G11B5/3954G11B5/66G11B2005/3996Y10S428/90Y10T29/49034Y10T29/49044Y10T29/49046Y10T428/1121
    • A method for forming a magnetoresistive (MR) sensor element, and a magnetoresistive sensor element fabricated in accord with the method. There is first provided a substrate. There is then formed over the substrate a magnetoresistive (MR) layer comprising: (1) a bulk layer of the magnetoresistive (MR) layer formed of a first magnetoresistive (MR) material optimized to provide an enhanced magnetoresistive (MR) resistivity sensitivity of the magnetoresistive (MR) layer; and (2) a surface layer of the magnetoresistive (MR) layer formed of a second magnetoresistive (MR) material optimized to provide an enhanced magnetic exchange bias when forming a magnetic exchange bias layer upon the surface layer of the magnetoresistive (MR) layer. Finally, there is then formed upon the surface layer of the magnetoresistive (MR) layer the magnetic exchange bias layer. The method contemplates an magnetoresistive (MR) sensor element fabricated in accord with the method. The method is particularly useful for forming a dual stripe magnetoresistive (DSMR) sensor element by employing a single magnetic exchange bias material with separate blocking temperatures.
    • 一种用于形成磁阻(MR)传感器元件的方法和根据该方法制造的磁阻传感器元件。 首先提供基板。 然后在衬底上形成磁阻(MR)层,包括:(1)由第一磁阻(MR)材料形成的磁阻(MR)层的体层,其被优化以提供增强的磁阻(MR)电阻率敏感性 磁阻(MR)层; 和(2)由第二磁阻(MR)材料形成的磁阻(MR)层的表面层,其优化以在磁阻(MR)层的表面层上形成磁交换偏置层时提供增强的磁交换偏压。 最后,在磁阻(MR)层的表面层上形成磁交换偏置层。 该方法考虑了根据该方法制造的磁阻(MR)传感器元件。 该方法对于通过采用具有单独的阻挡温度的单个磁交换偏压材料形成双重磁阻(DSMR)传感器元件特别有用。
    • 2. 发明授权
    • Multiple thermal annealing method for forming antiferromagnetic exchange biased magnetoresistive (MR) sensor element
    • 用于形成反铁磁交换偏磁电阻(MR)传感器元件的多重热退火方法
    • US06322640B1
    • 2001-11-27
    • US09489969
    • 2000-01-24
    • Rongfu XiaoChyu-Jiuh TorngHui-Chuan WangJei-Wei ChangCherng-Chyi HanKochan Ju
    • Rongfu XiaoChyu-Jiuh TorngHui-Chuan WangJei-Wei ChangCherng-Chyi HanKochan Ju
    • H01F4100
    • B82Y25/00B82Y40/00H01F10/3268H01F41/302H01L43/12Y10T29/49034
    • A method for forming a magnetically biased magnetoresistive (MR) layer. There is first provided a substrate. There is then formed over the substrate a ferromagnetic magnetoresistive (MR) material layer. There is then forming contacting the ferromagnetic magnetoresistive (MR) material layer a magnetic material layer formed of a first crystalline phase, where the magnetic material layer is formed of a crystalline multiphasic magnetic material having the first crystalline phase which does not appreciably antiferromagnetically exchange couple with the ferromagnetic magnetoresistive (MR) material layer and a second crystalline phase which does appreciably antiferromagnetically exchange couple with the ferromagnetic magnetoresistive (MR) material layer. There is then annealed thermally while employing a first thermal annealing method employing an extrinsic magnetic bias field the magnetic material layer formed of the first crystalline phase to form a magnetically aligned magnetic material layer formed of the first crystalline phase. Finally, there is then annealed thermally while employing a second thermal annealing method without employing an extrinsic magnetic bias field the magnetically aligned magnetic material layer formed of the first crystalline phase to form an antiferromagnetically coupled magnetically aligned magnetic material layer formed of the second crystalline phase. The method may be employed for forming non-parallel antiferromagnetically biased multiple magnetoresistive (MR) layer magnetoresistive (MR) sensor elements while employing a single antiferromagnetic material.
    • 一种用于形成磁偏置磁阻(MR)层的方法。 首先提供基板。 然后在衬底上形成铁磁磁阻(MR)材料层。 然后,形成使铁磁性磁阻(MR)材料层与由第一结晶相形成的磁性材料层接触,其中,磁性材料层由结晶多相磁性材料形成,该结晶多相磁性材料具有不明显地反铁磁性交换耦合的第一结晶相 铁磁磁阻(MR)材料层和第二结晶相,其明显地与铁磁性磁阻(MR)材料层反铁磁交换耦合。 然后在使用由第一结晶相形成的磁性材料层的外部磁偏置场的第一热退火方法进行退火,形成由第一结晶相形成的磁性取向的磁性材料层。 最后,在不使用由第一结晶相形成的磁性取向的磁性材料层的外部磁偏置场的情况下,采用第二热退火方法进行退火,形成由第二结晶相形成的反铁磁耦合的磁性取向的磁性材料层。 该方法可以用于在使用单个反铁磁材料的同时形成非平行的反铁磁偏振多磁阻(MR)层磁阻(MR)传感器元件。
    • 5. 发明授权
    • Method of MRAM fabrication with zero electrical shorting
    • 零电气短路的MRAM制造方法
    • US07936027B2
    • 2011-05-03
    • US12006889
    • 2008-01-07
    • Rongfu XiaoChyu-Jiuh TorngTom ZhongWitold Kula
    • Rongfu XiaoChyu-Jiuh TorngTom ZhongWitold Kula
    • G11C11/02
    • H01L43/12H01L43/08
    • An MTJ cell without footings and free from electrical short-circuits across a tunneling barrier layer is formed by using a Ta hard mask layer and a combination of etches. A first etch patterns the Ta hard mask, while a second etch uses O2 applied in a single high power process at two successive different power levels. A first power level of between approximately 200 W and 500 W removes BARC, photoresist and Ta residue from the first etch, the second power level, between approximately 400 W and 600 W continues an etch of the stack layers and forms a protective oxide around the etched sides of the stack. Finally, an etch using a carbon, hydrogen and oxygen gas completes the etch while the oxide layer protects the cell from short-circuits across the lateral edges of the barrier layer.
    • 通过使用Ta硬掩模层和蚀刻的组合,形成没有底脚并且穿过隧道势垒层的电短路的MTJ电池。 第一蚀刻图案Ta硬掩模,而第二蚀刻使用在两个连续的不同功率水平下在单个高功率过程中施加的O2。 在大约200W至500W之间的第一功率电平从第一蚀刻去除BARC,光致抗蚀剂和Ta残留物,第二功率电平在大约400W至600W之间,继续蚀刻叠层,并在其周围形成保护氧化物 蚀刻边的堆叠。 最后,使用碳,氢和氧气的蚀刻完成了蚀刻,而氧化物层保护电池免受横跨阻挡层的侧边缘的短路。
    • 7. 发明申请
    • Method of MRAM fabrication with zero electrical shorting
    • 零电气短路的MRAM制造方法
    • US20090173977A1
    • 2009-07-09
    • US12006889
    • 2008-01-07
    • Rongfu XiaoChyu-Jiuh TorngTom ZhongWitold Kula
    • Rongfu XiaoChyu-Jiuh TorngTom ZhongWitold Kula
    • H01L43/00H01L29/82H01L43/12H01L21/467
    • H01L43/12H01L43/08
    • An MTJ cell without footings and free from electrical short-circuits across a tunneling barrier layer is formed by using a Ta hard mask layer and a combination of etches. A first etch patterns the Ta hard mask, while a second etch uses O2 applied in a single high power process at two successive different power levels. A first power level of between approximately 200 W and 500 W removes BARC, photoresist and Ta residue from the first etch, the second power level, between approximately 400 W and 600 W continues an etch of the stack layers and forms a protective oxide around the etched sides of the stack. Finally, an etch using a carbon, hydrogen and oxygen gas completes the etch while the oxide layer protects the cell from short-circuits across the lateral edges of the barrier layer.
    • 通过使用Ta硬掩模层和蚀刻的组合,形成没有底脚并且穿过隧道势垒层的电短路的MTJ电池。 第一蚀刻图案Ta硬掩模,而第二蚀刻使用在两个连续的不同功率水平下在单个高功率过程中施加的O2。 在大约200W至500W之间的第一功率电平从第一蚀刻去除BARC,光致抗蚀剂和Ta残留物,第二功率电平在大约400W至600W之间,继续蚀刻叠层,并在其周围形成保护氧化物 蚀刻边的堆叠。 最后,使用碳,氢和氧气的蚀刻完成了蚀刻,而氧化物层保护电池免受横跨阻挡层的侧边缘的短路。
    • 8. 发明授权
    • High density spin-transfer torque MRAM process
    • 高密度自旋转移力矩MRAM工艺
    • US08183061B2
    • 2012-05-22
    • US12931648
    • 2011-02-07
    • Tom ZhongChyu-Jiuh TorngRongfu XiaoAdam ZhongWai-Ming Johnson KanDaniel Liu
    • Tom ZhongChyu-Jiuh TorngRongfu XiaoAdam ZhongWai-Ming Johnson KanDaniel Liu
    • H01L21/441
    • H01L27/228H01L43/12
    • A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden.
    • 公开了一种STT-MRAM集成方案,其中通过在CMOS着陆焊盘,接触和覆盖VAC的金属(VAM)焊盘上形成中间通孔接触(VAC)来简化MTJ和CMOS金属之间的连接,以及MTJ 在VAM上。 执行双镶嵌工艺,通过设备区域中的VAC / VAM / MTJ堆叠将BIT线金属连接到CMOS着陆焊盘,并通过设备区域外的BIT连接通孔将BIT线连接焊盘连接到CMOS连接焊盘。 VAM焊盘是由Ta,TaN或用作扩散阻挡层的其它导体制成的单层或复合材料,具有用于MTJ形成的高度光滑的表面,并且在化学机械抛光工艺期间提供了与补充介电材料的优异选择性。 每个VAC为500至3000埃厚,以最小化额外的电路电阻并最小化蚀刻负担。
    • 9. 发明授权
    • Method of magnetic tunneling layer processes for spin-transfer torque MRAM
    • 旋转转矩MRAM的磁隧道层工艺方法
    • US08133745B2
    • 2012-03-13
    • US11975045
    • 2007-10-17
    • Tom ZhongRongfu XiaoChyu-Jiuh TorngAdam Zhong
    • Tom ZhongRongfu XiaoChyu-Jiuh TorngAdam Zhong
    • H01L21/00
    • H01L43/12B82Y10/00H01L27/228
    • A method for forming a MTJ in a STT-MRAM is disclosed in which the easy-axis CD is determined independently of the hard-axis CD. One approach involves two photolithography steps and two etch steps to form a post in a hard mask which is transferred through a MTJ stack of layers by a third etch process. Optionally, the third etch may stop on the tunnel barrier or in the free layer. A second embodiment involves forming a first parallel line pattern on a hard mask layer and transferring the line pattern through the MTJ stack with a first etch step. A planar insulation layer is formed adjacent to the sidewalls in the line pattern and then a second parallel line pattern is formed which is transferred by a second etch through the MTJ stack to form a post pattern. Etch end point may be controlled independently for hard-axis and easy-axis dimensions.
    • 公开了一种用于在STT-MRAM中形成MTJ的方法,其中容易轴CD独立于硬轴CD来确定。 一种方法涉及两个光刻步骤和两个蚀刻步骤,以在通过第三蚀刻工艺通过MTJ叠层堆叠的硬掩模中形成柱。 可选地,第三蚀刻可以在隧道势垒上或在自由层中停止。 第二实施例涉及在硬掩模层上形成第一平行线图案,并通过第一蚀刻步骤通过MTJ堆叠传送线图案。 平面绝缘层与线图案中的侧壁相邻地形成,然后形成第二平行线图案,其通过第二次蚀刻通过MTJ叠层转印以形成柱形图案。 蚀刻终点可以独立控制硬轴和易轴尺寸。