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1. 发明授权

US5446845A Steering logic to directly connect devices having different data word widths 失效
标题翻译：转向逻辑直接连接具有不同数据字宽度的设备
公开(公告)号：US5446845A
公开(公告)日：1995-08-29
申请号：US123821
申请日：1993-09-20
申请人： Ronald X. Arroyo , William E. Burky , Tricia A. Gruwell , Joaquin Hinojosa
发明人： Ronald X. Arroyo , William E. Burky , Tricia A. Gruwell , Joaquin Hinojosa
IPC分类号： G06F13/40
CPC分类号： G06F13/4018
摘要： Data bus steering logic routes data between various byte lanes of the system bus. Additionally, control signals are provided which allow the connected device and the steering logic to communicate and respond to requests made by the CPU. The steering logic provides a path between the attached device and the byte lanes of the system bus, to which the device is not directly connected. During load and store operations data is transferred via the steering logic and directly between the device and CPU on to the portion of the system bus that it is directly connected to. The steering logic includes a multiplexer, latch, buffer, driver and the like for each lane of data on the system bus. For example, if the system bus is 64 bits wide and a 32 bit device is connected to one-half of the bus, the steering logic will provide a path from the 32 bit device to the other 32 bits of the system bus not directly connected to the device. Thus, during a 64 bit load operation, 32 bits are provided through the steering logic and driven on to the bus. The other 32 bits of data are then retrieved and driven on to the system bus by the 32 bit device. In this example, there are two paths provided by the steering logic since a 32 bit device has half the data width of a 64 bit bus. If 8 bit devices were to be connected to a 64 bit bus, then there would be 8 data paths since the 64 bit bus has eight times the data width of an 8 bit device.
摘要翻译：数据总线转向逻辑在系统总线的各个字节通道之间路由数据。此外，提供控制信号，其允许连接的设备和转向逻辑通信并响应由CPU所做的请求。转向逻辑在连接的设备和系统总线的字节通道之间提供路径，设备不直接连接到该路径。在加载和存储操作期间，数据通过转向逻辑直接传输到设备和CPU之间，直接连接到系统总线的部分。转向逻辑包括用于系统总线上的每个数据通道的多路复用器，锁存器，缓冲器，驱动器等。例如，如果系统总线是64位宽，32位器件连接到总线的一半，则转向逻辑将提供从32位器件到未直接连接的系统总线的其他32位的路径到设备。因此，在64位加载操作期间，通过转向逻辑提供32位，并被驱动到总线上。然后通过32位设备检索其他32位数据并将其驱动到系统总线上。在该示例中，由转向逻辑提供的两个路径，因为32位器件具有64位总线的数据宽度的一半。如果将8位器件连接到64位总线，那么将有8条数据通道，因为64位总线是8位器件的数据宽度的8倍。

2. 发明授权

US5502732A Method for testing ECC logic 失效
标题翻译： ECC逻辑测试方法
公开(公告)号：US5502732A
公开(公告)日：1996-03-26
申请号：US123829
申请日：1993-09-20
申请人： Ronald X. Arroyo , William E. Burky , Tricia A. Gruwell , Joaquin Hinojosa
发明人： Ronald X. Arroyo , William E. Burky , Tricia A. Gruwell , Joaquin Hinojosa
IPC分类号： G06F11/10 , G06F11/22 , G06F11/267 , H03M13/01 , H03M13/00
CPC分类号： G11C29/02 , G06F11/2215 , G06F11/2284 , H03M13/01 , G06F11/1044
摘要： A system and method for checking the test logic contained in a computer memory system during POST such that any errors can be determined and made available to the system software prior to beginning processing operations. Single and double bit errors are induced which the ECC logic must identify and correct. The CPU compares the data that is written to memory with the data that is read back. Thus, since it is known that an error occurred, due to the induced error provided by the present invention, identical data will verify that the ECC correction logic is working properly. More specifically, a multiplexer is provided in the data write path which substitutes a constant set of identical bits for the actual data generated by the CPU. ECC bits are generated based on the actual generated test data, rather than the inserted identical bits. The substituted data bits and generated ECC bits are then stored in memory. An error condition is identified when the data and ECC code is read back from memory. The correction logic then corrects the data, in the case of a single bit error, such that the data read by the CPU is the same as the originally generated data.
摘要翻译：一种用于在POST期间检查包含在计算机存储器系统中的测试逻辑的系统和方法，使得可以在开始处理操作之前确定任何错误并使系统软件可用。引起ECC逻辑必须识别和纠正的单位和双位错误。 CPU将写入内存的数据与读回的数据进行比较。因此，由于已知发生错误，由于本发明提供的感应错误，相同的数据将验证ECC校正逻辑是否正常工作。更具体地，在数据写入路径中提供多路复用器，其将由CPU产生的实际数据替换为相同位的常数集合。基于实际产生的测试数据而不是插入的相同位产生ECC位。然后将取代的数据位和生成的ECC位存储在存储器中。当从存储器读取数据和ECC代码时，会识别出错误条件。然后，校正逻辑在单个位错误的情况下校正数据，使得CPU读取的数据与原始生成的数据相同。

3. 发明授权

US09489207B2 Processor and method for partially flushing a dispatched instruction group including a mispredicted branch 有权
标题翻译：用于部分刷新分派指令组的处理器和方法，包括错误预测的分支
公开(公告)号：US09489207B2
公开(公告)日：2016-11-08
申请号：US12423495
申请日：2009-04-14
申请人： William E. Burky , Brian R. Mestan , Dung Q. Nguyen , Balaram Sinharoy , Benjamin W. Stolt
发明人： William E. Burky , Brian R. Mestan , Dung Q. Nguyen , Balaram Sinharoy , Benjamin W. Stolt
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3861 , G06F9/3842 , G06F9/3851 , G06F9/3855 , G06F9/3857
摘要： Mechanisms are provided for partial flush handling with multiple branches per instruction group. The instruction fetch unit sorts instructions into groups. A group may include a floating branch instruction and a boundary branch instruction. For each group of instructions, the instruction sequencing unit creates an entry in a global completion table (GCT), which may also be referred to herein as a group completion table. The instruction sequencing unit uses the GCT to manage completion of instructions within each outstanding group. Because each group may include up to two branches, the instruction sequencing unit may dispatch instructions beyond the first branch, i.e. the floating branch. Therefore, if the floating branch results in a misprediction, the processor performs a partial flush of that group, as well as a flush of every group younger than that group.
摘要翻译：提供了用于部分刷新处理的机制，每个指令组具有多个分支。指令提取单元将指令分组分组。组可以包括浮动分支指令和边界分支指令。对于每组指令，指令排序单元在全局完成表（GCT）中创建条目，其也可以在此被称为组完成表。指令排序单元使用GCT来管理每个优秀组内的指令完成。因为每个组可以包括多达两个分支，所以指令排序单元可以分派指令超出第一分支，即浮动分支。因此，如果浮动分支导致错误预测，则处理器将对该组进行部分刷新，以及每个小于该组的组的刷新。

4. 发明授权

US07971161B2 Apparatus and method for implementing speculative clock gating of digital logic circuits 有权
标题翻译：用于实现数字逻辑电路的推测时钟门控的装置和方法
公开(公告)号：US07971161B2
公开(公告)日：2011-06-28
申请号：US12019718
申请日：2008-01-25
申请人： Bartholomew Blaner , Mary D. Brown , William E. Burky , Todd A. Venton
发明人： Bartholomew Blaner , Mary D. Brown , William E. Burky , Todd A. Venton
IPC分类号： G06F17/50 , G06F1/04
CPC分类号： G06F1/3203 , G06F1/10 , G06F1/3237 , Y02D10/128
摘要： A method for implementing speculative clock gating of digital logic circuits in a multiple stage pipeline design includes generating, in a first pipeline stage n, a valid control signal that is input to a first register in a second pipeline stage n+1, the valid control signal indicative of when an operation is qualified to be performed by the second pipeline stage n+1; and generating, in the first pipeline stage, a speculative valid control signal that is used to gate a clock signal to a plurality of additional registers in the second pipeline stage, wherein the speculative valid control signal is generated using only a subset of a total number of control inputs used in generating the valid control signal, and wherein the clock signal is sent directly, without gating, to the first register in the second pipeline stage.
摘要翻译：一种用于在多级流水线设计中实现数字逻辑电路的推测时钟门控的方法包括在第一流水线级n中产生输入到第二流水线级n + 1中的第一寄存器的有效控制信号，有效控制指示操作何时被第二流水线阶段n + 1执行的信号; 以及在第一流水线级中生成用于在第二流水线级中对多个附加寄存器门控时钟信号的推测有效控制信号，其中，仅使用总数的子集来产生推测有效控制信号用于产生有效控制信号的控制输入，并且其中在第二流水线级中将时钟信号直接发送到第一流水线级的第一寄存器。

5. 发明申请

US20100262807A1 Partial Flush Handling with Multiple Branches Per Group 有权
标题翻译：部分冲洗处理与每个分支
公开(公告)号：US20100262807A1
公开(公告)日：2010-10-14
申请号：US12423495
申请日：2009-04-14
申请人： William E. Burky , Brian R. Mestan , Dung Q. Nguyen , Balaram Sinharoy , Benjamin W. Stolt
发明人： William E. Burky , Brian R. Mestan , Dung Q. Nguyen , Balaram Sinharoy , Benjamin W. Stolt
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3861 , G06F9/3842 , G06F9/3851 , G06F9/3855 , G06F9/3857
摘要： Mechanisms are provided for partial flush handling with multiple branches per instruction group. The instruction fetch unit sorts instructions into groups. A group may include a floating branch instruction and a boundary branch instruction. For each group of instructions, the instruction sequencing unit creates an entry in a global completion table (GCT), which may also be referred to herein as a group completion table. The instruction sequencing unit uses the GCT to manage completion of instructions within each outstanding group. Because each group may include up to two branches, the instruction sequencing unit may dispatch instructions beyond the first branch, i.e. the floating branch. Therefore, if the floating branch results in a misprediction, the processor performs a partial flush of that group, as well as a flush of every group younger than that group.
摘要翻译：提供了用于部分刷新处理的机制，每个指令组具有多个分支。指令提取单元将指令分组分组。组可以包括浮动分支指令和边界分支指令。对于每组指令，指令排序单元在全局完成表（GCT）中创建条目，其也可以在此被称为组完成表。指令排序单元使用GCT来管理每个优秀组内的指令完成。因为每个组可以包括多达两个分支，所以指令排序单元可以分派指令超出第一分支，即浮动分支。因此，如果浮动分支导致错误预测，则处理器将对该组进行部分刷新，以及每个小于该组的组的刷新。

6. 发明申请

US20100153700A1 Multicore Processor And Method Of Use That Configures Core Functions Based On Executing Instructions 有权
标题翻译：基于执行指令配置核心功能的多核处理器和使用方法
公开(公告)号：US20100153700A1
公开(公告)日：2010-06-17
申请号：US12335921
申请日：2008-12-16
申请人： Louis B. Capps, JR. , Michael J. Shapiro , Robert H. Bell, JR. , Thomas E. Cook , William E. Burky
发明人： Louis B. Capps, JR. , Michael J. Shapiro , Robert H. Bell, JR. , Thomas E. Cook , William E. Burky
IPC分类号： G06F9/22 , G06F9/318
CPC分类号： G06F9/5061 , G06F9/3842 , G06F9/3851 , G06F9/3887
摘要： A processor having multiple cores coordinates functions performed on the cores to automatically, dynamically and repeatedly reconfigure the cores for optimal performance based on characteristics of currently executing software. A core running a thread detects a multi-core characteristic of the thread and assigns one or more other cores to the thread to dynamically combine the cores into what functionally amounts to a common core for more efficient execution of the thread.
摘要翻译：具有多个核的处理器协调在核上执行的功能，以基于当前执行的软件的特性自动，动态地和重复地重新配置核以获得最佳性能。运行线程的核心检测线程的多核特性，并为线程分配一个或多个其他内核，以将内核动态组合到功能上相当于共同核心的内核，从而更有效地执行线程。

7. 发明申请

US20090063823A1 Method and System for Tracking Instruction Dependency in an Out-of-Order Processor 失效
标题翻译：用于跟踪乱序处理器中的指令依赖性的方法和系统
公开(公告)号：US20090063823A1
公开(公告)日：2009-03-05
申请号：US11847530
申请日：2007-08-30
申请人： William E. Burky , Krishnan Kailas
发明人： William E. Burky , Krishnan Kailas
IPC分类号： G06F9/30
CPC分类号： G06F9/384 , G06F9/3013 , G06F9/3838 , G06F9/3842 , G06F9/3855 , G06F9/3863
摘要： A method of tracking instruction dependency in a processor issuing instructions speculatively includes recording in an instruction dependency array (IDA) an entry for each instruction that indicates data dependencies, if any, upon other active instructions. An output vector read out from the IDA indicates data readiness based upon which instructions have previously been selected for issue. The output vector is used to select and read out issue-ready instructions from an instruction buffer.
摘要翻译：在处理器发布指令中跟踪指令依赖性的方法推测地包括在指令依赖性阵列（IDA）中记录指示其他活动指令的数据依赖性（如果有的话）的每个指令的条目。从IDA读出的输出向量基于先前已经选择了哪些指令进行发布来指示数据准备。输出向量用于从指令缓冲区中选择并读出准备就绪的指令。

8. 发明申请

US20090055631A1 Method And Apparatus For Register Renaming Using Multiple Physical Register Files And Avoiding Associative Search 审中-公开
标题翻译：使用多个物理寄存器文件进行寄存器重命名的方法和装置，并避免关联搜索
公开(公告)号：US20090055631A1
公开(公告)日：2009-02-26
申请号：US12128757
申请日：2008-05-29
申请人： William E. Burky , Krishnan K. Kailas , Balaram Sinharoy
发明人： William E. Burky , Krishnan K. Kailas , Balaram Sinharoy
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/3838 , G06F9/384
摘要： A method for implementing a register renaming scheme for a digital data processor using a plurality of physical register files for supporting out-of-order execution of a plurality of instructions from one or more threads, the method comprising: using a DEF table to store the instruction dependencies between the plurality of instructions using the instruction tags, the DEF table being indexed by a logical register name and including one entry per logical register; using a rename USE table indexed by the instruction tags to store logical-to-physical register mapping information shared by multiple sets of different types of non-architected copies of logical registers used by multiple threads; using a last USE table to transfer data of the multiple sets of different types of non-architected copies of logical registers into the first set of architected registered files, the last USE table being indexed by a physical register name in the second set of rename registered files; and performing the register renaming scheme at the instruction dispatch or wake-up/issue time.
摘要翻译：一种用于使用多个物理寄存器文件来实现用于数字数据处理器的寄存器重命名方案的方法，所述多个物理寄存器文件用于支持来自一个或多个线程的多个指令的无序执行，所述方法包括：使用DEF表来存储使用指令标签的多条指令之间的指令依赖性，DEF表由逻辑寄存器名称索引，并且每个逻辑寄存器包括一个条目; 使用由指令标签索引的重命名USE表来存储由多个线程使用的多组不同类型的非构造的逻辑寄存器副本共享的逻辑到物理寄存器映射信息; 使用最后一个USE表将多组不同类型的非构造的逻辑寄存器副本的数据传输到第一组架构化的注册文件中，最后的USE表由第二组重命名的物理寄存器名称索引文件; 并在指令发送或唤醒/发出时间执行注册重命名方案。

9. 发明申请

US20080127197A1 METHOD AND SYSTEM FOR ON-DEMAND SCRATCH REGISTER RENAMING 审中-公开
标题翻译：用于需求分配寄存器寄存器的方法和系统
公开(公告)号：US20080127197A1
公开(公告)日：2008-05-29
申请号：US12027665
申请日：2008-02-07
申请人： CHRISTOPHER M. ABERNATHY , William E. Burky , James A. Van Norstrand , Albert T. Williams
发明人： CHRISTOPHER M. ABERNATHY , William E. Burky , James A. Van Norstrand , Albert T. Williams
IPC分类号： G06F9/50
CPC分类号： G06F9/30098 , G06F9/3004 , G06F9/30094 , G06F9/30101 , G06F9/384 , G06F9/3857 , G06F9/3885
摘要： A method and processor for performing on-demand scratch register reallocation by dynamically adjusting the number of scratch registers from within the pool of rename registers includes initially allocating from a set of physical registers one or more architected registers and a pool of one or more rename registers and allocating from the pool of rename registers an initial number of scratch registers for storing microcode operands. In response to detecting that a fetched instruction requires an additional scratch register beyond the initial number, a selected physical register is reallocated from among the pool of rename registers as the additional scratch register, and a flag is set to indicate the rename register is allocated as the additional scratch register. In response to determining that the additional scratch register is no longer needed, the additional scratch register is deallocated and the flag is reset, such that the selected physical register returns to the pool of rename registers.
摘要翻译：用于通过从重命名寄存器池内动态地调整临时寄存器的数量来执行按需暂存寄存器重新分配的方法和处理器包括：首先从一组物理寄存器分配一个或多个架构寄存器和一个或多个重命名寄存器池并从重命名寄存器池分配初始数量的用于存储微代码操作数的暂存寄存器。响应于检测到所取出的指令需要超出初始号码的额外的临时寄存器，所选择的物理寄存器作为额外的临时寄存器从重命名寄存器池中重新分配，并且将标志设置为指示重命名寄存器被分配为额外的擦写寄存器。响应于确定不再需要额外的临时寄存器，额外的临时寄存器被解除分配并且该标志被复位，使得所选择的物理寄存器返回到重命名寄存器池。

10. 发明授权

US07991979B2 Issuing load-dependent instructions in an issue queue in a processing unit of a data processing system 有权
标题翻译：在数据处理系统的处理单元中的发布队列中发出与负载相关的指令
公开(公告)号：US07991979B2
公开(公告)日：2011-08-02
申请号：US12236175
申请日：2008-09-23
申请人： Christopher M. Abernathy , Mary D Brown , William E. Burky , Todd A. Venton
发明人： Christopher M. Abernathy , Mary D Brown , William E. Burky , Todd A. Venton
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/3824 , G06F9/3838
摘要： A system and method for issuing load-dependent instructions in an issue queue in a processing unit. A load miss queue is provided. The load miss queue comprises a physical address field, an issue queue position field, a valid identifier field, a source identifier field, and a data type field. A load instruction that misses a first level cache is dispatched, and both the physical address field and the data type field are set. A load-dependent instruction is identified. In response to identifying the load-dependent instruction, each of the issue queue position field, valid identifier field, and source identifier field are set. If the issue queue position field refers to a flushed instruction, the valid identifier field is cleared. The load instruction is recycled, and a value of the valid identifier field is determined. The load-dependent instruction is then selected for issue on a next processing cycle independent of an age of the load-dependent instruction.
摘要翻译：一种用于在处理单元中的发布队列中发布负载相关指令的系统和方法。提供了一个加载缺失队列。负载遗漏队列包括物理地址字段，发布队列位置字段，有效标识符字段，源标识符字段和数据类型字段。调度丢失第一级缓存的加载指令，同时设置物理地址字段和数据类型字段。识别负载相关的指令。响应于识别负载相关指令，设置每个发布队列位置字段，有效标识符字段和源标识符字段。如果问题队列位置字段引用了刷新指令，则清除有效的标识符字段。加载指令被回收，确定有效标识符字段的值。然后选择负载相关的指令用于在下一个处理周期中发出独立于负载相关指令的年龄。

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