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    • 5. 发明授权
    • System and method for detecting integrated circuit pattern defects
    • 检测集成电路图案缺陷的系统和方法
    • US07558419B1
    • 2009-07-07
    • US10917060
    • 2004-08-12
    • Jun YeYu CaoR. Fabian Pease
    • Jun YeYu CaoR. Fabian Pease
    • G06K9/00
    • G06T7/001G03F1/84G06T2207/30148
    • There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of, and system for inspecting integrated circuits, including, for example, patterns projected, provided or formed on a wafer using photomasks, or patterns on the photomask itself. The inspection system and technique of this aspect includes first identifying, determining and/or detecting areas and/or patterns that are potentially defective by removing, filtering and/or eliminating from a set of potential defects any and/or all typical, regular or normal patterns. The identification, determination and/or detection of potential defects may be performed relatively quickly by a rapidly executing algorithm. In this way, a first or “coarse” analysis is performed rapidly and some, many, all or substantially all of the regular, normal or typical patterns are eliminated from further analysis. Thereafter, a second more detailed analysis is performed. This second analysis focuses on the set of potential defects that were identified, determined and/or detected during the first analysis of the photomask or wafer (i.e., the “coarse” analysis). The second analysis may be considerably a more detailed or a “fine” analysis relative to the first or “coarse” analysis. Indeed, in one embodiment, the second analysis may implement a more computational intensive process, without sacrificing throughput, since only a small portion of the photomask or wafer is inspected in the second analysis. In this way, the detailed analysis of the defect candidates may identify (i) all or substantially all of the actual defects and/or (ii) only the actual defects from the potential defects identified during the first analysis.
    • 这里描述和说明了许多发明。 在一个方面,本发明涉及用于检查集成电路的技术和系统,包括例如使用光掩模投影,提供或形成在晶片上的图案或光掩模本身上的图案。 该方面的检查系统和技术包括首先识别,确定和/或检测潜在缺陷的区域和/或图案,该区域和/或图案通过去除,过滤和/或从一组潜在的缺陷中消除任何和/或所有典型的,规则的或正常的 模式。 可能通过快速执行的算法相对较快地执行潜在缺陷的识别,确定和/或检测。 以这种方式,快速执行第一个或“粗略”分析,并从进一步的分析中消除一些,许多,全部或基本上所有常规,正常或典型的模式。 此后,进行第二更详细的分析。 该第二分析集中在在光掩模或晶片的第一次分析期间(即,“粗略”分析))中识别,确定和/或检测到的潜在缺陷集合。 第二次分析可能相对于第一次或“粗略”分析可能是更详细或“精细”的分析。 实际上,在一个实施例中,第二分析可以实现更加计算密集的过程,而不会牺牲吞吐量,因为在第二次分析中只检查了一小部分光掩模或晶片。 以这种方式,缺陷候选人的详细分析可以识别(i)所有或基本上所有的实际缺陷和/或(ii)仅在第一次分析期间识别的潜在缺陷的实际缺陷。