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1. 发明授权

US08826531B1 Method for making an integrated circuit substrate having laminated laser-embedded circuit layers 有权
标题翻译：制造具有层叠激光嵌入电路层的集成电路基板的方法
公开(公告)号：US08826531B1
公开(公告)日：2014-09-09
申请号：US11098995
申请日：2005-04-05
申请人： David Jon Hiner , Ronald Patrick Huemoeller , Sukianto Rusli
发明人： David Jon Hiner , Ronald Patrick Huemoeller , Sukianto Rusli
IPC分类号： H01R43/00 , H05K13/00
CPC分类号： H05K3/465 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48237 , H01L2924/15311 , H05K3/0035 , H05K3/1216 , H05K3/18 , H05K2201/0195 , H05K2203/063 , Y10T29/49117 , Y10T29/49126 , Y10T29/49155 , Y10T29/49169 , H01L2924/00014
摘要： A method for making an integrated circuit substrate having laminated laser-embedded circuit layers provides a multi-layer high-density mounting and interconnect structure for integrated circuits. A prepared substrate, which may be a rigid double-sided dielectric or film dielectric with conductive patterns plated, etched or printed on one or both sides is laminated with a thin-film dielectric on one or both sides. The thin-film is laser-ablated to form channels and via apertures and conductive material is plated or paste screened into the channels and apertures, forming a conductive interconnect pattern that is isolated by the channel sides and vias through to the conductive patterns on the prepared substrate. An integrated circuit die and external terminals can then be attached to the substrate, providing an integrated circuit having a high-density interconnect.
摘要翻译：用于制造具有层叠的激光嵌入电路层的集成电路基板的方法为集成电路提供了多层高密度安装和互连结构。制备的衬底，其可以是在一侧或两侧上镀有，蚀刻或印刷的导电图案的刚性双面电介质或膜电介质，其一面或两侧与薄膜电介质层压。薄膜被激光烧蚀以形成通道并且通孔，并且导电材料被电镀或糊化物屏蔽到通道和孔中，形成通过通道侧和通孔隔离的导电互连图案到制备的导电图案基质。然后可以将集成电路管芯和外部端子连接到衬底，从而提供具有高密度互连的集成电路。

2. 发明授权

US07923645B1 Metal etch stop fabrication method and structure 有权
标题翻译：金属蚀刻停止制造方法和结构
公开(公告)号：US07923645B1
公开(公告)日：2011-04-12
申请号：US11765806
申请日：2007-06-20
申请人： Ronald Patrick Huemoeller , Sukianto Rusli , Robert F. Darveaux
发明人： Ronald Patrick Huemoeller , Sukianto Rusli , Robert F. Darveaux
IPC分类号： H05K1/03
CPC分类号： H05K3/428 , H01L2224/48091 , H05K1/185 , H05K3/205 , H05K3/421 , H05K3/4658 , H05K2201/0394 , H05K2201/10674 , H05K2203/0361 , H05K2203/0384 , Y10T29/49117 , Y10T29/49126 , Y10T29/4913 , Y10T29/49147 , Y10T29/49149 , Y10T29/49155 , Y10T29/49204 , Y10T29/49222 , H01L2924/00014
摘要： A first patterned etch stop layer and a first patterned conductor layer are laminated by a dielectric material to a second patterned etch stop layer and a second patterned conductor layer. As the etch stop metal of the first and second patterned etch stop layers is selectively etchable compared to a conductor metal of the first and second patterned conductor layers, the first and second patterned etch stop layers provide an etch stop for substrate formation etch processes. In this manner, etching of the first and second patterned conductor layers is avoided insuring that impedance is controlled to within tight tolerance.
摘要翻译：第一图案化蚀刻停止层和第一图案化导体层通过电介质材料层压到第二图案化蚀刻停止层和第二图案化导体层。由于与第一和第二图案化导体层的导体金属相比，第一和第二图案化蚀刻停止层的蚀刻停止金属是可选择的可蚀刻的，所以第一和第二图案化蚀刻停止层提供用于衬底形成蚀刻工艺的蚀刻停止。以这种方式，避免了第一和第二图案化导体层的蚀刻，确保阻抗被控制在紧密公差内。

3. 发明授权

US07145238B1 Semiconductor package and substrate having multi-level vias 有权
标题翻译：具有多层通孔的半导体封装和衬底
公开(公告)号：US07145238B1
公开(公告)日：2006-12-05
申请号：US10839647
申请日：2004-05-05
申请人： Ronald Patrick Huemoeller , David Jon Hiner , Sukianto Rusli
发明人： Ronald Patrick Huemoeller , David Jon Hiner , Sukianto Rusli
IPC分类号： H01L23/48
CPC分类号： H01L23/49827 , H01L21/486 , H01L23/49822 , H01L24/48 , H01L2224/16 , H01L2224/16235 , H01L2224/48235 , H01L2924/00011 , H01L2924/00014 , H01L2924/01078 , H01L2924/15173 , H01L2924/15311 , H01L2224/0401 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package and substrate having multi-level plated vias provide a high density blind via solution at low incremental cost. Via are half-plated atop a circuit pattern and then a second via half is added to complete the via after isolation of elements of the circuit pattern. Successive resist pattern applications and etching are used to form a via tier atop a circuit pattern that is connected by a thin plane of metal. After the tier is deposited, the thin metal plane is etched to isolate the circuit pattern elements. Dielectric is then deposited and the top half of the via is deposited over the tier. The tier may have a larger or smaller diameter with respect to the other half of the via, so that the via halves may be properly registered. Tin plating may also be used to control the etching process to provide etching control.
摘要翻译：具有多层电镀通孔的半导体封装和衬底以低增量成本提供高密度盲孔解决方案。通孔在电路图案的顶部被半镀，然后添加第二通孔半部以在隔离电路图案的元件之后完成通孔。连续的抗蚀剂图案应用和蚀刻用于在通过金属薄层连接的电路图案之上形成通孔层。在层沉积之后，蚀刻薄金属平面以隔离电路图案元件。然后沉积介质，并将通孔的上半部分沉积在层上。层可以具有相对于通孔的另一半具有更大或更小的直径，使得通孔半部可以被适当地登记。也可以使用镀锡来控制蚀刻工艺以提供蚀刻控制。

4. 发明授权

US06967124B1 Imprinted integrated circuit substrate and method for imprinting an integrated circuit substrate 有权
标题翻译：印刷集成电路基板和印刷集成电路基板的方法
公开(公告)号：US06967124B1
公开(公告)日：2005-11-22
申请号：US09884193
申请日：2001-06-19
申请人： Ronald Patrick Huemoeller , Sukianto Rusli
发明人： Ronald Patrick Huemoeller , Sukianto Rusli
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50 , H05K1/05 , H05K1/18 , H05K3/06 , H05K3/10 , H05K3/44
CPC分类号： H01L21/486 , H01L21/4846 , H01L21/4857 , H01L21/4867 , H01L2224/05573 , H01L2224/11 , H01L2224/48091 , H01L2224/73257 , H01L2924/00014 , H05K1/056 , H05K1/182 , H05K3/062 , H05K3/107 , H05K3/445 , H05K2201/0397 , H05K2201/09036 , H05K2203/0108 , H01L2224/05599
摘要： A die-attach method and assembly using film and epoxy bonds speeds manufacturing for large die assemblies while providing improved bond characteristics. An adhesive film defining an epoxy flow mask is attached to the die or substrate, epoxy is dispensed within the epoxy flow mask area and the die is then bonded to the substrate. The film controls the flow of the epoxy, preventing spillover. Additionally, the epoxy area can be made small with respect to the die size, reducing the time required to dispense the epoxy and reducing the amount of epoxy material required.
摘要翻译：使用膜和环氧树脂粘合剂的芯片附接方法和组装加速了大型模具组件的制造，同时提供了改善的粘合特性。将限定环氧流量掩模的粘合剂膜附着到模具或基底上，将环氧树脂分配在环氧树脂流动掩模区域内，然后将模具结合到基底上。该胶片控制环氧树脂的流动，防止外溢。此外，相对于模具尺寸，可以使环氧树脂面积较小，减少了分配环氧树脂所需的时间并减少了所需的环氧树脂材料的量。

5. 发明授权

US08176628B1 Protruding post substrate package structure and method 有权
标题翻译：突出后基板封装结构和方法
公开(公告)号：US08176628B1
公开(公告)日：2012-05-15
申请号：US12342839
申请日：2008-12-23
申请人： Sukianto Rusli , Ronald Patrick Huemoeller , David Hiner
发明人： Sukianto Rusli , Ronald Patrick Huemoeller , David Hiner
IPC分类号： H01K3/10
CPC分类号： H01L23/49816 , H01L21/4853 , H01L24/48 , H01L2224/05571 , H01L2224/05573 , H01L2224/16225 , H01L2224/16227 , H01L2224/48227 , H01L2224/73265 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H05K3/4007 , H05K2203/0376 , Y10T29/49165 , H01L2924/00 , H01L2224/05599 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： In accordance with one embodiment, a method of forming a protruding post substrate package includes applying a dielectric layer to a carrier. Via apertures are formed in the dielectric layer. Carrier cavities are formed in the carrier using the dielectric layer as a mask. The carrier cavities are lined with a first metal, the first metal being selectively etchable compared to the carrier. After encapsulation of an electronic component with an encapsulant, the carrier is removed such that protruding posts including the first metal protrude outward from a first surface of the dielectric layer.
摘要翻译：根据一个实施例，形成突出的后衬底封装的方法包括将介电层施加到载体上。在电介质层中形成通孔。使用电介质层作为掩模在载体中形成载体空穴。载体空腔内衬有第一金属，与载体相比，第一金属可选择性地蚀刻。在用密封剂封装电子部件之后，移除载体，使得包括第一金属的突出柱从电介质层的第一表面向外突出。

6. 发明授权

US07832097B1 Shielded trace structure and fabrication method 有权
标题翻译：屏蔽迹线结构及制作方法
公开(公告)号：US07832097B1
公开(公告)日：2010-11-16
申请号：US12018435
申请日：2008-01-23
申请人： Ronald Patrick Huemoeller , Sukianto Rusli , Nozad Karim
发明人： Ronald Patrick Huemoeller , Sukianto Rusli , Nozad Karim
IPC分类号： H01K3/10
CPC分类号： H05K3/027 , H01L2224/16227 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H05K1/0219 , H05K1/0221 , H05K1/116 , H05K3/0026 , H05K3/108 , H05K3/205 , H05K3/4644 , H05K2201/0715 , H05K2201/09236 , H05K2203/308 , Y10T29/49124 , Y10T29/49147 , Y10T29/49155 , Y10T29/49165 , Y10T29/49167 , Y10T29/49218 , H01L2924/00012
摘要： A method includes forming a patterned sacrificial layer on a first carrier and a patterned trace layer on the patterned sacrificial layer. The patterned sacrificial layer and the patterned trace layer are laminated to a dielectric material. The first carrier and the patterned sacrificial layer are removed creating sacrificial layer gaps above the patterned trace layer. The sacrificial layer gaps are filled with a trace layer isolation dielectric material. Shield trenches are laser-ablated within the dielectric material and on opposite sides of a signal trace of the patterned trace layer. The shield trenches are filled with an electrically conductive material to form shield walls. The electrically conductive material is patterned to form a shield top. The shield top, the shield walls, and a second carrier form a bias shield around the signal trace.
摘要翻译：一种方法包括在图案化的牺牲层上在第一载体上形成图案化的牺牲层和图案化的迹线层。图案化的牺牲层和图案化的迹线层被层压到电介质材料上。去除第一载体和图案化牺牲层，在图案化的迹线层上方产生牺牲层间隙。牺牲层间隙用痕量隔离绝缘材料填充。屏蔽沟槽在电介质材料内和图案化迹线层的信号迹线的相对侧被激光烧蚀。屏蔽沟槽填充有导电材料以形成屏蔽壁。将导电材料图案化以形成屏蔽顶部。屏蔽顶部，屏蔽壁和第二载体在信号迹线周围形成偏置屏蔽。

7. 发明授权

US07632753B1 Wafer level package utilizing laser-activated dielectric material 有权
标题翻译：晶圆级封装采用激光激活电介质材料
公开(公告)号：US07632753B1
公开(公告)日：2009-12-15
申请号：US11867293
申请日：2007-10-04
申请人： Sukianto Rusli , Bob Shih-Wei Kuo , Ronald Patrick Huemoeller
发明人： Sukianto Rusli , Bob Shih-Wei Kuo , Ronald Patrick Huemoeller
IPC分类号： H01L21/4763 , H01L21/44 , H01L23/04 , H01L23/52 , H01L23/48 , H01L29/40 , H01L23/538
CPC分类号： H01L23/525 , H01L21/76804 , H01L21/76843 , H01L21/76874 , H01L21/76879 , H01L23/5328 , H01L23/5329 , H01L2224/05001 , H01L2224/05026 , H01L2224/11 , H01L2224/13025 , H01L2924/00014 , H01L2924/0002 , H01L2924/12044 , H01L2924/00 , H01L2224/05599 , H01L2224/05099
摘要： A method of forming a wafer level package includes attaching a laser-activated dielectric material to an integrated circuit substrate to form an assembly, the integrated circuit substrate including a plurality of electronic components having terminals on first surfaces thereof. The laser-activated dielectric material is laser activated and ablated with a laser to form laser-ablated artifacts in the laser-activated dielectric material and simultaneously to form an electrically conductive laser-activated layer lining the laser-ablated artifacts. The laser-ablated artifacts are filled using an electroless plating process in which an electrically conductive filler material is selectively plated on the laser-activated layer to form an embedded circuit pattern within the laser-activated dielectric material.
摘要翻译：形成晶片级封装的方法包括将激光激活介电材料附接到集成电路基板以形成组件，所述集成电路基板包括多个电子部件，所述电子部件在其第一表面上具有端子。激光激活的介电材料被激光激活并用激光烧蚀，以在激光激活的电介质材料中形成激光烧蚀的伪影，同时形成衬在激光烧蚀的伪像上的导电激光激活层。使用化学镀方法填充激光烧蚀的人造物，其中导电填料材料选择性地电镀在激光激活层上，以在激光激活的电介质材料内形成嵌入的电路图案。

8. 发明授权

US07501338B1 Semiconductor package substrate fabrication method 有权
标题翻译：半导体封装衬底制造方法
公开(公告)号：US07501338B1
公开(公告)日：2009-03-10
申请号：US11527104
申请日：2006-09-25
申请人： Ronald Patrick Huemoeller , David Jon Hiner , Sukianto Rusli , Richard Sheridan
发明人： Ronald Patrick Huemoeller , David Jon Hiner , Sukianto Rusli , Richard Sheridan
IPC分类号： H01L21/4763
CPC分类号： H01L21/4857 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2924/01078 , H01L2924/01079 , H01L2924/15311 , H01L2924/19041 , H05K3/0032 , H05K3/0035 , H05K3/107 , H05K3/386 , H05K3/423 , H05K3/465 , H05K3/4664 , H05K7/1061 , H05K2201/0195 , H05K2201/09036 , H01L2924/00014
摘要： An integrated circuit substrate having embedded lands with etching and plating control features provides improved manufacture of a high-density and low cost mounting and interconnect structure for integrated circuits. The integrated circuit substrate is formed by generating channels in a dielectric material, adding conductive material to fill the channels and then planarizing the conductive material, so that conductors are formed beneath the surface of the dielectric material. Lands are formed with feature shapes that reduce a dimpling effect at etching and/or an over-deposit of material during plating, both due to increased current density at the relatively larger land areas. Feature shapes may be a grid formed with line sizes similar to those employed to form conductive interconnects, so that all features on the substrate have essentially the same line width. Alternatively, and in particular for circular pads such as solderball attach lands, sub-features may be radially disposed around a central circular area and connected with channels formed as interconnect lines that connect the sub-features to the central circular area. Connection of the lands may be made using vias or by other conductive channels forming electrical interconnect lines.
摘要翻译：具有带蚀刻和电镀控制特征的嵌入式焊盘的集成电路基板提供了用于集成电路的高密度和低成本安装和互连结构的改进制造。通过在电介质材料中产生通道形成集成电路衬底，添加导电材料以填充沟道，然后使导电材料平坦化，从而在电介质材料的表面之下形成导体。由于在相对较大的陆地区域处的电流密度增加，在地面处形成有减少蚀刻时的凹坑效应和/或电镀期间材料过度沉积的特征形状。特征形状可以是形成为具有与用于形成导电互连的线尺寸相似的线尺寸的网格，使得衬底上的所有特征具有基本上相同的线宽。或者，并且特别是对于诸如焊球附着平台的圆形焊盘，子特征可以径向设置在中心圆形区域周围并且与形成为将子特征连接到中心圆形区域的互连线形成的通道连接。可以使用通孔或形成电互连线的其它导电通道来进行焊盘的连接。

9. 发明授权

US07399661B2 Method for making an integrated circuit substrate having embedded back-side access conductors and vias 有权
标题翻译：制造具有嵌入式背面存取导体和通路的集成电路基板的方法
公开(公告)号：US07399661B2
公开(公告)日：2008-07-15
申请号：US10947124
申请日：2004-09-22
申请人： David Jon Hiner , Ronald Patrick Huemoeller , Sukianto Rusli
发明人： David Jon Hiner , Ronald Patrick Huemoeller , Sukianto Rusli
IPC分类号： H01L21/00 , H01L23/04 , H05K1/11
CPC分类号： H01L21/4857 , H05K3/0035 , H05K3/423 , H05K7/1061
摘要： A method for making an integrated circuit substrate having embedded back-side access conductors and vias provides a high-density mounting and interconnect structure for integrated circuits that is compatible with etched, plated or printed pre-manufactured substrate components. A circuit board or film having a pre-plated, etched or printed circuit, for example a rigid substrate having a Ball Grid Array (BGA) ball-attach pattern, is laser perforated to produce blind vias and/or conductive patterns that provide contact through to conductors of the prefabricated circuit board or film. Existing circuit board and substrate technology is thereby made compatible with laser-embedding technologies, providing the low-cost advantages of existing etching, plating and printing technologies along with a high conductor density associated with laser-embedded circuit technologies.
摘要翻译：用于制造具有嵌入式背面存取导体和通孔的集成电路基板的方法为与蚀刻的，电镀的或印刷的预制衬底部件兼容的集成电路提供了高密度的安装和互连结构。具有预镀，蚀刻或印刷电路（例如具有球栅阵列（BGA）球附着图案的刚性基板）的电路板或膜被激光穿孔以产生盲孔和/或导电图案，其提供接触通过到预制电路板或电影的导体。因此，现有的电路板和衬底技术与激光嵌入技术相兼容，提供了现有蚀刻，电镀和印刷技术的低成本优势以及与激光嵌入式电路技术相关的高导体密度。

10. 发明授权

US07028400B1 Integrated circuit substrate having laser-exposed terminals 有权
标题翻译：具有激光曝光端子的集成电路基板
公开(公告)号：US07028400B1
公开(公告)日：2006-04-18
申请号：US10603878
申请日：2003-06-24
申请人： David Jon Hiner , Ronald Patrick Huemoeller , Sukianto Rusli
发明人： David Jon Hiner , Ronald Patrick Huemoeller , Sukianto Rusli
IPC分类号： H01K3/10
CPC分类号： H05K3/4007 , H05K1/056 , H05K3/0035 , H05K3/107 , H05K3/243 , H05K3/244 , H05K3/28 , H05K3/386 , H05K2201/0394 , H05K2201/09472 , H05K2203/041 , H05K2203/072 , Y10T29/49117 , Y10T29/4913 , Y10T29/49144 , Y10T29/49165
摘要： An integrated circuit substrate having laser-exposed terminals provides a high-density and low cost mounting and interconnect structure for integrated circuits. The laser-exposed terminals can further provide a selective plating feature by using a dielectric layer of the substrate to prevent plating terminal conductors and subsequently exposing the terminals via laser ablation. A metal layer may be coated on one or both sides with a dielectric material, conductive material embedded within the dielectric to form conductive interconnects and then coating over the conductive material with a conformal protective coating. The protectant is then laser-ablated to expose the terminals. A dielectric film having a metal layer laminated on one side may be etched and plated. Terminals are then laser-exposed from the back side of the metal layer exposing unplated terminals.
摘要翻译：具有激光曝光端子的集成电路基板为集成电路提供高密度且低成本的安装和互连结构。激光曝光端子可以通过使用基板的电介质层来进一步提供选择性电镀特征，以防止电镀端子导体，并随后通过激光烧蚀暴露端子。金属层可以在一侧或两侧上用介电材料涂覆，导电材料嵌入电介质内以形成导电互连，然后用保形涂层涂覆在导电材料上。然后将保护剂激光烧蚀以暴露终端。可以对具有层叠在一侧的金属层的电介质膜进行蚀刻和电镀。然后将端子从金属层的背面激光曝光，暴露未镀层的端子。

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