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    • 5. 发明申请
    • METHOD AND APPARATUS FOR MEASURING COMMUNICATIONS LINK QUALITY
    • 用于测量通信链路质量的方法和装置
    • US20060223478A1
    • 2006-10-05
    • US11424209
    • 2006-06-14
    • Juan-Antonio CarballoJeffrey BurnsIvan Vo
    • Juan-Antonio CarballoJeffrey BurnsIvan Vo
    • H04B1/00H04B1/10H04B15/00
    • H04B17/20
    • A method and apparatus for measuring communications link quality provides accurate on-chip estimation of the difficulty of achieving a particular bit error rate (BER) for a communications link. A low cost/complexity accumulator circuit connected to internal signals from a clock/data recovery (CDR) circuit provides a measure of high frequency and low frequency jitter in a received signal. The low frequency jitter measurement is used to correct the high frequency jitter measurement which may otherwise contain error. The corrected output may be used to adjust operational characteristics of the link or otherwise evaluate the link for operating margin. The correction may be performed by subtracting a portion of the low frequency jitter measurement from the measured high frequency jitter, or the value of the low frequency jitter measurement may be used to select between two or more correction factors that are then applied to the high frequency jitter measurement.
    • 用于测量通信链路质量的方法和装置提供对实现通信链路的特定误码率(BER)的难度的精确的片上估计。 连接到来自时钟/数据恢复(CDR)电路的内部信号的低成本/复杂度的累加器电路提供接收信号中的高频和低频抖动的量度。 低频抖动测量用于校正可能包含错误的高频抖动测量。 校正的输出可用于调整链路的操作特性或以其他方式评估链路的操作裕度。 可以通过从测量的高频抖动中减去一部分低频抖动测量来执行校正,或者可以使用低频抖动测量的值来选择两个或更多个校正因子,然后将其应用于高频抖动 抖动测量。
    • 6. 发明授权
    • Processor and method for generating less than (LT), Greater than (GT), and equal to (EQ) condition code bits concurrent with a logical or complex operation
    • 用于生成小于(LT),大于(GT)和等于(EQ)条件码位的处理器和方法与逻辑或复杂操作并发
    • US06237085B1
    • 2001-05-22
    • US09207482
    • 1998-12-08
    • Jeffrey BurnsSang Hoo DhongKevin John Nowka
    • Jeffrey BurnsSang Hoo DhongKevin John Nowka
    • G06F9305
    • G06F9/30094G06F7/026G06F9/3875
    • A processor includes execution resources and condition code logic. The execution resources execute an arithmetic or logical instruction by arithmetically or logically combining at least two operands. Concurrent with the execution of the arithmetic or logical instruction by the execution resources, the condition code logic determines less than, greater than, and equal to condition code bits associated with the result of the arithmetic or logical instruction. In one embodiment, the condition code logic includes a single computation stage that receives as inputs individual bit values of bit positions within first and second operands and logically combines the individual bit values. The single computation stage outputs, for each bit position, propagate, generate, and kill signals that collectively indicate values for the less than, greater than, and equal to condition code bits. One or more merging stages coupled to the computation stage then merge the propagate, generate, and kill signals into output signals that set the condition code bits. The condition code logic is also capable of receiving externally computed condition code bits associated with complex instructions and utilizing such condition code bits to produce the output signals.
    • 处理器包括执行资源和条件代码逻辑。 执行资源通过算术或逻辑地组合至少两个操作数来执行算术或逻辑指令。 与执行资源执行算术或逻辑指令同时,条件代码逻辑确定小于,大于和等于与算术或逻辑指令的结果相关联的条件码位。 在一个实施例中,条件码逻辑包括单个计算阶段,其接收第一和第二操作数中的比特位置的各个比特值作为输入,并逻辑地组合各个比特值。 对于每个位位置,单个计算级输出传播,产生和去除共同指示小于,大于和等于条件码位的值的信号。 耦合到计算阶段的一个或多个合并阶段然后将传播,生成和终止信号合并到设置条件码位的输出信号中。 条件代码逻辑还能够接收与复杂指令相关联的外部计算的条件码位,并利用这些条件码位产生输出信号。
    • 10. 发明申请
    • Binary options on an organized exchange and the systems and methods for trading the same
    • 有组织的交易所的二元期权和交易的系统和方法
    • US20050165669A1
    • 2005-07-28
    • US11017191
    • 2004-12-21
    • Donato MontanaroMichael BickfordJeffrey BurnsChristopher MascialeScott Ebner
    • Donato MontanaroMichael BickfordJeffrey BurnsChristopher MascialeScott Ebner
    • G06F17/60
    • G06Q40/04
    • The invention relates to financial systems and methods for trading fixed return options on secondary markets such as stock exchanges. A financial system of the invention includes both an electronic order delivery and execution system and/or an on-floor trading auction, configured to provide an exchange-traded environment. The financial system also includes at least one fixed return option or binary option traded through an exchange's order delivery and execution system or on-floor trading auction, whereby such trading environment provides an open market. The system of the invention makes the trading of fixed return options or binary options possible via a unique use of the existing symbology schemes for standardized (non-binary) options, such that “Finish High” options are processed as calls, and “Finish Low” options are processed as puts, enabling these newly standardized binary options to be both recognized and accepted as standardized option contracts by existing trading, clearance, margin and settlement systems, while also enabling these options to be differentiated from traditional standardized options, and appropriately segregated for different treatment than the typical standardized option forms. The system employs a novel method for calculating the closing settlement value for securities underlying fixed return options or binary options in order to maintain a fair and orderly trading environment for these instruments on an organized exchange.
    • 本发明涉及在诸如证券交易所的二级市场上交易固定回报期权的金融系统和方法。 本发明的金融系统包括电子订单交付和执行系统和/或地板上交易拍卖,被配置为提供交易所交易的环境。 金融体系还包括通过交易所的订单交付和执行系统或楼内交易拍卖交易的至少一个固定回报期权或二元期权,由此这种交易环境提供公开市场。 本发明的系统通过独特地使用现有的用于标准化(非二进制)选项的符号体系来进行固定返回选项或二进制选项的交易,使得“完成高”选项被处理为调用,并且“完成低 “期权作为期权进行处理,使这些新标准化的二元期权既可以被现有的交易,清算,保证金和结算系统认可并接受为标准化期权合约,同时也可以将这些期权与传统的标准期权相区分, 用于不同于典型的标准化选项形式的处理。 该系统采用新颖的方法计算固定回报期权或二元期权的证券的收盘结算价值,以便在有组织的交易所上保持这些工具的公平有序的交易环境。